March C address matching algorithm for SDRAM memory test
By using the March C address matching algorithm in memory testing, combined with the connection between SDRAM and DSP, the problem of excessive testing time in the existing technology is solved, and efficient and fast fault detection and verification are achieved.
Patent Information
- Application Number
- CN202411472052.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-21
- Publication Date
- 2025-03-07
AI Technical Summary
Existing memory testing methods mainly focus on failure rate, and cannot shorten the detection time while meeting a certain fault coverage rate, resulting in too long testing time.
The March C address matching algorithm is used to test the SDRAM memory. This method uses the connection between SDRAM and the digital signal processing chip DSP to test it using test instructions, addresses and data to achieve rapid detection and verification of all units.
It realizes that while meeting higher failure rate detection, it significantly shortens memory test time and improves testing efficiency and reliability.
Smart Images
Figure CN119580812A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the field of memory, and in particular, relates to a testing method of a synchronous dynamic random-access memory (Synchronous Dynamic Random-Access Memory, SDRAM for short). Background Art
[0002] With the advancement of microelectronics technology and the development of semiconductor integrated circuits, higher requirements are placed on circuit testing, and memory testing has become an important part of integrated circuit testing.
[0003] Memory is mainly used to store data, instructions, programs and other information, and is widely used in industry, communications, home appliances, computers and other electronic equipment. The quality of memory testing methods affects the stability and reliability of the storage system, so memory testing technology has always been the focus of research. In order to meet the needs of mass testing of electronic storage devices, various memory testing methods have emerged.
[0004] In the prior art, memory testing methods are mainly focused on testing the failure rate, but this is not in line with actual applications. Testing should be able to shorten the testing time while meeting a certain fault coverage. Therefore, a memory testing method that can detect a higher failure rate and reduce the testing time is needed. Summary of the invention
[0005] In order to solve the problems existing in the background technology, the present invention proposes a March C address matching algorithm for SDRAM memory test.
[0006] According to the present invention, a method for testing SDRAM is provided, comprising: testing the entire SDRAM memory; wherein the SDRAM is connected to a digital signal processing chip DSP; and testing all memory units according to the testing method.
[0007] Further, the memory is tested, including: obtaining a test instruction sent by a host computer; obtaining an address of an SDRAM test unit; obtaining test data used in the SDRAM test;
[0008] Further, according to the above, testing all the SDRAM units includes: writing the test data into the corresponding test address units according to the test method.
[0009] Furthermore, according to the above, after all the units of the SDRAM are tested, it is also necessary to read the test data from the address unit and verify the read data.
[0010] Furthermore, after recording the verification result, it is also necessary to send the verification result to the host computer module, wherein the DSP sends the data to the host computer through the serial port.
[0011] Furthermore, after receiving the test result, the host computer module further includes: displaying the SDRAM test qualified result. BRIEF DESCRIPTION OF THE DRAWINGS
[0012] Figure 1 Schematic diagram of the structure of the SDRAM testing method according to an embodiment of the present invention.
[0013] Figure 2 FIG. 4 is a flow chart of an SDRAM testing method according to an embodiment of the present invention. DETAILED DESCRIPTION
[0014] In order to make the purpose, technical solutions and advantages of this specification clearer, this embodiment provides a March C address matching algorithm for SDRAM memory testing to clearly and completely describe the present invention.
[0015] Figure 1 A schematic diagram of the structure of an SDRAM testing method according to an embodiment of the present invention; Figure 2 Flow chart of the SDRAM test method of the embodiment of the present invention; Figure 2 The present invention provides a March C address matching algorithm for SDRAM memory testing, comprising the following steps:
[0016] Step S1, preparation for system testing.
[0017] Step S2, initializing configuration items, connecting the host computer to the DSP via the serial port, configuring test data for the DSP, and connecting the SDRAM and DSP modules.
[0018] Step S3: The host computer sends a test instruction to the DSP, notifying the DSP that data writing and reading tests can be performed.
[0019] Step S4, DSP determines whether the test instruction is correct. If the instruction is wrong, it notifies the host computer to resend the test instruction after waiting timeout.
[0020] Step S5: The DSP receives the correct test instruction and executes the established test algorithm according to the user configuration.
[0021] Step S6, after completing the above address test on the entire SDRAM, record the correct test unit and the wrong test unit according to the verification result, save the accuracy of the test unit, and determine whether it is within an acceptable range.
[0022] Step S7, DSP sends the test result to the host computer through the serial port. If it is within the acceptable range, it will be displayed as normal; if it is not within the range, it will be displayed as a fault.
[0023] Step S8: SDRAM test is completed.
[0024] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, and they should be covered by the protection scope of the present invention.
Claims
1. A March C address matching algorithm for SDRAM memory testing, characterized in that: include: A host computer, a DSP module and an SDRAM memory, wherein the host computer and the digital signal processing chip DSP are connected via a serial port bus.
2. The method according to claim 1, characterized in that: Test all SDRAM memory cells: Get the address space range of the memory cells; Get the test data and methods used in the test.
3. The method according to claim 2, characterized in that Get test instructions to test the memory, including: When the DSP receives the test instruction sent by the host computer, it writes the storage data to the specified address of the memory.
4. The method according to claim 3, characterized in that After writing data to the specified address of the memory, it also includes: Read data from the specified address. Verify the read data and record the verification data.
5. The method according to claim 4, characterized in that After all tests and verifications are completed, the host computer module needs to send the verification result value.
6. The method according to claim 5, characterized in that The host computer obtains the verification value and needs to determine whether the tested memory is qualified and display it.