Structure and method to maximize contact density across cavity

Abstract

The invention relates to a structure and a method to maximize contact density across a cavity. Novel tools and techniques are provided for implementing a semiconductor package or chip package, and more particularly, methods, systems, and apparatus are provided for implementing a semiconductor package or chip package including one or more channel vias. In various embodiments, an apparatus includes: a first layer including a channel; a first via extending through the first layer to a first surface of the channel; and a wire connecting the first through hole to a pad. In some cases, the first surface is located at a bottom of the channel.

Description

[0001] CROSS REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. patent application No. 63 / 581,203, filed on September 7, 2023 by Jeremy Theil et al., entitled “Structures and Methods to Maximize Contact Density Across Cavities” (“the '203 application”), the disclosure of which is incorporated herein by reference in its entirety for all purposes.

[0003] Copyright Notice

[0004] A portion of the disclosure of this patent document contains material that is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the U.S. Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever. Technical Field

[0005] The present disclosure generally relates to methods, systems, and apparatus for implementing a semiconductor device including a channel having one or more vias. Background Art

[0006] When dealing with semiconductor devices that have channels, cavities, or apertures present therein, there are some limitations regarding the routing of traces or vias due to the presence of engineered channels, cavities, or apertures within the semiconductor device. Examples of situations where the semiconductor device includes channels, cavities, or apertures include where the semiconductor device includes one or more cooling plates (e.g., fluid cooling plates, etc.) across which signals (e.g., electrical signals, etc.) need to be passed, or one or more vacuum cavities for sensors and transducers.

[0007] Through substrate vias (TSVs) are often used to pass signals through a semiconductor device from or toward one or more layers or dies. However, the number, quantity, or density of TSVs in a semiconductor device or one or more regions of a semiconductor device in which one or more trenches, cavities, or voids are formed may be limited.

[0008] Therefore, there is a need for a more robust and scalable solution for implementing semiconductor packages and chip packages having a channel.Therefore, methods, systems and apparatus are provided for implementing a semiconductor package or chip package including a via extending through a layer to a bottom surface of a channel. Summary of the invention

[0009] In one aspect, the present disclosure relates to a semiconductor device comprising: a first layer comprising a channel; a first via extending through the first layer to a first surface of the channel, wherein the first surface is located at a bottom of the channel; and a line connecting the first via to a pad.

[0010] In another aspect, the present disclosure relates to a semiconductor device comprising: a via array including at least one first via extending through a layer to a bottom of a channel; and a line extending along a portion of the channel and connecting the at least one first via to a pad.

[0011] In another aspect, the present disclosure relates to a method of manufacturing a semiconductor device, the method comprising: forming a through hole extending through a first layer; forming a channel in the first layer to expose a first surface of the through hole, wherein the first surface of the through hole is exposed on a bottom surface of the channel; and forming a line extending from the first surface of the through hole and configured to connect the through hole to a pad. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] A further understanding of the nature and advantages of particular embodiments may be achieved by reference to the remainder of the specification and to the drawings, in which like reference numerals are used to refer to similar components. In some instances, a sub-label is associated with a reference numeral to identify one of a plurality of similar components. When a reference numeral is mentioned without specific reference to an existing sub-label, it is intended to refer to all such plurality of similar components.

[0013] Figure 1 is a schematic cross-sectional view of an embodiment of a semiconductor device having one or more channel vias according to various embodiments;

[0014] Figure 2 is a top view of a bottom portion of a substrate having one or more trench vias according to various embodiments;

[0015] Figure 3A and 3B According to various embodiments Figure 2 A schematic cross-sectional view of a bottom portion of a substrate;

[0016] Figure 4 is a top view of a bottom portion of a substrate having one or more trench vias according to various embodiments;

[0017] Figure 5 is a top view of a bottom portion of a substrate having one or more trench vias according to various embodiments;

[0018] Figure 6 is a top view of a bottom portion of a substrate having one or more trench vias according to various embodiments;

[0019] Fig. 7A According to various embodiments, one or more dielectric layers Figure 2 A schematic cross-sectional view of a bottom portion of a substrate;

[0020] Figure 7B According to various embodiments, one or more dielectric layers Figure 2 a top view of a bottom portion of a substrate;

[0021] Fig. 8A and 8B are schematic cross-sectional views of various embodiments of semiconductor devices having one or more trench vias according to various embodiments;

[0022] Fig. 9 is a flow chart of a method of fabricating a semiconductor device having one or more trench vias according to various embodiments;

[0023] Fig.10 is another flow chart of a method of fabricating a semiconductor device having one or more trench vias according to various embodiments;

[0024] Figures 11A to 11K According to various embodiments, Fig.10 A schematic cross-sectional view of a semiconductor device formed by the steps described in;

[0025] Fig.12 is another flow chart of a method of fabricating a semiconductor device having one or more trench vias according to various embodiments; and

[0026] Fig.13 is used Fig.12 A schematic cross-sectional view of a bottom portion of a substrate formed by the method. DETAILED DESCRIPTION

[0027] Various embodiments are described herein that provide tools and techniques for implementing semiconductor packages or chip packages that include one or more channels.

[0028] In a first aspect, a semiconductor device includes: a first layer including a channel; a first via extending through the first layer to a first surface of the channel; and a line connecting the first via to a pad. In some cases, the first surface may be located at a bottom of the channel.

[0029] In some embodiments, the pad may be located on the ridge of the channel. The wire may extend along a portion of the first wall of the channel to connect to the pad. The first wall of the channel may be inclined between about 20 degrees and about 87 degrees. In some embodiments, the second layer may be located between the first wall of the channel and the wire. In various examples, the ridge further includes a second through hole extending to a second surface of the ridge. The second surface may be located at the top of the ridge. The diameter of the first through hole may be smaller than the diameter of the second through hole.

[0030] In various examples, a second layer may be partially formed on the first layer to encapsulate at least one of a top of the first via or connecting the first via to the line of the pad.

[0031] In some cases, the channel includes a fluid. A second layer may be formed at a location to encapsulate a portion of the wire. The location may be selected to prevent the portion of the wire from contacting the fluid in the channel.

[0032] In various embodiments, the spacer is located on top of the ridge of the channel.The semiconductor device further includes a second layer encapsulating the line, a third layer encapsulating the spacer on top of the ridge, and a top surface of the second layer may be lower than a top surface of the third layer.

[0033] In another aspect, a semiconductor device may include: a via array including at least one first via extending through a layer to a bottom of a channel; and a line extending along a portion of the channel and connecting the at least one first via to a pad. In various cases, the pad may be located on a ridge of the channel.

[0034] In some examples, the via array includes two or more vias arranged in two or more columns or two or more rows along the bottom of the channel.The via array may include at least one second via extending through the layer to a top of a ridge of the channel.

[0035] In some embodiments, the shim includes a zero-clearance bondable surface.

[0036] In yet another aspect, a method of manufacturing a semiconductor device may include: forming a via extending through a first layer; forming a trench in the first layer to expose a first surface of the via; and forming a line extending from the first surface of the via and configured to connect the via to a pad. In some cases, the first surface of the via is exposed on a bottom surface of the trench.

[0037] In various cases, the method may include, after forming the channel and before forming the line, forming a second layer on top of the first layer including the channel. The second layer may be a dielectric layer. The method may also include, after forming the line, forming a third layer on top of the line. The third layer may be a dielectric layer.

[0038] In some examples, forming the wire further includes forming the wire to extend from the first surface of the via to the pad on a ridge of the channel. The wire may extend along a portion of a wall of the channel to connect to the pad.

[0039] In the following description, for the purpose of explanation, numerous details are set forth to provide a thorough understanding of the described embodiments. However, it should be apparent to those skilled in the art that other embodiments may be practiced without some of these details. Several embodiments are described herein, and although various features are attributed to different embodiments, it should be understood that features described with respect to one embodiment may also be combined with other embodiments. However, for the same reasons, a single feature or several features of any described embodiment should not be considered necessary for every embodiment of the present invention, as other embodiments of the present invention may omit such features.

[0040] When an element is referred to herein as being "connected," "coupled," or "attached" to another element, it is understood that the element may be directly connected or coupled to the other element, or that there may be intervening elements between the elements. In contrast, when an element is referred to as being "directly connected," "directly coupled," or "directly attached" to another element, it is understood that there may be no intervening elements in the "direct" connection or coupling between the elements. However, the presence of a direct connection or coupling does not exclude other connections or couplings in which there may be intervening elements. As used throughout this disclosure, "connected," "connected," and the like may refer to a connection (e.g., an electrical connection) between one or more elements, while "coupled," "coupled," and the like may refer to a connection (e.g., a mechanical or physical connection, link, or engagement) between one or more elements.

[0041] When an element is referred to herein as being "positioned" or "located" in a certain manner relative to another element (e.g., positioned on, between, below, adjacent, or in some other relative manner), it is understood that the element may be directly positioned or located relative to the other element (e.g., directly on the other element) or that there may be intervening elements between the elements. In contrast, when an element is referred to as being "directly positioned" or "directly located" relative to another element, it is understood that there are no intervening elements in the "direct" instance. However, the presence of a direct positioning does not exclude other instances in which there may be intervening elements.

[0042] Likewise, when an element is referred to herein as a "layer," it is understood that the layer may be a single layer or may include multiple layers. For example, a conductive layer may include a plurality of different conductive materials or multiple layers of different conductive materials, and a dielectric layer may include a plurality of dielectric materials or multiple layers of dielectric materials. When a layer is described as being coupled or connected to another layer, it is understood that the coupled or connected layer may include intervening elements present between the coupled or connected layers. In contrast, when a layer is referred to as being "directly" connected or coupled to another layer, it is understood that there are no intervening elements between the layers. However, the presence of directly coupled or connected layers does not exclude other connections in which intervening elements may be present.

[0043] Furthermore, the terms left, right, front, back, top, bottom, forward, reverse, clockwise, and counterclockwise are used for explanation purposes only and are not limited to any fixed direction or orientation. Rather, they are only used to indicate the relative position and / or direction between the various parts and / or components of an object. In addition, unless otherwise expressly stated, terms such as first, second, third, etc. are only used to distinguish elements or components from each other and are not intended to imply an order or sequence.

[0044] In addition, the methods and processes described herein may be described in a particular order for ease of explanation. However, it should be understood that unless the context dictates otherwise, intervening processes may occur before and / or after any portion of the described process, and in addition, various procedures may be reordered, added, and / or omitted according to various embodiments.

[0045] Unless otherwise indicated, all numbers used herein to express quantities, dimensions, and the like should be understood as being modified in all instances by the term "about." As used herein, the term "substantially" or "approximately" refers to a variation of ±10% or less (e.g., ±10%, ±5%, etc.) (including the endpoints of the range) from a reference value or ratio.

[0046] In this application, unless specifically stated otherwise, the use of the singular includes the plural, and the use of the terms "and" and "or" means "and / or" unless otherwise indicated. In addition, the use of the terms "including" and "having" and other forms such as "include", "included", "has", "have" and "had" should be considered non-exclusive. Also, unless specifically stated otherwise, terms such as "element" or "component" encompass both elements and components that include one unit and elements and components that include more than one unit.

[0047] As used herein, the phrase "at least one of" preceding a list of items (with the terms "and" or "or" separating any of the items) modifies the list as a whole, rather than each member of the list (i.e., each item). The phrase "at least one of" does not require selection of at least one of each of the listed items; rather, the phrase allows for the inclusion of a meaning of at least one of any of the items and / or at least one of any combination of items. By way of example, the phrase "at least one of A, B, and C" or "at least one of A, B, or C" each refers to only A, only B, or only C; and / or any combination of A, B, and C. In instances where "at least one of each of A, B, and C" or, alternatively, "at least one of A, at least one of B, and at least one of C" is intended to be selected, it will be explicitly described as such.

[0048] In conventional semiconductor or chip packages, vias are often used to pass signals through a semiconductor device from or toward one or more layers, parts, or components. However, the number, quantity, or density of vias in a semiconductor device or one or more regions of a semiconductor device in which one or more channels, cavities, or pores are formed may be limited.

[0049] The present technology includes a semiconductor or chip device (e.g., an integrated circuit (IC), a chip or other semiconductor device or module) or an interposer (e.g., an interface for routing one or more electrical connections between at least two layers, etc.) that provides one or more channels (e.g., channels, cavities, pores, openings, etc.). The semiconductor device may include one or more through-holes (e.g., ridge through-holes, ridge through-substrate vias (TSVs), etc.) extending through one or more layers to the top surface of a ridge (e.g., a ridge, a fin, etc.) of the channel. The through-holes can be used to route one or more electrical connections through one or more layers and can be used to ensure electrical contact across an interface (e.g., an interface where two layers are coupled together, an interface where a die is coupled to a substrate, an interface where two substrates are coupled together, an interface where a die is coupled to a cooling plate (e.g., one or more layers including a channel configured to contain a nanofluid), or any other interface where two parts of a semiconductor device are coupled together, etc.). However, providing only ridge vias that extend through one or more layers to the top surface of the ridge of the channel, cavity, or void may limit the density or number of vias that may be formed within a semiconductor device.

[0050] Thus, the present technology may further provide one or more channels having vias (e.g., channel vias, channel TSVs, etc.) extending to the bottom surface of the channel. In some embodiments, a line (e.g., a conductive line, a conductive strip, a conductive strip, etc.) may extend upward from the channel via along the wall of the channel and connect to one or more conductive elements on the ridge of the channel. By extending the channel via to the bottom surface of the channel, several advantages may be achieved. For example, the diameter of the channel via extending to the bottom surface of the channel may be smaller than the diameter of the ridge via extending to the top surface of the ridge. During the manufacture of semiconductor devices, the diameter of the via is determined based on the amount of material through which the via needs to extend and the technical limitations of forming the via. In a non-limiting example, as the length of the via increases, the hole used to form the via needs to be enlarged to ensure that the hole is completely filled during the deposition of material to form the via. Therefore, as the via becomes longer or deeper, the diameter of the via needs to be increased. The channel vias may have a smaller diameter than the ridge vias because the channel has less substrate material for the channel vias to extend through. Additionally, the channel vias may be closer together than the ridge vias because the cross-sectional area of ​​the channel vias is smaller than the cross-sectional area of ​​the ridge vias. Thus, channel vias extending to the bottom surface of the channel may be mounted at a higher density than the (optionally) larger diameter ridge vias extending to the top surface of the ridge.

[0051] Figure 1 1 is a schematic cross-sectional view of an embodiment of a semiconductor device 100 or an interposer according to various embodiments. The semiconductor device 100 may include a substrate 102 (e.g., a support material on or within which elements of a semiconductor device are fabricated or attached). In various cases, the substrate 102 may be formed of one or more layers. The one or more layers may include, but are not limited to, one or more dielectric layers, one or more device layers, one or more conductive layers, one or more insulating layers, one or more redistribution layers, and / or the like. In this case, the substrate 102 has a first layer 104 coupled to a second layer 106. However, the substrate 102 may have more or fewer layers than the first layer 104 and the second layer 106. In some cases, the substrate 102 may be formed of silicon or other substrate materials.

[0052] In some embodiments, the first layer 104 of the substrate 102 may include one or more channels 108 (e.g., channels, cavities, pores, etc.) and one or more ridges 110. In various cases, the substrate 102 may be a cooling plate including one or more channels, one or more components including one or more vacuum cavities, or one or more other components including one or more channels, etc. In some cases, for example, when the substrate 102 is a cooling plate, the one or more channels 108 may contain or may be configured to contain a liquid. In a non-limiting example, the liquid may be a liquid configured to cool the semiconductor device 100, one or more active devices (e.g., transistors, diodes, etc.) located on or within the semiconductor device 100, one or more device dies of the semiconductor device, etc. In some cases, the liquid may be water or other liquid configured to cool the semiconductor device 100, the one or more active devices, the one or more device dies, etc. In some cases, when substrate 102 includes one or more vacuum cavities, the vacuum cavities may include one or more sensors, one or more transducers, and the like.

[0053] In various cases, semiconductor device 100 may further include a device die (not shown). The device die may include, but is not limited to, one or more circuits and / or one or more active devices configured to perform a function. In various cases, one or more channels 108 may be located near the device die and configured to dissipate or transfer heat from the device die. In some cases, layer 104 may be directly coupled to the device die. In various cases, second layer 106 may include a device die or may be a device die.

[0054] In some examples, semiconductor device 100 may further include one or more vias 112. The one or more vias may include at least one via 112a extending through one or more layers of substrate 102 to the bottom surface of channel 108 (e.g., one or more channel vias 112a). In some cases, one or more vias 112 may additionally include at least one via 112b extending through one or more layers of substrate 102 to the top surface of ridge 110 (e.g., one or more ridge vias 112b). In some cases, at least one via 112b may not be included in semiconductor device 100.

[0055] The one or more through-vias 112 may include, but are not limited to, one or more through-silicon vias and / or one or more through-substrate vias (TSVs). The one or more through-vias 112 may be configured to extend completely through the substrate 102 (e.g., "through" vias) and may be formed of a conductive material. The conductive material of the one or more through-vias 112 may include a metal or metal combination / alloy such as copper, tungsten, nickel, aluminum, gold, silver, tin, etc., or may be formed of other conductive materials or conductive material combinations. The one or more through-vias 112 may be configured to form one or more electrical connections for power or one or more signals to travel through the semiconductor device 100, the substrate 102, and / or the device die.

[0056] In some cases, semiconductor device 100 may further include one or more lines 114 (e.g., conductive wires, conductive strips, conductive strips, conductive traces, conductive wires, conductive ribbons, etc.). One or more lines 114 may be configured to connect to one or more conductive surfaces or pads 116 (e.g., one or more conductive elements, one or more conductive wires, one or more bonding pads or bonding surfaces, one or more via pads, etc.). In some cases, one or more pads 116 may be located on the top surface of one or more ridges 110, within one or more trenches 108, or along one or more walls of one or more trenches 108. In some examples, one or more lines 114 or pads 116 may be formed of a metal or metal combination / alloy such as copper, aluminum, gold, silver, tin, nickel, etc., or may be formed of other conductive materials or material combinations.

[0057] In various cases, the one or more wires 114 and / or pads 116 can be configured to connect to one or more vias 118 located in the second layer 106 of the substrate 102. In some cases, the vias 118 can be configured to extend completely through the second layer 106, or can extend through the second layer 106 from an outer surface (e.g., a "blind" via), and / or the like. The conductive material of the one or more vias 118 can include a metal or metal combination / alloy such as copper, tungsten, aluminum, gold, silver, tin, nickel, etc., or can be formed of other conductive materials or material combinations.

[0058] In some cases, layer 106 may include one or more features or components described above with respect to layer 104. In non-limiting examples, layer 106 may also have one or more channels and ridges, one or more channel or ridge vias, one or more lines, etc. In various cases, layer 106 may be a mirror image of one or more features or components described above with respect to layer 104.

[0059] The following is about Figure 2 8 further describe the one or more vias 112 and the one or more lines 114 of the semiconductor device 100.

[0060] Steering Figure 2to 7, Figure 2 7 show different embodiments of the bottom portion of substrates 200a to 200f (collectively, substrate 200) according to various embodiments. The substrate 200 may be similar to the substrate 200 described above with respect to Figure 1 The substrate 102 is described. In addition, as described above, the embodiments are not limited to substrates, and the embodiments of the present disclosure may also be applied to cooling plates, other components of semiconductor devices (such as one or more components including a vacuum cavity), or other semiconductor components including a channel. In addition, although Figure 2 7 show different embodiments of the substrate 200, but a person skilled in the art will appreciate that various modifications to each embodiment may be applied to other embodiments.

[0061] Figure 2 is a schematic top view of an embodiment of a portion of a substrate 200 a according to various embodiments. Figure 3A It is taken along line AA Figure 2 A cross-sectional view of the substrate 200a, and Figure 3B is a cross-sectional view of the substrate 200a taken along line BB. Figures 3 to 7 illustrate top views of different configurations or embodiments of substrates 200b to 200f according to various embodiments.

[0062] In some embodiments, substrate 200 may include one or more channels 202 and one or more ridges 204. One or more channels 202 may contain or may be configured to contain a liquid. In a non-limiting example, the liquid may be a liquid configured to cool semiconductor device 100, one or more active devices located on or within semiconductor device 100, one or more device dies of a semiconductor device, and the like.

[0063] The substrate 200 may further include one or more through-holes 206 (e.g., trench vias) extending to a bottom surface 208 of the trench 202. The one or more through-holes 206 may include, but are not limited to, one or more through-silicon vias and / or one or more through-substrate vias (TSVs). The one or more through-holes 206 may be configured to extend completely through the substrate 200 and may be formed of a conductive material. The one or more through-holes 206 may be configured to form an electrical connection for power or one or more signals to travel through the substrate 200.

[0064] One or more through holes 206 can be arranged in various ways within one or more channels 202. In various cases, such as Figure 2 As shown in FIG. 1 , one or more through holes 206a may be arranged around the center of one or more channels 202. In some cases, as shown in FIG. Figure 2 As shown in FIG. 1 , one or more through holes 206 b may be arranged parallel to an axis CC extending along one or more channels 202. In some examples, as shown in FIG. Figure 4As shown in FIG. 1 , one or more through holes 206 d may be arranged in one or more rows or columns within one or more channels 202. In one example, a two-dimensional orthogonal or non-orthogonal array of through holes 206 may be formed within one or more channels 202, such as Figure 4 and 5 In some cases, one or more through holes 206c may be arranged in one or more staggered columns or rows or offset from each other within the channel 202, such as Figure 5 By arranging one or more through-holes 206 in one or more rows or columns within the channel 202, a higher number or density of through-holes 206 may be obtained.

[0065] In some embodiments, the Figure 3B 2, one or more vias 206 may include one or more optional via spacers 210 (e.g., one or more conductive elements, one or more conductive connections, one or more conductive bonds, etc.) formed on the bottom surface 208 of the channel 202 and connected to the top surface 212 of the one or more vias 206. In some examples, the one or more via spacers 210 surround the top surface 212 of the one or more vias 206. In some instances, the one or more via spacers 210 may be formed of a metal or metal combination / alloy such as copper, tungsten, aluminum, gold, silver, tin, nickel, etc., or may be formed of other conductive materials or material combinations.

[0066] In some examples, substrate 200 may further include one or more lines 214 (e.g., conductive lines, conductive strips, conductive strips, conductive traces, conductive wires, conductive tapes, etc.). One or more lines 214 may be configured to connect to one or more via pads 210. Alternatively, one or more lines 214 may be configured to connect to top surface 212 of one or more vias 206.

[0067] In various embodiments, such as Figure 3B , one or more wires 214 may be configured to extend along a wall 216 of the channel 202 to a top surface 218 of the ridge 204 of the channel 202. In some cases, one or more wires 214a may extend along only one wall 216a of the channel 202. In other cases, one or more wires 214a and 214b may extend along both walls 216a and 216b of the channel 202, such as Figure 2 , 3B 4. In some cases, a portion of the one or more lines 214 may also extend along the top surface 218 of the one or more ridges 204.

[0068] The wall 216 of the channel 202 may be inclined between about 20 degrees and about 87 degrees relative to the bottom surface 208 of the channel 202, and may preferably be about 70 degrees relative to the bottom surface 208 of the channel 202. However, in some cases, the wall 216 may be about vertical (e.g., about 90 degrees relative to the bottom surface 208 of the channel 202). When the wall 216 is inclined, the one or more lines 214 extending along the wall 216 of the channel may be inclined by about the same amount as the wall 216 is inclined relative to the bottom surface 208 of the channel 202.

[0069] In various examples, the substrate 200 may further include one or more vias 220 (eg, ridge vias) extending through one or more layers of the substrate 200 to the top surface 218 of the ridge 204, such as Figure 2 , 3A and 3B. In various cases, such as Figure 3A and 3B , the diameter D1 of the one or more channel vias 206 may be smaller than the diameter D2 of the one or more ridge vias 220. The diameter D1 of the one or more channel vias 206 may be smaller than the diameter D2 of the one or more ridge vias 220 because the distance D3 of the one or more channel vias 206 to the bottom surface 208 of the channel 202, or the length of the one or more channel vias, is shorter than the distance D4 of the one or more ridge vias 220 to the top surface 218 of the ridge 204, or the length of the one or more ridge vias.

[0070] In some embodiments, one or more through-holes 220 may include one or more optional through-hole pads 222 (eg, one or more conductive elements, one or more conductive connections, one or more conductive bonds, etc.) Figure 2 and 4 6 by one or more circles including a line pattern fill on the top surface 218 of the ridge 204. One or more via spacers 222 can be connected to the top surface 224 of the one or more through-holes 220. In some examples, the one or more via spacers 222 surround the top surface 224 of the one or more through-holes 220. In some examples, the one or more via spacers 222 can be formed of a metal or metal combination / alloy such as copper, tungsten, aluminum, gold, silver, tin, nickel, lead, etc., or can be formed of other conductive materials or material combinations. In various cases, the one or more via spacers 222 can be configured to connect to, for example, Figure 1 One or more corresponding conductive elements on another layer or component of the semiconductor device shown in .

[0071] In addition to or in lieu of one or more through-holes 220 or through-hole pads 222, the substrate 200 may further include one or more bonding surfaces 226. Figure 2 and4 6 by one or more circles on the top surface 218 of the ridge 204 that do not include a pattern fill. The one or more bonding surfaces 226 may include one or more zero-gap bonding surfaces, such as one or more hybrid bonding surfaces, one or more direct bonding surfaces, one or more surface-activated bonding surfaces, and the like. The one or more hybrid bonding surfaces may include one or more surfaces having more than one material (e.g., an insulator or a combination of a dielectric material and a conductive material, and the like). The one or more direct bonding surfaces may include directly bonding two surfaces (e.g., two layers) together without an intermediate layer between the two surfaces. The one or more surface-activated bonding surfaces may include one or more surfaces that have been chemically treated or treated with a plasma process to enhance the bond energy between the one or more surfaces.

[0072] In various cases, the one or more bonding surfaces 226 may include one or more bonds that combine a dielectric material (e.g., silicon oxide, etc.) with an embedded metal (e.g., one or more bonding pads 228) to form one or more interconnects (e.g., interconnects between layers 104 and 106 of the substrate 102 or between other parts or components of the semiconductor device, etc.). The embedded metal may include, but is not limited to, a metal or metal combination / alloy such as copper, tungsten, nickel, aluminum, gold, silver, tin, etc., or may be formed of other conductive materials or material combinations.

[0073] In some examples, one or more bonding pads 228 of one or more bonding surfaces 226 may be located on the top surface 218 of the ridge 204. The top surface 224 of the one or more vias 220, the one or more via pads 222, and / or the top surface 230 of the one or more bonding pads 228 may be located at the interface 234 (or substrate 102) of the substrate 200 (or substrate 102). Figure 1 200) or at an interface 234 between the substrate 200 and one or more other semiconductor components. One or more bonding pads 228 may be configured to connect to, for example, Figure 1 One or more corresponding conductive elements on another layer or component of the semiconductor device shown in .

[0074] In various cases, one or more wires 214 may be configured to extend along the wall 216 of the channel 202 to the top surface 218 of the ridge 204 of the channel 202 and connect to the top surface 224 of one or more vias 220, to one or more via pads 222, or to the top surface 230 of one or more bonding pads 228, etc.

[0075] The one or more wires 214 may be arranged in various ways within the substrate 200. For example, Figure 6As shown in FIG. 2 , one or more wires 214 c may extend within the channel 202 and connect two or more vias 206 together or connect two or more via pads 210 together. Figure 6 As shown by line 214d in FIG. 1 , one or more lines 214d may extend around one or more ridges 204 and connect two or more through holes 206 together. Figure 6 , the line 214e may extend over one or more ridges 204 to connect two or more through holes 206 together. Figure 6 As shown by line 214f ​​in FIG. 1 , one or more lines 214f ​​may extend from the corresponding through hole 206 at an angle and upward and along the wall 216 of the channel 202 to connect to one or more other conductive elements (e.g., one or more through holes 206, one or more through hole pads 210, one or more through holes 220, one or more through hole pads 222 and / or one or more bonding pads 228, etc.).

[0076] In some cases, such as Figure 6 As shown in FIG. 1 , one or more wires 214g may extend upward from one or more vias 206 along walls 216a and 216b of channel 202 to connect to at least two of one or more vias 220, one or more via pads 222, and / or one or more bonding pads 228, etc. In some cases, as shown in FIG. Figure 6 206, one or more wires 214h may extend through the channel 202 to connect at least two of the one or more vias 220, the one or more via pads 222, and / or the one or more bonding pads 228, etc. In some cases, the wire 214h may not be connected to the channel via 206. In other cases, the wire 214h may be connected to the channel via 206. In some cases, the one or more wires 214i may extend from the via 206 to at least one of the one or more vias 220, the one or more via pads 222, and / or the one or more bonding pads 228 on the ridge 204 that is not directly adjacent to the channel 202 including the via 206. In some cases, two channel vias 206 may be connected to at least one of one or more vias 220 , one or more via pads 222 , and / or one or more bonding pads 228 via one or more wires 214 j .

[0077] These are only some of the possible arrangements of the one or more wires 214, and many other arrangements are possible and within the scope of the embodiments. In various cases, the one or more wires 214 may be routed between, around, over, along, or across the channels and ridges and connected to the one or more vias 206, the one or more via pads 210, the one or more vias 220, the one or more via pads 222, and / or the one or more bonding pads 228, etc., in any arrangement required by the design without limitation.

[0078] In yet another embodiment, Fig. 7A and 7B As shown in FIG. 1 , one or more layers 232a (composed of Figure 7B 206, one or more via pads 210, one or more via pads 222, and / or one or more bonding pads 228. The one or more layers 232a and 232b may be one or more dielectric layers or insulating layers. The one or more layers 232a and 232b may be formed of inorganic materials such as silicon dioxide, silicon nitride, silicon carbonitride, etc., or organic materials such as photodefinable or non-photodefinable polymers, and / or another other material suitable for use as a dielectric layer or insulating layer. The one or more layers 232a and 232b may be selectively located at locations where the one or more lines 214, one or more via pads 210, one or more via pads 222, and / or one or more bonding pads 228 are formed. In a non-limiting example, one or more layers 232a and 232b may be deposited on first wall 216c of one or more channels 202 while one or more layers 232a and 232b are not deposited on wall 216d.

[0079] By selectively positioning the one or more layers 232a and 232b at locations where the one or more lines 214, the one or more vias 206, the one or more via pads 210, the one or more via pads 222, and / or the one or more bonding pads 228 are formed, heat transfer between the substrate 200 and another component of the semiconductor device (e.g., a device die) can be increased. However, the one or more layers 232a and 232b can completely cover any portion of the metal that would otherwise be in contact with the fluid contained within the one or more channels 202. By covering the one or more lines 214, the one or more vias 206, the one or more via pads 210, the one or more via pads 222, and / or the one or more bonding pads 228 with the one or more layers 232a and 232b, corrosion or other unwanted chemical reactions can be prevented.

[0080] In yet another embodiment, as shown in FIG. 8 , a semiconductor device 300 may include a substrate 302 having a first layer 304 and a second layer 306 (or other component of a semiconductor device having a channel, etc.).

[0081] In various embodiments, the first layer 304 of the substrate 302 may include one or more channel vias 308 extending to the bottom surface of the channel 310 (similar to Figure 2 7). The first layer 304 may further include one or more lines 312 extending from the one or more vias 308 along one or more walls 314 (similar to the channel vias 206 described with reference to FIG. 7). Figure 2 7 ). In various cases, a bonding pad (e.g., similar to bonding pad 228 or via pad 210 or 222) may be connected to a top surface 324 of one or more wires 312. A second layer 306 of semiconductor device 300 (e.g., a second layer of a substrate, a device die, etc.) may include one or more channel vias 316 (similar to channel vias 316) extending to a bottom surface of channel 318. Figure 2 7). The second layer 306 may further include one or more wires 320 extending along one or more walls 322 corresponding to and configured to connect to the one or more wires 312. In various cases, a bonding pad (e.g., similar to bonding pad 228 or via pad 210 or 222) may be connected to a top surface 326 of the one or more wires 320.

[0082] 8, one or more wires 312 may extend upwardly along a first portion of a wall 314 of a channel 310, while one or more wires 320 may extend downwardly along a wall 322 of a channel 318. In some cases, one or more wires 312 may be the same length or approximately the same length as the wall 314, and one or more wires 320 may be the same length or approximately the same length as the wall 322. A top surface 324 of the one or more wires 312 may be connected to a top surface 326 of the one or more wires 320. Alternatively, in other cases, one or more wires 312 may be less than the height of the wall 314, and one or more wires 320 may be less than the height of the wall 322. The height difference between one or more wires 312 or 320 and the corresponding wall 314 or 322 must be small enough to allow one or more wires 312 or 320 to overcome the height difference relative to the corresponding wall 314 or 322 when the substrate 302 is heated. In this case, when substrate 302 is heated, one or more wires 312 and one or more wires 320 may expand at a faster rate than corresponding walls 314 or 322 of substrate 302 and connect top surface 324 of one or more wires 312 to top surface 326 of one or more wires 320 .

[0083] In some cases, one or more lines 312, one or more lines 320, one or more walls 314, and / or one or more walls 322 may be inclined (e.g., between about 20 degrees and about 87 degrees). In other cases, one or more lines 312, one or more lines 320, one or more walls 314, and / or one or more walls 322 may be approximately vertical (e.g., about 90 degrees relative to the bottom surface of one or more channels 310 or 318).

[0084] In various cases, one or more wires 312 and / or one or more wires 320 may be configured to connect to one or more spine vias (e.g., Figure 2 to ridge through hole 220 of 7), one or more through hole spacers (e.g., Figure 2 7 through-hole pads 210 and / or 222) and / or one or more bonding pads (e.g., Figure 2 One or more of bonding pads 228 to 7) and / or the like.

[0085] Fig. 9 is a flow chart of a method of manufacturing a semiconductor device according to various embodiments. Fig. 9 The method described in the Figure 1 However, other methods (e.g., method 1000, method 1200, or other methods) may be used to manufacture the components of FIG. Figure 1 to 8 components.

[0086] Steering Fig. 9 , method 900 may begin at block 905 by providing a substrate (e.g., substrate 102, 200, 302, or other component of a semiconductor device including one or more channels, etc.). Next, one or more vias (e.g., ridge vias, channel vias, etc.) may be formed within the substrate at block 910. In some cases, one or more channels may then be formed in the substrate at block 915 to expose top surfaces of the one or more channel vias. Method 900 may further include connecting one or more wires to the top surfaces of the one or more channel vias at block 920. The one or more wires may be configured to extend along the walls of the channel to the top surfaces of the one or more ridges of the channel.

[0087] Fig.10 is a flow chart of a method 1000 of fabricating a semiconductor device according to various embodiments. Figures 11A to 11K Is Fig.10 A cross-sectional view of a semiconductor device formed by the steps described in FIG. Fig.10 The method described in the Figure 1 However, other methods can be used to make Figure 1 to 8 components.

[0088] Steering Fig.10 and 11A To 11K, method 1000 may be performed at block 1005 and Fig.11A The invention begins by providing a substrate 1100 (e.g., substrate 102, 200, 302 or other component of a semiconductor device including one or more channels, etc.) including one or more vias 1102. The vias 1102 may be one or more channel vias 1102a and / or ridge vias 1102b, as described above with respect to Figure 1 8. In various cases, one or more channel vias and / or one or more ridge vias may be formed simultaneously, approximately simultaneously, or separately. In some cases, one or more vias 1102 may be formed simultaneously or approximately simultaneously with substrate 1100. In some cases, substrate 1100 may have vias that have already been formed but are still buried in substrate 1100, such as Fig.11A As shown in .

[0089] Next, in optional blocks 1010 and Fig. 11B At , the substrate 1100 may be thinned (e.g., one or more of grinding, polishing, or etching, etc.) to expose the top surface of the ridge via 1102b. In addition, at optional blocks 1015 and Fig. 11B At the top portion of the substrate 1100, one or more first layers 1104 may be formed. The one or more first layers 1104 may be one or more dielectric layers, insulating layers, or isolation layers. The one or more first layers 1104 may be formed of an inorganic material such as silicon dioxide, silicon oxide, etc., and / or another other material suitable for use as a dielectric layer, an insulating layer, or an isolation layer.

[0090] In some cases, one or more first layers 1104 (e.g., one or more isolation oxide layers, etc.) may be deposited only at selected locations where one or more lines, via pads, bonding pads, etc. are formed. In other cases, at optional blocks 1020 and Fig. 11B At selected locations where one or more lines, via pads, bonding pads, etc. are to be formed, one or more portions of the one or more first layers 1104 may be removed (e.g., etched, removed using photolithography, etc.). In some embodiments, one or more portions of the one or more layers 1104 may be removed to expose the top surface of the via (e.g., via 1102b). In some cases, one or more portions of the one or more layers 1104 may be removed in order to deposit one or more via pads, bonding pads, etc. In some cases, a portion of the one or more layers 1104 may be configured to remain under the one or more lines, via pads, bonding pads, etc. to isolate the one or more lines, via pads, bonding pads, etc. from the top surface of the substrate 1100. In various cases, a seed layer may be formed. The seed layer may be used to facilitate electrical connection between one or more conductive elements or to serve as a barrier or bonding layer to help the metal of the conductor bond to the dielectric layer, etc.

[0091] Next, at optional blocks 1025 and Fig. 11C At the top portion of the ridge 1112, one or more conductive elements (e.g., optional portions of one or more wires 1106 (e.g., one or more wires 214, 312, etc.), one or more via pads 1108 (e.g., via pad 222, etc.), and / or one or more bonding pads 1110 (e.g., bonding pad 228, etc.)) may be formed. In various cases, the conductive elements may be formed in selected locations where one or more layers 1104 are removed. In various cases, the one or more wires 1106, one or more via pads 1108, and / or one or more bonding pads 1110 may be formed on top of the one or more first layers 1104 or within one or more removed portions 1105 of the one or more first layers 1104.

[0092] Next, at block 1030 and Fig.11D At 1035, the method 1000 may include forming one or more second layers 1114 (e.g., one or more silicon oxide layers, etc.) on the top portion of the substrate 1100, the one or more first layers 1104, the one or more lines 1106, the one or more via pads 1108, and / or the one or more bonding pads 1110, etc. The one or more second layers 1114 may be one or more dielectric layers, insulating layers, or isolation layers. The one or more second layers 1114 may be used to form a bonding surface (e.g., a zero-gap bonding surface, a hybrid bonding surface, etc.) and serve as an interface between the substrate 1100 and another component of the semiconductor device or a layer of the substrate 1100. At optional blocks 1035 and Fig.11D The one or more second layers 1114 may then be planarized to ensure that the top surface of the one or more second layers is substantially horizontal. In various cases, the one or more second layers may be planarized to be optionally horizontal with the top surface of the one or more via pads 1108 and / or the one or more bonding pads 1110 and optionally expose the top surface, such as Fig.11D As shown in .

[0093] Next, at optional blocks 1040 and Fig.11E At 1045, one or more bonding pads 1110 (e.g., zero-gap bonding pads, etc.) may be formed in one or more second layers. Bonding pads 1110 may be used to connect wires 1106 and / or vias 1102b of substrate 1100 to one or more conductive elements located on another component configured to be coupled to the substrate. In some cases, at optional blocks 1045 and Fig.11F At , one or more thin protective layers 1115 may then be formed or deposited on the one or more second layers 1114 to protect the top surface of the one or more via pads 1108 and / or the one or more bonding pads 1110 .

[0094] Method 1000 may be performed at block 1050 and Fig.11G The substrate 1100 may continue at block 1050 and form one or more channels 1116 (e.g., channels 108, 202, 310, 318, etc.). The one or more channels 1116 may be formed to expose the top surface of the one or more channel vias 1102a at the bottom surface of the one or more channels 1116. For example, an etching process may be used to etch the substrate 1100 to expose the top surface of the one or more vias 1102a and form the one or more channels 1116. The method 1000 may then optionally include blocks 1050 and Fig.11H A step 1117 is formed (e.g., etched) in the one or more second layers 1114 and / or the one or more protective layers 1115 over one or more portions of the line 1106. In some cases, the step 1117 may be completely etched to expose the one or more portions of the line 1106. Alternatively, in other cases, the step 1117 may be etched until a particular thickness of the one or more second layers 1114 is achieved and then an opening or hole 1119 may be formed that is less than the length of the one or more portions of the line 1106. In some cases, at optional block 1060, the top surface of the one or more channels 1116 may be etched to expose the top surface of the one or more channel vias 1102a at the bottom surface of the one or more channels 1116.

[0095] Method 1000 may then continue to optional block 1065 and Fig.11I And one or more third layers 1118 are formed on one or more walls of one or more channels 1116. One or more third layers 1118 may be one or more dielectric layers or insulating layers. One or more third layers may be formed of photo-definable polyimide or other dielectric materials. Photo-definable polyimide or other dielectric materials may be selected based on one or more materials of substrate 1100 or layers 1104, 1114, 1115, etc. One or more third layers 1118 may be deposited only at selected locations where one or more lines, via pads, bonding pads, etc. are formed. In other cases, one or more third layers 1118 may be removed at selected locations where one or more lines, via pads, hybrid bonding pads, etc. are not formed. In some cases, one or more portions of one or more third layers 1118 may then be removed to expose the top surface of the through hole (e.g., through hole 1102). For example, an etching process may be used to etch the one or more third layers 1118 to expose the top surface of the one or more vias 1102a.

[0096] Method 1000 may then proceed to block 1070 and Fig.11JAnd at least a portion of the one or more wires 1106 is formed on top of the one or more third layers 1118. The portion of the one or more wires 1106 formed on the one or more third layers 1118 may be connected to one or more of the one or more vias 1102a, the one or more vias 1102b, one or more portions of the wires 1106 at the top surface of the one or more ridges 1112, one or more via pads 1108, and / or one or more bonding pads 1110.

[0097] Next, method 1000 may then proceed to optional block 1075 and Figure 11K And one or more fourth layers 1120 are formed on one or more wires 1106 formed on one or more walls of one or more channels and / or encapsulate the wires and / or on top of one or more wires 1106 formed on the top surface of one or more ridges 1112. One or more fourth layers 1120 may be one or more dielectric layers or insulating layers. One or more fourth layers 1120 may be formed of photo-definable polyimide or other dielectric materials. One or more fourth layers 1120 may be deposited only at selected locations where one or more wires, via pads, hybrid bonding pads, etc. are formed. In other cases, one or more fourth layers 1120 may be removed at selected locations where one or more wires, via pads, hybrid bonding pads, etc. are not formed. In various cases, in order to ensure a smooth bonding surface between the one or more bonding pads 1110 and another component of the semiconductor device (e.g., a device die, etc.), the height of the one or more fourth layers 1120 may be less than the height of the one or more second layers 1114. In other words, the top surface of the one or more fourth layers 1120 may be lower than the top surface of the one or more second layers 1114.

[0098] Finally, the substrate 1100 may be cleaned and one or more optional thin protective layers used to protect the top surface of the one or more via pads 1108 and / or the one or more bonding pads 1110 may be removed from the one or more second layers 1114. In some cases, the top surface of the substrate 1100 may be formed by using a chemical mechanical planarization process to prepare the substrate 1100 for coupling to another component. Next, at optional block 1080, the substrate 1100 may be coupled to another component of a semiconductor device (e.g., a device die, another layer of the substrate 1100, etc.). When the substrate 1100 is coupled to another component of the semiconductor device, the one or more via pads 1108 and / or the one or more bonding pads 1110 may be connected to one or more conductive elements (e.g., via pads, bonding pads, etc.) of the other component of the semiconductor device.

[0099] The techniques and processes described above with respect to various embodiments may be used to manufacture Figure 1 8 to 8 semiconductor devices or components and / or components thereof, as described herein. Alternatively, other processes may be used to manufacture Figure 1 to 8 semiconductor devices or components.

[0100] Fig.12 is a flow chart of a method 1200 of fabricating a semiconductor device according to various embodiments. Fig.12 The method described in the Figure 1 However, other methods can be used to make Figure 1 to 8 components. Fig.13 Demonstration of use Fig.12 A possible embodiment of a substrate 1300 manufactured by a method.

[0101] The method 1200 may begin at block 1205 by providing a substrate 1300 (e.g., substrate 102, 200, 302, or other component of a semiconductor device including one or more channels, etc.) and forming one or more vias 1302 at block 1210. The vias may be one or more channel vias 1302a and / or ridge vias 1302b, as described above with respect to Figure 1 8. In various cases, one or more channel vias 1302a and / or one or more ridge vias 1302b may be formed simultaneously, approximately simultaneously, or separately.

[0102] Next, at optional block 1215 ( Fig.13 At (not shown), the substrate 1300 may be thinned to expose the top surface of the ridge via 1302b. In addition, at optional blocks 1220 and Fig.13 At the top portion of the substrate 1300, one or more first layers 1304 may be formed. The one or more first layers 1304 may be one or more dielectric layers, insulating layers, or isolation layers. The one or more first layers 1304 may be formed of an inorganic material such as silicon dioxide, silicon oxide, etc., and / or another other material suitable for use as a dielectric layer, insulating layer, or isolation layer.

[0103] The method 1200 may continue at block 1225 and form one or more channels 1306 (e.g., channels 108, 202, 310, 318, etc.). The one or more channels 1306 may be formed to expose the top surface of the one or more channel vias 1302a at the bottom surface of the one or more channels 1306. For example, the substrate 1300 may be etched using an etching process to expose the top surface of the one or more vias 1302a and form the one or more channels 1306. The method 1200 may then optionally include forming one or more second layers 1308 on the top portion of the ridge 1310 of the channel 1306 and on the top surface of the channel 1306 at block 1230. The one or more second layers 1308 may be one or more dielectric layers, insulating layers, or isolation layers. The one or more second layers 1308 may be formed of an inorganic material such as silicon dioxide, silicon oxide, etc., and / or another other material suitable for use as a dielectric layer, an insulating layer, or an isolation layer.

[0104] Next, the method 1200 may include forming one or more first openings in the one or more first layers 1304 and / or the one or more second layers 1308 to expose the surface of the one or more channel vias 1302a and / or the one or more ridge vias 1302b at optional block 1235. The method 1200 may then continue to block 1240 and form at least a portion of one or more wires 1312 and / or bonding pads 1314 on top of the one or more second layers 1308. In some cases, the one or more bonding pads 1314 may be formed at optional blocks 1250 and 1255. The portion of the one or more wires 1312 formed on the one or more second layers 1308 may be connected to one or more of the one or more vias 1302 through the one or more first openings, other portions of the wires 1312, and / or the one or more bonding pads 1314.

[0105] The method 1200 may include depositing one or more third layers 1316 on top of the one or more lines 1312 at optional block 1245. The one or more third layers 1316 may be one or more dielectric layers, insulating layers, or isolation layers. The one or more third layers 1316 may be used to form a bonding surface (e.g., a zero-gap bonding surface, a hybrid bonding surface, etc.) and serve as an interface between the substrate 1300 and another component of the semiconductor device or a layer of the substrate 1300. The one or more third layers 1316 may then be planarized to ensure that the top surface of the one or more third layers is substantially level.

[0106] Next, the method 1200 may include forming one or more second openings in the one or more third layers 1316 to expose the surface of the one or more wires 1312 at the top surface of the one or more ridges 1310 at optional block 1250. A bonding pad 1314 may then be formed within the one or more second openings and connected to the one or more wires 1312 at optional block 1255.

[0107] Finally, the substrate 1300 may be cleaned and the surface of the ridge 1310 may be planarized. Next, at optional block 1260, the substrate 1300 may be coupled to another component of a semiconductor device (e.g., a device die, another layer of the substrate 1300, etc.). When the substrate 1300 is coupled to another component of a semiconductor device, the one or more via pads and / or the one or more bonding pads 1314 may be connected to one or more corresponding conductive elements (e.g., via pads, bonding pads, etc.) of the other component of the semiconductor device.

[0108] Although some features and aspects have been described with respect to embodiments, it should be recognized by those skilled in the art that numerous modifications are possible. In addition, although the procedures of the methods and processes described herein are described in a particular order for ease of explanation, various procedures may be reordered, added, and / or omitted according to various embodiments unless the context otherwise dictates. In addition, the procedures described with respect to a method or process may be incorporated into other described methods or processes; similarly, system components described according to a specific structural architecture and / or with respect to a system may be organized in an alternative structural architecture and / or incorporated into other described systems. Therefore, although those embodiments are described with or without some features for ease of explanation and for the purpose of illustrating various aspects of various embodiments, various components and / or features described herein with respect to a specific embodiment may be replaced, added, and / or subtracted from other described embodiments unless the context otherwise dictates. Therefore, although several embodiments are described above, it should be understood that the present invention is intended to cover all modifications and equivalent forms within the scope of the appended claims.

Claims

1. A semiconductor device comprising: a first layer including a channel; a first through hole extending through the first layer to a first surface of the channel, wherein the first surface is located at a bottom of the channel; and A line connects the first via to the pad. The semiconductor device according to claim 1 , wherein the spacer is located on a ridge of the trench. 3 . The semiconductor device according to claim 2 , wherein the wire extends along a portion of the first wall of the trench to be connected to the pad. The semiconductor device according to claim 3 , wherein the first wall of the channel is inclined. The semiconductor device of claim 4 , wherein the first wall is inclined between about 20 degrees and about 87 degrees. The semiconductor device of claim 3 , wherein a second layer is located between the first wall of the trench and the line. 7 . The semiconductor device of claim 2 , wherein the ridge further comprises a second through hole extending to a second surface of the ridge, wherein the second surface is located at a top of the ridge. 8 . The semiconductor device according to claim 6 , wherein a diameter of the first through hole is smaller than a diameter of the second through hole. 9 . The semiconductor device of claim 1 , wherein a second layer is partially formed on the first layer to encapsulate at least one of a top of the first via or the line connecting the first via to the pad.

10. The semiconductor device of claim 1, wherein the channel comprises a fluid, and wherein a second layer is formed at a location to encapsulate a portion of the wire, wherein the location is selected to prevent the portion of the wire from contacting the fluid in the channel.

11. The semiconductor device according to claim 1, wherein When the spacer is located on top of the ridge of the channel, the semiconductor device further comprises: a second layer encapsulating the wire; and A third layer, which sits on top of the ridge, encapsulates the gasket, The top surface of the second layer is lower than the top surface of the third layer.

12. A semiconductor device comprising: a via array, the via array comprising at least one first via extending through the layer to a bottom of the channel; and A line extends along a portion of the channel and connects the at least one first via to the pad. The semiconductor device according to claim 12 , wherein the spacer is located on a ridge of the trench. 14 . The semiconductor device according to claim 12 , wherein the through-hole array comprises two or more through-holes arranged in two or more columns or two or more rows along the bottom of the channel. 15 . The semiconductor device of claim 12 , wherein the via array includes at least one second via extending through the layer to a top of a ridge of the channel.

16. The semiconductor device of claim 12, the spacer comprising a zero-gap bondable surface.

17. A method for manufacturing a semiconductor device, the method comprising: forming a through hole extending through the first layer; forming a trench in the first layer to expose a first surface of the through hole, wherein the first surface of the through hole is exposed on a bottom surface of the trench; and A line is formed extending from the first surface of the via and configured to connect the via to a pad.

18. The method according to claim 17, further comprising: After forming the channel and before forming the line, a second layer is formed on top of the first layer including the channel, wherein the second layer is a dielectric layer.

19. The method according to claim 18, further comprising: After forming the lines, a third layer is formed on top of the lines, wherein the third layer is a dielectric layer.

20. The method of claim 17, wherein forming the line further comprises: The wire is formed to extend from the first surface of the through-hole to the pad on the ridge of the channel, wherein the wire extends along a portion of a wall of the channel to connect to the pad.

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