Converter circuit for suppressing output voltage spike

Abstract

The invention discloses a converter circuit for suppressing output voltage spikes. The converter circuit comprises a transformer module, an input module, a rectification output module, a first capacitive suppression module and a second capacitive suppression module, wherein the input module is arranged on a primary winding of the transformer module; the rectification output module, the first capacitive suppression module and the second capacitive suppression module are arranged on a secondary winding of the transformer module; the first capacitive suppression module is bridged at the two ends of a first path inductor, and the first path inductor is located between the first end of the secondary winding and the first end of the rectification output module; the second capacitive suppression module is bridged at the two ends of a second path inductor, and the second path inductor is located between the second end of the secondary winding and the second end of the rectification output module; the capacitive suppression module only comprises a capacitor. According to the invention, the junction capacitance parasitic oscillation in the turn-on and turn-off processes of the rectification device in the output rectification module can be suppressed, and the output voltage spike of the output rectification module can be greatly reduced, so that the voltage stress of the output rectification module is reduced, and the circuit stability is improved.

Description

Technical Field

[0001] The present invention relates to the field of converters, and more particularly to a converter circuit for suppressing output voltage spikes. Background Art

[0002] LLC resonant converters are often used in new energy power conversion applications due to their soft switching and high conversion efficiency. In order to further improve the overall efficiency performance of the resonant converter, in different application scenarios, the secondary side rectifier circuit can adopt various types of rectifier circuits such as full-wave rectification, full-bridge rectification, voltage doubler rectification or current doubler rectification to achieve DC output. In the above rectifier circuit, according to the selection of the rectifier tube, the rectifier circuit is divided into a diode rectifier circuit and a synchronous rectifier circuit with synchronous rectification function. Regardless of whether diode rectification or synchronous rectification technology is used, both ends of the rectifier tube contain parasitic junction capacitance. When the rectifier tube is switched / turned on and off, the parasitic junction capacitance at both ends of the rectifier tube and other parasitic parameters (stray, wiring inductance) in the circuit form parasitic oscillations, forming voltage oscillation spikes at both ends of the rectifier tube, increasing the voltage stress of the rectifier tube, thereby affecting the stable operation of the converter.

[0003] In order to optimize the voltage stress problem of the output rectifier tube of the resonant converter, a common method is to add an RC or RCD absorption circuit at both ends of the rectifier tube to absorb the oscillation spike. However, the voltage spike energy absorbed by such an absorption circuit is released through the absorption resistor, thus reducing the overall conversion efficiency.

[0004] Therefore, a converter circuit that can both reduce voltage stress and improve conversion efficiency has become an urgent problem to be solved by those skilled in the art. Summary of the invention

[0005] The technical problem to be solved by the present invention is that, in view of the above-mentioned defects of the prior art, a converter circuit for suppressing output voltage spikes is provided, which can significantly reduce the output voltage spikes of the converter, thereby reducing the voltage stress of the output rectifier module, thereby improving the circuit stability.

[0006] The technical solution adopted by the present invention to solve its technical problem is: constructing a converter circuit for suppressing output voltage spikes, including a transformer module, an input module arranged on the primary winding of the transformer module, and a rectifier output module arranged on the secondary winding of the transformer module; the converter circuit for suppressing output voltage spikes further includes a first capacitive suppression module and a second capacitive suppression module; the first capacitive suppression module is bridged across the two ends of a first path inductor, and the first path inductor is located between the first end of the secondary winding and the first end of the rectifier output module; the second capacitive suppression module is bridged across the two ends of a second path inductor, and the second path inductor is located between the second end of the secondary winding and the second end of the rectifier output module; the capacitive suppression module only includes a capacitor.

[0007] In the converter circuit for suppressing output voltage spikes described in the present invention, the capacitive suppression module is composed of a single capacitor or multiple capacitors connected in series or in parallel.

[0008] In the converter circuit for suppressing output voltage spikes described in the present invention, the rectifier output module includes a full-bridge rectifier unit and an output filter unit; the full-bridge rectifier unit includes a first switch device, a second switch device, a third switch device and a fourth switch device; the first end of the first switch device is connected to the second end of the second switch device and the first end of the rectifier output module, and the first end of the third switch device is connected to the second end of the fourth switch device and the second end of the rectifier output module; the second end of the first switch device and the second end of the third switch device are connected to the output positive electrode; the first end of the second switch device and the first end of the fourth switch device are connected to the output negative electrode;

[0009] The output filter unit is connected between the output positive electrode and the output negative electrode.

[0010] In the converter circuit for suppressing output voltage spikes described in the present invention, the switching device includes a diode or a switching tube; when the switching device is a diode, the first end of the switching device is the anode of the diode, and the second end of the switching device is the cathode of the diode; when the switching device is a switching tube, the control end of the switching tube receives a control signal, the first end of the switching device is the first end of the switching tube, and the second end of the switching device is the second end of the switching tube.

[0011] In the converter circuit for suppressing output voltage spikes described in the present invention, the rectifier output module includes a full-wave rectifier unit and an output filter unit; the converter circuit further includes a third capacitive suppression module; the first capacitive suppression module is connected across the two ends of a first path inductance between the first end of the secondary winding and the first end of the full-wave rectifier unit; the second capacitive suppression module is connected across the two ends of a second path inductance between the second end of the secondary winding and the second end of the full-wave rectifier unit; the third capacitive suppression module is connected across the two ends of a third path inductance between the third end of the secondary winding and the third end of the full-wave rectifier unit; the third end of the secondary winding is located between the first end of the secondary winding and the second end of the secondary winding.

[0012] In the converter circuit for suppressing output voltage spikes described in the present invention, the secondary winding of the transformer module includes a first secondary winding and a second secondary winding, the first end of the first secondary winding is the first end of the secondary winding, the second end of the first secondary winding is connected to the first end of the second secondary winding to form the third end of the secondary winding, and the second end of the second secondary winding is the second end of the secondary winding.

[0013] In the converter circuit for suppressing output voltage spikes described in the present invention, the full-wave rectifier unit includes a first switching device and a second switching device; the first end of the first switching device is connected to the first end of the full-wave rectifier unit, and the second end is connected to the output positive pole, the first end of the second switching device is connected to the second end of the full-wave rectifier unit, and the second end of the second switching device is connected to the output positive pole; the third end of the full-wave rectifier unit is connected to the output negative pole; the output filter unit is connected between the output positive pole and the output negative pole.

[0014] In the converter circuit for suppressing output voltage spikes described in the present invention, the switching device includes a diode or a switching tube; when the switching device is a diode, the first end of the switching device is the anode of the diode, and the second end of the switching device is the cathode of the diode; when the switching device is a switching tube, the control end of the switching tube receives a control signal, the first end of the switching device is the first end of the switching tube, and the second end of the switching device is the second end of the switching tube.

[0015] In the converter circuit for suppressing output voltage spikes described in the present invention, each of the capacitive suppression modules includes a capacitor, each of the path inductors includes an inductor, and the capacitor is connected across both ends of the inductor.

[0016] In the converter circuit for suppressing output voltage spikes described in the present invention, the capacitive suppression module includes N capacitors, the path inductance includes N series-connected inductors, and each capacitor is connected across two ends of an inductor; wherein N is a positive integer greater than 1.

[0017] In this preferred embodiment, since capacitors are respectively connected across the two ends of the path inductance between the first end and the second end of the secondary winding of the transformer module and the rectifier output module, the parasitic oscillation of the junction capacitance during the turn-on and turn-off process of the rectifier device in the output rectifier module can be suppressed, thereby greatly reducing the output voltage spike of the output rectifier module, thereby reducing the voltage stress of the output rectifier module and improving the circuit stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The present invention will be further described below with reference to the accompanying drawings and embodiments, in which:

[0019] Figure 1 is a principle block diagram of a first preferred embodiment of a converter circuit for suppressing output voltage spikes of the present invention;

[0020] Figure 2 is a circuit diagram of a second preferred embodiment of a converter circuit for suppressing output voltage spikes of the present invention;

[0021] Figure 3 is a circuit diagram of a third preferred embodiment of a converter circuit for suppressing output voltage spikes of the present invention;

[0022] Figure 4 is a circuit diagram of a fourth preferred embodiment of a converter circuit for suppressing output voltage spikes of the present invention;

[0023] Figure 5 is a circuit diagram of a fifth preferred embodiment of a converter circuit for suppressing output voltage spikes of the present invention;

[0024] Figure 6 is a circuit diagram of a sixth preferred embodiment of a converter circuit for suppressing output voltage spikes of the present invention;

[0025] Figure 7 It is a schematic diagram of the output voltage at both ends of the rectifier tube of the rectifier output module of the resonant converter circuit in the prior art;

[0026] Figure 8 The present invention is a schematic diagram of the output voltage at both ends of the rectifier device of the rectifier output module of the converter circuit for suppressing the output voltage spike. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0028] Figure 1 FIG. 1 is a schematic block diagram of a first preferred embodiment of a converter circuit for suppressing output voltage spikes according to the present invention. Figure 1 As shown, the converter circuit for suppressing output voltage spikes includes a transformer module 200, an input module 100 arranged at the primary winding of the transformer module 200, a rectifier output module 400 arranged at the secondary winding of the transformer module 200, and a first capacitive suppression module 310 and a second capacitive suppression module 320. The first capacitive suppression module 310 is connected across the two ends of a first path inductor, the first path inductor is located between the first end of the secondary winding and the first end of the rectifier output module 400; the second capacitive suppression module 320 is connected across the two ends of a second path inductor, the second path inductor is located between the second end of the secondary winding and the second end of the rectifier output module 400; the capacitive suppression module only includes a capacitor. Here, the path inductance refers to the parasitic inductance and / or leakage inductance between the secondary winding and the rectifier device of the rectifier output module.

[0029] In a preferred embodiment of the present invention, the capacitive suppression module is composed of a single or multiple capacitors connected in series or in parallel. In a preferred embodiment of the present invention, the first capacitive suppression module 310 and the second capacitive suppression module 320 may each include only one capacitor, the first path inductor and the second path inductor may each include only one inductor, and the capacitor is connected across the two ends of the inductor. In a preferred embodiment of the present invention, the first capacitive suppression module 310 and the second capacitive suppression module 320 may each include N capacitors, the first path inductor and the second path inductor may each include N inductors connected in series, and each capacitor is connected across the two ends of an inductor; wherein N is a positive integer greater than 1.

[0030] In a preferred embodiment of the present invention, the transformer module 200, the input module 100 and the rectifier output module 400 may be constructed using any device or module known in the art. In a preferred embodiment of the present invention, the transformer module 200 may include at least one primary winding and at least one secondary winding. In a preferred embodiment of the present invention, the transformer module 200 may include at least one primary winding and at least two secondary windings connected in series with each other. In another preferred embodiment of the present invention, the transformer module 200 may include N primary windings connected in series with each other and N secondary windings connected in series with each other, where N is a positive integer greater than 1.

[0031] In a preferred embodiment of the present invention, the converter circuit may be an isolated converter circuit, such as a flyback converter, a resonant converter, and the like. In a further preferred embodiment of the present invention, the converter circuit is an LLC resonant converter circuit, and the input module includes an LLC resonant conversion input module, which may include an LC resonant unit and a full-bridge or half-bridge inverter module. In a preferred embodiment of the present invention, the rectifier output module 400 may include various types of rectifier circuits such as full-wave rectification, full-bridge rectification, voltage doubler rectification, or current doubler rectification. In a preferred embodiment of the present invention, the rectifier output module 400 includes a full-bridge rectifier unit and an output filter unit. Here, the full-bridge rectifier unit may be a switch tube rectifier full-bridge or a diode rectifier full-bridge. In another preferred embodiment of the present invention, the rectifier output module includes a full-wave rectifier unit and an output filter unit. Here, the full-wave rectifier unit may be a switch tube full-wave rectifier unit or a diode full-wave rectifier unit. The output filter unit may include a filter capacitor.

[0032] In this preferred embodiment, since capacitors are respectively connected across the two ends of the path inductance between the first end and the second end of the secondary winding of the transformer module and the rectifier output module, the parasitic oscillation of the junction capacitance during the turn-on and turn-off process of the rectifier device in the output rectifier module can be suppressed, thereby greatly reducing the output voltage spike of the output rectifier module, thereby reducing the voltage stress of the output rectifier module and improving the circuit stability.

[0033] Figure 2 FIG. 2 is a circuit diagram of a second preferred embodiment of a converter circuit for suppressing output voltage spikes according to the present invention. Figure 1-2 As shown, the converter circuit for suppressing output voltage spikes includes a transformer module 200, an input module 100 arranged at the primary winding of the transformer module 200, a rectifier output module 400 arranged at the secondary winding of the transformer module 200, and a first capacitive suppression module 310 and a second capacitive suppression module 320. The first capacitive suppression module 310 is connected across the two ends of a first path inductance between the first end of the secondary winding and the first end of the rectifier output module 400; the second capacitive suppression module 320 is connected across the two ends of a second path inductance between the second end of the secondary winding and the second end of the rectifier output module 400.

[0034] Further Figure 2As shown, the input module 100 includes a full-bridge inverter unit composed of MOS tubes S1 to S4 and a resonant unit composed of a resonant inductor Lr and a resonant capacitor Cr. Of course, in other preferred embodiments of the present invention, the input module 100 may also include an input filter capacitor, or a full-bridge inverter unit composed of an IGBT tube or other switch tube, or any other known circuit or module.

[0035] Further Figure 2 As shown, the rectification output module 400 includes a full-bridge rectification unit and an output filtering unit. The full-bridge rectification unit is a diode rectifier bridge, which uses diodes for rectification. The full-bridge rectification unit includes a diode D1, a diode D2, a diode D3 and a diode D4. The anode of the diode D1 is connected to the cathode of the diode D2 and the first end of the rectification output module 400, and the anode of the diode D3 is connected to the cathode of the diode D4 and the second end of the rectification output module 400; the cathode of the diode D1 and the cathode of the diode D3 are connected to the output positive pole Vo+; the anode of the diode D2 and the anode of the diode D4 are connected to the output negative pole Vo-; the output filtering unit includes a filtering capacitor Co, which is connected between the output positive pole Vo+ and the output negative pole Vo-. An output load Ro can also be connected between the output positive pole Vo+ and the output negative pole Vo-.

[0036] Further Figure 2 As shown, the transformer module 200 includes a transformer T, and the transformer T includes a primary winding and a secondary winding. The first capacitive suppression module 310 and the second capacitive suppression module 320 respectively include a capacitor Cs1 and a capacitor Cs2, which are respectively connected across the parasitic inductance path on the output side of the transformer T, as follows. Capacitor Cs1 is connected across the two ends of the path inductance (i.e., parasitic inductance and / or leakage inductance) between the same-name end of the secondary winding of the transformer T and the anode of the diode D1 (i.e., the first end of the rectifier output module 400). Capacitor Cs2 is connected across the two ends of the path inductance (i.e., parasitic inductance and / or leakage inductance) between the opposite-name end of the secondary winding of the transformer T and the cathode of the diode D4 (i.e., the second end of the rectifier output module 400). Here, those skilled in the art can select adaptation values ​​for capacitor Cs1 and capacitor Cs2 according to actual conditions. By reasonably setting the size of capacitor Cs1 and capacitor Cs2, the junction capacitance of the rectifier diode during the conduction and shutdown process of the rectifier diode can be suppressed (see Figure 4 The junction capacitance Coss1 and Coss2 in the output rectifier module can reduce the parasitic oscillation, thereby greatly reducing the output voltage spike of the output rectifier module, thereby reducing the voltage stress of the output rectifier module and improving the circuit stability.

[0037] In a further preferred embodiment of the present invention, the first capacitive suppression module 310 and the second capacitive suppression module 320 may respectively include N capacitors, and the corresponding path inductance between the same-name end of the secondary winding of the transformer T and the anode of the diode D1 and the path inductance between the opposite-name end of the secondary winding of the transformer T and the cathode of the diode D4 may respectively include N series-connected inductors, and each capacitor is correspondingly connected across the two ends of an inductor; wherein N is a positive integer greater than 1. Similarly, by reasonably setting the size of these 2N capacitors, the parasitic oscillation of the junction capacitance of the rectifier diode during the conduction and shutdown process of the rectifier diode can be suppressed, so that the output voltage spike of the output rectifier module can be greatly reduced, thereby reducing the voltage stress of the output rectifier module, thereby improving the circuit stability.

[0038] Figure 3 FIG. 1 is a circuit diagram of a third preferred embodiment of a converter circuit for suppressing output voltage spikes according to the present invention. Figure 3 The circuit shown is Figure 2 The difference is that the full-bridge rectifier unit is a MOS tube rectifier bridge, which uses MOS tubes for rectification. Figure 3 As shown, the full-bridge rectifier unit includes MOS transistor SD1, MOS transistor SD2, MOS transistor SD3 and MOS transistor SD4. The gates of the MOS transistors SD1, MOS transistor SD2, MOS transistor SD3 and MOS transistor SD4 receive control signals. The source of the MOS transistor SD1 is connected to the drain of the MOS transistor SD2 and the first end of the rectifier output module 400, and the source of the MOS transistor SD3 is connected to the drain of the MOS transistor SD4 and the second end of the rectifier output module 400; the drain of the MOS transistor SD1 and the drain of the MOS transistor SD3 are connected to the output positive electrode Vo+; the source of the MOS transistor SD2 and the source of the MOS transistor SD4 are connected to the output negative electrode Vo-; the output filter unit includes a filter capacitor Co, which is connected between the output positive electrode Vo+ and the output negative electrode Vo-. An output load Ro can also be connected between the output positive electrode Vo+ and the output negative electrode Vo-.

[0039] Similarly, if Figure 3As shown, the first capacitive suppression module 310 and the second capacitive suppression module 320 respectively include a capacitor Cs1 and a capacitor Cs2, which are respectively connected across the parasitic inductance path on the output side of the transformer T, as follows. The capacitor Cs1 is connected across the two ends of the path inductance (i.e., parasitic inductance and / or leakage inductance) between the same-name end of the secondary winding of the transformer T and the source of the rectifier MOS tube SD1 (i.e., the first end of the rectifier output module 400). The capacitor Cs2 is connected across the two ends of the path inductance (i.e., parasitic inductance and / or leakage inductance) between the opposite-name end of the secondary winding of the transformer T and the drain of the rectifier MOS tube SD4 (i.e., the second end of the rectifier output module 400). Here, those skilled in the art can select adaptation values ​​for the capacitor Cs1 and the capacitor Cs2 according to actual conditions. By reasonably setting the size of the capacitor Cs1 and the capacitor Cs2, the junction capacitance of the rectifier MOS tube during the conduction and shutdown of the rectifier MOS tube can be suppressed (see Figure 5 The junction capacitance Coss1 and Coss2 in the circuit can be parasitic oscillated, so the output voltage spike of the output rectifier module can be greatly reduced, thereby reducing the voltage stress of the output rectifier module and improving the circuit stability. Selecting a synchronous rectifier with a lower withstand voltage level can reduce the on-resistance and device cost of the synchronous rectifier, which is beneficial to improving efficiency and reducing design costs.

[0040] Those skilled in the art know that the MOS tubes SD1 to SD4 may also be other switch tubes, such as IGBT tubes or triodes. When a triode is selected, the base of the triode receives a control signal, the emitter thereof corresponds to the source of the MOS tube, and the collector corresponds to the drain of the MOS tube. When an IGBT tube is selected, the gate of the IGBT tube receives a control signal, the source thereof corresponds to the source of the MOS tube, and the drain corresponds to the drain of the MOS tube.

[0041] In a further preferred embodiment of the present invention, the first capacitive suppression module 310 and the second capacitive suppression module 320 may respectively include N capacitors, and the corresponding path inductance between the same-name end of the secondary winding of the transformer T and the source of the rectifier MOS tube SD1 and the path inductance between the opposite-name end of the secondary winding of the transformer T and the drain of the rectifier MOS tube SD4 may respectively include N series-connected inductors, and each capacitor is correspondingly connected across the two ends of an inductor; wherein N is a positive integer greater than 1. Similarly, by reasonably setting the size of these 2N capacitors, the parasitic oscillation of the junction capacitance of the rectifier MOS tube during the conduction and shutdown process of the rectifier MOS tube can be suppressed, so that the output voltage spike of the output rectifier module can be greatly reduced, thereby reducing the voltage stress of the output rectifier module, thereby improving the circuit stability.

[0042] Figure 4 FIG. 4 is a circuit diagram of a converter circuit for suppressing output voltage spike according to a fourth preferred embodiment of the present invention. Figure 4 The circuit shown is Figure 2 Similar, the difference is that in Figure 4 In the preferred embodiment shown, a full-wave rectifier unit is used to replace the full-bridge rectifier unit, the secondary winding of the transformer module 200 includes a third end, and the converter circuit includes a first capacitive suppression module 310, a second capacitive suppression module 320, and a third capacitive suppression module. The first capacitive suppression module 310 is connected across the two ends of the first path inductance between the first end of the secondary winding and the first end of the full-wave rectifier unit; the second capacitive suppression module 320 is connected across the two ends of the second path inductance between the second end of the secondary winding and the second end of the full-wave rectifier unit; the third capacitive suppression module is connected across the two ends of the third path inductance between the third end of the secondary winding and the third end of the full-wave rectifier unit; the third end of the secondary winding is located between the first end and the second end of the secondary winding.

[0043] Further Figure 4 As shown, the secondary winding of the transformer module 200 includes a first secondary winding and a second secondary winding, the like-name end of the first secondary winding is the first end of the secondary winding, the unlike-name end of the second secondary winding is the second end of the secondary winding, and the unlike-name end of the first secondary winding is connected to the like-name end of the second secondary winding to form the third end of the secondary winding.

[0044] like Figure 4 As shown, the full-wave rectifier unit includes a diode D1 and a diode D2; the anode of the diode D1 is connected to the first end of the full-wave rectifier unit, and the cathode is connected to the output positive pole Vo+, the anode of the diode D2 is connected to the second end of the full-wave rectifier unit, and the second end of the second switching device is connected to the output positive pole Vo+; the third end of the full-wave rectifier unit is connected to the output negative pole Vo-.

[0045] like Figure 4 As shown, Coss1 and Coss2 represent the parasitic junction capacitances at both ends of the rectifier diodes D1 and D2, respectively. Ls1 represents the path inductance (i.e., parasitic inductance and / or leakage inductance) between the same-name end of the first secondary winding of the transformer T and the anode of the rectifier diode D1, Ls2 represents the path inductance (i.e., parasitic inductance and / or leakage inductance) between the center tap of the secondary winding of the transformer T (i.e., the connection point between the opposite-name end of the first secondary winding and the same-name end of the second secondary winding) and the cathode of the rectifier diode D1, and Ls3 represents the path inductance (i.e., parasitic inductance and / or leakage inductance) between the opposite-name end of the second secondary winding of the transformer T and the anode of the rectifier diode D2.

[0046] like Figure 4As shown, the first capacitive suppression module 310 includes a capacitor Cs1, the third capacitive suppression module includes a capacitor Cs2, and the second capacitive suppression module 320 includes a capacitor Cs3, which are respectively connected across the parasitic inductance path of the output side of the transformer T, as follows. The capacitor Cs1 is connected across the two ends of the path inductance Ls1 (i.e., parasitic inductance and / or leakage inductance) between the same-name end of the first secondary winding of the transformer T and the anode of the rectifier diode D1, the capacitor Cs2 is connected across the two ends of the path inductance (i.e., parasitic inductance and / or leakage inductance) Ls2 between the center tap of the secondary winding of the transformer T (i.e., the connection point of the opposite-name end of the first secondary winding and the same-name end of the second secondary winding) and the cathode of the rectifier diode D1, and the capacitor Cs3 is connected across the two ends of the path inductance Ls3 (i.e., parasitic inductance and / or leakage inductance) between the opposite-name end of the second secondary winding of the transformer T and the anode of the rectifier diode D2.

[0047] Here, those skilled in the art can select adaptation values ​​for capacitor Cs1, capacitor Cs2 and capacitor Cs3 according to actual conditions. By reasonably setting the sizes of capacitor Cs1, capacitor Cs2 and capacitor Cs3, the parasitic oscillation of the junction capacitance of the rectifier diode during the conduction and shutdown process of the rectifier diode can be suppressed, so the output voltage spike of the output rectifier module can be greatly reduced, thereby reducing the voltage stress of the output rectifier module, thereby improving the circuit stability.

[0048] In a further preferred embodiment of the present invention, the first capacitive suppression module 310, the third capacitive suppression module and the second capacitive suppression module 320 may respectively include N capacitors, corresponding to the path inductance Ls1 between the same-name end of the first secondary winding of the transformer T and the anode of the rectifier diode D1, the path inductance Ls2 between the center tap of the secondary winding of the transformer T and the cathode of the rectifier diode D1, and the two ends of the path inductance Ls3 (i.e., parasitic inductance and / or leakage inductance) between the opposite-name end of the second secondary winding of the transformer T and the anode of the rectifier diode D2 may respectively include N series-connected inductors, and each capacitor is correspondingly connected across the two ends of an inductor; wherein N is a positive integer greater than 1. Similarly, by reasonably setting the size of these 2N capacitors, the parasitic oscillation of the junction capacitance of the rectifier diode during the conduction and shutdown process of the rectifier diode can be suppressed, so that the output voltage spike of the output rectifier module can be greatly reduced, thereby reducing the voltage stress of the output rectifier module, thereby improving the circuit stability.

[0049] Figure 5 FIG. 5 is a circuit diagram of a fifth preferred embodiment of a converter circuit for suppressing output voltage spikes according to the present invention. Figure 5 The circuit shown is Figure 4Similarly, the only difference is that the full-wave rectifier unit is constructed by MOS transistors SD1 and SD2. The gates of the MOS transistors SD1 and SD2 receive control signals. The source of the MOS transistor SD1 is connected to the first end of the full-wave rectifier unit, and the drain is connected to the output positive electrode Vo+. The source of the MOS transistor SD2 is connected to the second end of the full-wave rectifier unit, and the drain is connected to the output positive electrode Vo+.

[0050] and Figure 4 Similar to the embodiment shown, the first capacitive suppression module 310 includes a capacitor Cs1, the third capacitive suppression module includes a capacitor Cs2, and the second capacitive suppression module 320 includes a capacitor Cs3, which are respectively connected across the parasitic inductance path of the output side of the transformer T, as follows. The capacitor Cs1 is connected across the two ends of the path inductance Ls1 (i.e., parasitic inductance and / or leakage inductance) between the same-name end of the first secondary winding of the transformer T and the source of the rectifier MOS tube SD1, the capacitor Cs2 is connected across the two ends of the path inductance (i.e., parasitic inductance and / or leakage inductance) Ls2 between the center tap of the secondary winding of the transformer T (i.e., the connection point of the opposite-name end of the first secondary winding and the same-name end of the second secondary winding) and the drain of the rectifier MOS tube SD1, and the capacitor Cs3 is connected across the two ends of the path inductance Ls3 (i.e., parasitic inductance and / or leakage inductance) between the opposite-name end of the second secondary winding of the transformer T and the source of the rectifier MOS tube SD2.

[0051] Here, those skilled in the art can select adaptation values ​​for capacitor Cs1, capacitor Cs2 and capacitor Cs3 according to actual conditions. By reasonably setting the values ​​of capacitor Cs1, capacitor Cs2 and capacitor Cs3, the parasitic oscillation of the junction capacitance of the rectifier MOS tube during the conduction and shutdown of the rectifier MOS tube can be suppressed, so the output voltage spike of the output rectifier module can be greatly reduced, thereby reducing the voltage stress of the output rectifier module, thereby improving the circuit stability.

[0052] Those skilled in the art know that the MOS tubes SD1-SD2 can also use other switch tubes, such as IGBT tubes or triodes. When a triode is selected, the base of the triode receives a control signal, the emitter corresponds to the source of the MOS tube, and the collector corresponds to the drain of the MOS tube. When an IGBT tube is selected, the gate of the IGBT tube receives a control signal, the source corresponds to the source of the MOS tube, and the drain corresponds to the drain of the MOS tube.

[0053] Figure 6 FIG. 6 is a circuit diagram of a sixth preferred embodiment of a converter circuit for suppressing output voltage spikes according to the present invention. Figure 6 The embodiment shown and Figure 4The embodiment shown is similar, except that each capacitive suppression module includes N capacitors, each path inductor includes N series-connected inductors, and each capacitor is connected across the two ends of an inductor; wherein N is a positive integer greater than 1. Figure 6 As shown, Ls1, Ls12, Ls13, etc. are parasitic inductances distributed in sequence along the routing path between the like-name end of the first winding of the secondary side of the transformer and the anode of the rectifier diode D1; Ls2, Ls22, Ls23 are parasitic inductances distributed in sequence along the routing path between the center tap of the secondary side of the transformer and the cathode of the rectifier diode D1; Ls3, Ls32, Ls33 are parasitic inductances distributed in sequence along the routing path between the opposite-name end of the second winding of the secondary side of the transformer and the anode of the rectifier diode D2. Cs1 is a capacitor across Ls1, Cs12 is a capacitor across Ls12, Cs13 is a capacitor across Ls13, and so on, capacitors are gradually connected across the parasitic inductance path; Cs2 is a capacitor across Ls2, Cs22 is a capacitor across Ls22, Cs23 is a capacitor across Ls23, and so on, capacitors are gradually connected across the parasitic inductance path; Cs3 is a capacitor across Ls3, Cs32 is a capacitor across Ls32, Cs33 is a capacitor across Ls33, and so on, capacitors are gradually connected across the parasitic inductance path. As mentioned above, by reasonably setting the size of the cross-over capacitor, the parasitic oscillation of the junction capacitance of the rectifier diode during the conduction and shutdown process of the rectifier diode can be suppressed, so that the output voltage spike of the output rectifier module can be greatly reduced, thereby reducing the voltage stress of the output rectifier module, thereby improving the circuit stability.

[0054] Figure 7 It is a schematic diagram of the output voltage at both ends of the rectifier tube of the rectifier output module of the resonant converter circuit in the prior art. Figure 8 Schematic diagram of the output voltage at both ends of the rectifier device of the rectifier output module of the converter circuit for suppressing output voltage spikes of the present invention. Figure 7 As shown in the figure, there is no cross-capacitor in the path inductance on the secondary winding side of the transformer module. When the rectifier (rectifier diode or switch tube) is turned on / off, the parasitic junction capacitance of the rectifier tube and the parasitic inductance of the loop form a parasitic oscillation, and a voltage oscillation peak is formed at both ends of the rectifier tube. At this time, the maximum voltage stress at both ends of the rectifier tube is 76V. Figure 8 As shown in the figure, under the action of the capacitor across the parasitic inductance on the secondary side of the transformer, under the same working conditions, the maximum voltage across the rectifier device (rectifier diode or switch tube) is 65V. Figure 7In comparison, the converter circuit for suppressing output voltage spikes of the present application can suppress the oscillation of the junction capacitance and parasitic inductance of the rectifier tube during the turning on and off process of the rectifier tube by connecting a capacitor across the parasitic inductance and leakage inductance of the wiring loop path on the secondary side of the transformer, thereby effectively reducing the voltage stress of the rectifier tube.

[0055] Although the present invention is described by specific embodiments, it should be understood by those skilled in the art that various changes and equivalent substitutions may be made to the present invention without departing from the scope of the present invention. In addition, various modifications may be made to the present invention for specific situations or materials without departing from the scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed, but should include all implementation methods falling within the scope of the claims of the present invention.

[0056] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A converter circuit for suppressing output voltage spikes, comprising a transformer module, an input module arranged at a primary winding of the transformer module, and a rectifier output module arranged at a secondary winding of the transformer module, characterized in that: The converter circuit for suppressing output voltage spikes also includes a first capacitive suppression module and a second capacitive suppression module; the first capacitive suppression module is connected across two ends of a first path inductor, and the first path inductor is located between the first end of the secondary winding and the first end of the rectifier output module; the second capacitive suppression module is connected across two ends of a second path inductor, and the second path inductor is located between the second end of the secondary winding and the second end of the rectifier output module; the capacitive suppression module only includes a capacitor.

2. The converter circuit for suppressing output voltage spike according to claim 1, characterized in that: The capacitive suppression module is composed of a single or multiple capacitors connected in series or in parallel.

3. The converter circuit for suppressing output voltage spike according to claim 1 or 2, characterized in that: The rectification output module includes a full-bridge rectification unit and an output filtering unit; The full-bridge rectifier unit includes a first switch device, a second switch device, a third switch device and a fourth switch device; The first end of the first switch device is connected to the second end of the second switch device and the first end of the rectifier output module, and the first end of the third switch device is connected to the second end of the fourth switch device and the second end of the rectifier output module; the second end of the first switch device and the second end of the third switch device are connected to the output positive electrode; the first end of the second switch device and the first end of the fourth switch device are connected to the output negative electrode; The output filter unit is connected between the output positive electrode and the output negative electrode.

4. The converter circuit for suppressing output voltage spike according to claim 3, characterized in that: The switch device includes a diode or a switch tube; When the switch device is a diode, the first end of the switch device is the anode of the diode, and the second end of the switch device is the cathode of the diode; When the switch device is a switch tube, the control end of the switch tube receives a control signal, the first end of the switch device is the first end of the switch tube, and the second end of the switch device is the second end of the switch tube.

5. The converter circuit for suppressing output voltage spike according to claim 1 or 2, characterized in that: The rectification output module includes a full-wave rectification unit and an output filtering unit; The converter circuit further includes a third capacitive suppression module; The first capacitive suppression module is connected across the two ends of a first path inductance between the first end of the secondary winding and the first end of the full-wave rectifier unit; the second capacitive suppression module is connected across the two ends of a second path inductance between the second end of the secondary winding and the second end of the full-wave rectifier unit; the third capacitive suppression module is connected across the two ends of a third path inductance between the third end of the secondary winding and the third end of the full-wave rectifier unit; the third end of the secondary winding is located between the first end of the secondary winding and the second end of the secondary winding.

6. The converter circuit for suppressing output voltage spike according to claim 5, characterized in that: The secondary winding of the transformer module includes a first secondary winding and a second secondary winding, the first end of the first secondary winding is the first end of the secondary winding, the second end of the first secondary winding is connected to the first end of the second secondary winding to form the third end of the secondary winding, and the second end of the second secondary winding is the second end of the secondary winding.

7. The converter circuit for suppressing output voltage peak according to claim 5, characterized in that: The full-wave rectification unit comprises a first switching device and a second switching device; The first end of the first switch device is connected to the first end of the full-wave rectifier unit, and the second end is connected to the output positive electrode; the first end of the second switch device is connected to the second end of the full-wave rectifier unit, and the second end of the second switch device is connected to the output positive electrode; the third end of the full-wave rectifier unit is connected to the output negative electrode; The output filter unit is connected between the output positive electrode and the output negative electrode.

8. The converter circuit for suppressing output voltage spike according to claim 7, characterized in that: The switch device includes a diode or a switch tube; When the switch device is a diode, the first end of the switch device is the anode of the diode, and the second end of the switch device is the cathode of the diode; When the switch device is a switch tube, the control end of the switch tube receives a control signal, the first end of the switch device is the first end of the switch tube, and the second end of the switch device is the second end of the switch tube.

9. The converter circuit for suppressing output voltage peak according to claim 2, characterized in that: Each of the capacitive suppression modules includes a capacitor, each of the path inductors includes an inductor, and the capacitor is connected across both ends of the inductor.

10. The converter circuit for suppressing output voltage spike according to claim 2, characterized in that: The capacitive suppression module includes N capacitors, the path inductance includes N series-connected inductors, and each capacitor is connected across two ends of an inductor; wherein N is a positive integer greater than 1.

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