Adaptive pulse control and method and signal converter for implementing the same

Abstract

The invention relates to adaptive pulse control and a method and a signal converter for implementing adaptive pulse control. The signal converter includes a pulse generator, a level shifter, and a controller. The pulse generator is configured to receive an input control signal for the switch driver. The pulse generator is further configured to generate a set control signal based on the input control signal. The level shifter is configured to generate an output control signal having a first amplitude greater than a second amplitude of the input control signal based on the set control signal. The level shifter is further configured to transmit the output control signal to the switch driver. The controller is configured to detect a common mode transient at a node coupled to the switch driver. The pulse generator is further configured to increase a pulse width of the set control signal when the controller detects a common mode transient.

Description

Technical Field

[0001] The present application relates to the technical field of power management, and in particular to adaptive pulse control in high voltage level shifters. Background Art

[0002] Level shifters are widely used in high voltage half-bridge applications to level shift high-side control signals between low voltage power domains and high voltage power domains. Since such applications can operate at frequencies ranging from tens to thousands of kilohertz and the control signals can be level shifted by up to hundreds of volts, it is desirable to minimize propagation delays and power losses. Summary of the invention

[0003] Set and reset pulses can be used to control a level shifter to generate a high voltage control signal from a low voltage control signal. Wide set and reset pulses improve transmission reliability during common mode transients, but also increase power loss. Narrow set and reset pulses minimize power loss, but also limit transmission reliability during common mode transients. The present disclosure provides a signal converter, a system for power conversion, and a method for adaptive pulse control that, among other things, widens the control pulses for the level shifter during common mode transients.

[0004] The present disclosure provides a signal converter, which in a specific implementation includes a pulse generator, a level shifter, and a controller. The pulse generator is configured to receive an input control signal for a switch driver. The pulse generator is also configured to generate a set control signal based on the input control signal. The level shifter is configured to generate an output control signal having a first amplitude greater than a second amplitude of the input control signal based on the set control signal. The level shifter is also configured to send the output control signal to the switch driver. The controller is configured to detect a common mode transient at a node coupled to the switch driver. The pulse generator is also configured to increase the pulse width of the set control signal when the controller detects a common mode transient.

[0005] The present disclosure also provides a system for power conversion, which in a specific implementation includes a power converter, a driver and a signal converter. The power converter includes a transistor. The driver is configured to control the transistor. The signal converter is configured to receive an input control signal for the driver. The signal converter is also configured to generate a set control signal based on the input control signal. The signal converter is also configured to generate an output control signal having a first voltage level higher than a second voltage level of the input control signal based on the set control signal. The signal converter is also configured to send the output control signal to the driver. The signal converter is also configured to detect common mode transients at a node coupled to the driver. The signal converter is also configured to increase the pulse width of the set control signal in response to detecting the common mode transient.

[0006] The present disclosure also provides a method for adaptive pulse control. The method includes receiving an input control signal for a transistor driver. The method also includes generating a set control signal based on the input control signal. The method also includes generating an output control signal having a first amplitude greater than a second amplitude of the input control signal based on the set control signal. The method also includes sending the output control signal to the transistor driver. The method also includes detecting a common mode transient at a node coupled to the transistor driver. The method also includes increasing a pulse width of the set control signal in response to detecting the common mode transient. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] To describe in detail exemplary embodiments, reference will now be made to the accompanying drawings, in which:

[0008] Figure 1A is a partial schematic diagram and a partial block diagram of an example of a power conversion system including a half-bridge driver according to some specific implementations;

[0009] Figure 1B is a partial schematic diagram and a partial block diagram of an example of a power conversion system including a floating driver according to some specific implementations;

[0010] Figure 2 It is based on some specific implementations including Figure 1A and Figure 1B A partial schematic diagram and a partial block diagram of an example of a signal converter in a system;

[0011] Figure 3 It is based on some specific implementations including Figure 2 A partial schematic diagram and a partial block diagram of an example of a level shifter in a signal converter;

[0012] Figure 4 a graph illustrating an example response of a pulse generator generating set and reset control signals of fixed length according to some implementations;

[0013] Figure 5 It is based on some specific implementations including Figure 2 A partial schematic diagram and a partial block diagram of an example of a controller in a signal converter;

[0014] Figure 6 is a flow chart of an example of a method for generating a pulse in a set control signal according to some implementations;

[0015] Figure 7 a graph illustrating an example response of a pulse generator generating a set control signal having an increased pulse width during a common mode transient according to some implementations;

[0016] Figure 8is a flow chart of an example of a method for generating a pulse in a reset control signal according to some implementations;

[0017] Fig. 9 a graph illustrating an example response of a pulse generator generating set and reset control signals having increased pulse widths during common mode transients according to some implementations; and

[0018] Fig.10 is a flow chart of an example of a method for adaptive pulse control according to some specific implementations.

[0019] definition

[0020] Various terms are used to refer to specific system components. Different companies may refer to a component by different names - this document is not intended to distinguish between components that differ in name but function the same. In the following discussion and in the claims, the terms "include" and "comprising" are used in an open-ended manner, and therefore, these terms should be interpreted to mean "including but not limited to...". In addition, the terms "couple" or "coupled" are intended to mean either an indirect connection or a direct connection. Thus, if a first device is coupled to a second device, that connection may be made through a direct connection or through an indirect connection via other devices and connections.

[0021] In reference to electrical devices, whether stand-alone or as part of an integrated circuit, the terms "input" and "output" refer to electrical connections to the electrical device and should not be construed as verbs requiring operation. For example, a differential amplifier such as an operational amplifier may have a first differential input and a second differential input, and these "inputs" define electrical connections to the operational amplifier and should not be construed as requiring signal inputs to the operational amplifier.

[0022] “Controller” shall mean, alone or in combination, an individual circuit component, an application specific integrated circuit (ASIC), one or more microcontrollers with control software, a reduced instruction set computer (RISC) with control software, a digital signal processor (DSP), one or more processors with control software, a programmable logic device (PLD), a field programmable gate array (FPGA), or a programmable system on a chip (PSOC) configured to read inputs and drive outputs in response to those inputs. DETAILED DESCRIPTION

[0023] This application claims priority to and the benefit of U.S. utility patent application serial number 18 / 462,240, filed on September 6, 2023, entitled “ADAPTIVE PULSE CONTROL FOR HIGH-VOLTAGE LEVEL SHIFTER,” the entire disclosure of which is hereby incorporated by reference for all purposes.

[0024] The following discussion relates to various embodiments of the present invention. Although one or more of these embodiments may be preferred, the disclosed embodiments should not be interpreted or otherwise used to limit the scope of the present disclosure, including the claims. In addition, it should be understood by those skilled in the art that the following description has a wide range of applications, and the discussion of any embodiment is only intended to be an example of that embodiment, and is not intended to indicate that the scope of the present disclosure, including the claims, is limited to that embodiment.

[0025] Various examples relate to systems and methods for adaptive pulse control of high voltage level shifters. More specifically, various examples relate to systems and methods for power conversion and related signal converters that increase the pulse width of set and reset control signals during common mode transients. The specification now turns to an exemplary system to guide the reader.

[0026] Figure 1A is a partial schematic diagram and a partial block diagram of an example of a system 100 for power conversion according to some implementations of the present disclosure. Figure 1A The system 100 shown includes a power converter 102 and a half-bridge driver 104. The methods described herein may be used with Figure 1A The system 100 shown may be used with a system having more components, fewer components, or different components than a system having a different configuration. In some implementations, the power converter 102 and the half-bridge driver 104 are separate components (e.g., Figure 1A In alternative implementations, the power converter 102 and the half-bridge driver 104 may be part of the same component. For example, both the power converter 102 and the half-bridge driver 104 may be located on a single printed circuit board or within a single chip housing.

[0027] Figure 1A The power converter 102 shown in FIG. 1 includes a high-side transistor 106 and a low-side transistor 108 coupled in a series configuration between an input voltage supply VBULK and a reference terminal 110 (eg, a ground terminal). The high-side transistor 106 and the low-side transistor 108 are connected in series. Figure 1A exemplified as a metal oxide semiconductor field effect transistor (MOSFET), specifically an N-channel MOSFET. However, other types of FETs (e.g., P-channel MOSFETs) may be used, and indeed other types of transistors (e.g., bipolar junction transistors (BJTs) and junction gate field effect transistors (JFETs)) may also be used. In some implementations, the high-side transistor 106 and the low-side transistor 108 are gallium nitride (GaN) transistors. In an alternative implementation, the high-side transistor 106 and the low-side transistor 108 are silicon carbide (SiC) transistors. Figure 1AThe half-bridge driver 104 shown in FIG. 1 includes a high-side driver 112, a low-side driver 114, and a signal converter 116. The high-side driver 112 (an example of a “switch driver” and a “transistor driver”) controls the high-side transistor 106, and the low-side driver 114 controls the low-side transistor 108 to generate a square wave at a bridge node 118 of the power converter 102. Figure 1A The illustrated power converter 102 also includes an inductor 120 and a first capacitor 122 , which together form a resonant tank circuit to filter the square wave and generate an output signal (eg, output VOUT).

[0028] The low-side transistor 108 operates in a low voltage power domain (eg, less than 10 volts). Therefore, to control the low-side transistor 108, the low-side driver 114 also operates in the low voltage power domain. For example, Figure 1A The low-side driver 114 shown in FIG. 1 is coupled to a low voltage power supply VCC. The high-side transistor 106 operates in a high voltage power domain (eg, greater than 100 volts). Therefore, in order to control the high-side transistor 106, the high-side driver 112 also operates in the high voltage power domain. Figure 1A The power converter 102 shown in FIG. 1 further includes a second capacitor 124 for generating a high voltage power supply VBOOT for the high-side driver 112 from the low voltage power supply VCC.

[0029] During the first state in which the high-side transistor 106 of the power converter 102 is turned off and the low-side transistor 108 is turned on, the charge is supplied to the second capacitor 124 from the low voltage power supply VCC through the diode 126. Subsequently, during the second state in which the high-side transistor 106 of the power converter 102 is turned on and the low-side transistor 108 is turned off, the bridge node 118 is shorted to the input voltage power supply VBULK through the high-side transistor 106. During the second state of the power converter 102, the charge stored in the second capacitor 124 cannot flow to the low voltage power supply VCC because the diode 126 is reversely polarized. Therefore, during the second state of the power converter 102, the charge stored in the second capacitor 124 is supplied to the high-side driver 112.

[0030] The half-bridge driver 104 receives a pair of complementary input control signals (eg, Figure 1AThe high-side input control signal HS_INPUT and the low-side input control signal LS_INPUT shown in the figure). The half-bridge driver 104 can receive the pair of complementary input control signals from a separate controller (not shown). The pair of complementary input control signals are low voltage signals (e.g., having an amplitude of less than 10 volts). As described above, the low-side driver 114 operates in a low voltage power domain. Therefore, the low-side input control signal LS_INPUT can directly drive the low-side driver 114, such as Figure 1A However, as also described above, the high-side driver 112 operates in the high voltage power domain. Therefore, the high-side input control signal HS_INPUT (which is a low voltage signal and is an example of an “input control signal”) cannot directly control the high-side driver 112.

[0031] The signal converter 116 is configured to adjust the amplitude of the high-side input control signal HS_INPUT between the low voltage power domain and the high voltage power domain in which the high-side driver 112 operates. As will be described in more detail below, the signal converter 116 generates a high-side output control signal (an example of an “output control signal”) that has an amplitude greater than the amplitude of the high-side input control signal HS_INPUT and is sufficient to control the high-side driver 112. Figure 1A As shown in , the signal converter 116 receives the high-side input control signal HS_INPUT at the input terminal 128. In addition, as shown in Figure 1A As shown in , the output terminal 130 of the signal converter 116 is coupled to the input of the high-side driver 112 to provide a high-side output control signal thereto. Figure 1A The signal converter 116 shown in FIG. 1 also includes a power connection 132 coupled to a high voltage supply VBOOT and a reference connection 134 coupled to the bridge node 118 .

[0032] In some implementations, the power converter 102 does not include the low-side transistor 108. Figure 1B In the embodiment, the low-side transistor 108 is replaced by a diode 136, the cathode of the diode is coupled to the high-side transistor 106, and the anode of the diode is coupled to the reference terminal 110. In such a specific implementation, Figure 1B As shown in FIG. 1 , the high-side driver 112 is replaced by a floating driver 138 and the low-side driver 114 is not included. The present description now turns to a description of the components located within the signal converter 116 .

[0033] Figure 2 is a partial schematic diagram and a partial block diagram of an example of a signal converter 116 according to some specific implementations of the present disclosure. Figure 2 The signal converter 116 shown in FIG. 1 includes a pulse generator 202, a level shifter 204, and a controller 206. In some implementations, the signal converter 116 may include Figure 2 For example, in addition to the connections described below, there will be additional input and output connections (e.g., power connections, reference voltage connections, and ground connections), but those additional input and output connections are not shown to avoid overcomplicating the drawing.

[0034] The pulse generator 202 is configured to generate a set control signal and a reset control signal based on the high-side input control signal HS_INPUT. For example, the pulse generator 202 may generate a pulse in the set control signal (an example of a "set pulse") in response to detecting the beginning of a pulse (an example of an "input pulse") in the high-side input control signal HS_INPUT. In addition, the pulse generator 202 may generate a pulse in the reset control signal (an example of a "reset pulse") in response to detecting the end of a pulse in the high-side input control signal HS_INPUT. Figure 2 The pulse generator 202 shown includes an input terminal 208, a first output terminal 210, a second output terminal 212, and a control terminal 214. The input terminal 208 is coupled to the input terminal 128 of the signal converter 116 to receive the high-side input control signal HS_INPUT. The first output terminal 210 is coupled to the level shifter 204 and the controller 206 to provide a set control signal thereto. The second output terminal 212 is coupled to the level shifter 204 and the controller 206 to provide a reset control signal thereto. The control terminal 214 is coupled to the controller 206 to receive a detection signal therefrom.

[0035] The level shifter 204 is configured to generate a high-side output control signal for the high-side driver 112 . Figure 2The level shifter 204 shown in the figure includes a first input terminal 216, a second input terminal 218, an output terminal 220, a power connection 222 and a reference connection 224. The first input terminal 216 of the level shifter 204 is coupled to the first output terminal 210 of the pulse generator 202 to receive the set control signal therefrom. The second input terminal 218 of the level shifter 204 is coupled to the second output terminal 212 of the pulse generator 202 to receive the reset control signal therefrom. The output terminal 220 of the level shifter 204 is coupled to the output terminal 130 of the signal converter 116 to send the high-side output control signal to the high-side driver 112. As will be described in more detail below, the level shifter 204 is configured to start generating pulses in the high-side output control signal in response to the set control signal, and stop generating the pulses in the output control signal in response to the reset control signal. The power connection 222 of the level shifter 204 is coupled to the high voltage power supply VBOOT via the power connection 132 of the signal converter 116. Reference connection 224 is coupled to bridge node 118 of power converter 102 via reference connection 134 of signal converter 116 .

[0036] Controller 206 is configured to detect common-mode transients at one or more nodes coupled to signal converter 116 , as will be described in greater detail below. Figure 2 The controller 206 shown in 2 includes a sense terminal 226 , a first input terminal 228 , a second input terminal 230 , and an output terminal 232 . Figure 2 102 is coupled to the bridge node 118 of the power converter 102 via the reference connection 134 of the signal converter 116. Alternatively or in addition, the sense terminal 226 of the controller 206 may be coupled to one or more other low impedance nodes. For example, the sense terminal 226 of the controller 206 may be coupled to the high voltage power supply VBOOT via the power connection 132 of the signal converter 116. The first input terminal 228 of the controller 206 is coupled to the first output terminal 210 of the pulse generator 202 to receive the set control signal therefrom. The second input terminal 230 of the controller 206 is coupled to the second output terminal 212 of the pulse generator 202 to receive the reset control signal therefrom. The output terminal 232 of the controller 206 is coupled to the control terminal 214 of the pulse generator 202 to provide a detection signal thereto. As will be described in more detail below, the controller 206 is configured to generate a detection signal when a common mode transient is detected at one or more nodes coupled to the signal converter 116. The description now turns to a description of the components located within level shifter 204 .

[0037] Figure 3 is a partial schematic diagram and a partial block diagram of an example of a level shifter 204 according to some specific implementations of the present disclosure. Figure 3The level shifter 204 shown in FIG. 1 includes an RS flip-flop 302, a first high voltage transistor 304, a second high voltage transistor 306, a first sense resistor 308, a second sense resistor 310, a first differential transistor 312, a second differential transistor 314, a first load resistor 316, and a second load resistor 318. In some implementations, the level shifter 204 may include Figure 3 More components, fewer components, or different components than those illustrated.

[0038] The RS flip-flop 302 is configured to generate a high-side output control signal based on a set control signal and a reset control signal. When the set control signal generated by the pulse generator 202 changes from low to high while the reset control signal generated by the pulse generator 202 remains low, the RS flip-flop 302 is placed in a set state. When placed in the set state, the RS flip-flop 302 changes the high-side output control signal from low to high. In addition, when the reset control signal generated by the pulse generator 202 changes from low to high while the set control signal generated by the pulse generator 202 remains low, the RS flip-flop 302 is placed in a reset state. When placed in the reset state, the RS flip-flop 302 changes the high-side output control signal from low to high. Figure 3 The RS flip-flop 302 shown in the figure includes a first input terminal 320, a second input terminal 322, an output terminal 324, a power connection 326, and a reference connection 328. The output terminal 324 of the RS flip-flop 302 is coupled to the high-side driver 112 via the output terminal 220 of the level shifter 204. The power connection 326 of the RS flip-flop 302 is coupled to the high voltage power supply VBOOT via the power connection 222 of the level shifter 204. The reference connection 328 of the RS flip-flop 302 is coupled to the bridge node 118 of the power converter 102 via the reference connection 224 of the level shifter 204.

[0039] The gate terminal of the first high voltage transistor 304 is coupled to the first input terminal 216 of the level shifter 204 to receive the set control signal from the pulse generator 202. The drain terminal of the first high voltage transistor 304 is coupled to the first sense resistor 308, the source terminal of the first differential transistor 312, and the gate terminal of the second differential transistor 314. The source terminal of the first high voltage transistor 304 is coupled to the reference terminal 110. The gate terminal of the second high voltage transistor 306 is coupled to the second input terminal 218 of the level shifter 204 to receive the reset control signal from the pulse generator 202. The drain terminal of the second high voltage transistor 306 is coupled to the second sense resistor 310, the gate terminal of the first differential transistor 312, and the source terminal of the second differential transistor 314. The source terminal of the second high voltage transistor 306 is coupled to the reference terminal 110. The first sense resistor 308 is coupled between the high voltage power supply VBOOT and the drain terminal of the first high voltage transistor 304. The second sensing resistor 310 is coupled between the high voltage power supply VBOOT and the drain terminal of the second high voltage transistor 306 .

[0040] The gate terminal of the first differential transistor 312 is coupled to the drain terminal of the second high voltage transistor 306, the second sense resistor 310, and the source terminal of the second differential transistor 314. The drain terminal of the first differential transistor 312 is coupled to the first load resistor 316 and the first input terminal 320 of the RS flip-flop 302. The source terminal of the first differential transistor 312 is coupled to the drain terminal of the first high voltage transistor 304, the first sense resistor 308, and the gate terminal of the second differential transistor 314. The gate terminal of the second differential transistor 314 is coupled to the drain terminal of the first high voltage transistor 304, the first sense resistor 308, and the source terminal of the first differential transistor 312. The drain terminal of the second differential transistor 314 is coupled to the second load resistor 318 and the second input terminal 322 of the RS flip-flop 302. The source terminal of the second differential transistor 314 is coupled to the drain terminal of the second high voltage transistor 306, the second sense resistor 310, and the gate terminal of the first differential transistor 312. The first load resistor 316 is coupled between the high voltage power supply VBOOT and the first input terminal 320 of the RS flip-flop 302. The second load resistor 318 is coupled between the high voltage power supply VBOOT and the second input terminal 322 of the RS flip-flop 302.

[0041] The drain terminals of the first high voltage transistor 304 and the second high voltage transistor 306 each have a parasitic capacitance. Even when the set and reset control signals are both kept low, these parasitic capacitances can also generate pulse signals. The first differential transistor 312 and the second differential transistor 314 act as comparators to prevent these unwanted parasitic pulse signals from reaching the RS trigger 302. In particular, only the differential voltage between the first sensing resistor 308 and the second sensing resistor 310, which is larger than the threshold voltage of the first differential transistor 312 or the second differential transistor 314, can be passed to the RS trigger 302. For example, when the first high voltage transistor 304 and the second high voltage transistor 306 each generate a parasitic pulse signal, the differential voltage between the first sensing resistor 308 and the second sensing resistor 310 is less than the threshold voltage of the first differential transistor 312 and the second differential transistor 314. Therefore, the parasitic pulse signal is not allowed to pass through to the RS trigger 302. However, when the set control signal changes from low to high while the reset control signal remains low, the differential voltage between the first sense resistor 308 and the second sense resistor 310 is greater than the threshold voltage of the first differential transistor 312. Therefore, the pulse generated by the set control signal on the first high voltage transistor 304 is allowed to pass through the comparator and the RS flip-flop 302 is placed in the set state. In addition, when the reset control signal changes from low to high while the set control signal remains low, the differential voltage between the first sense resistor 308 and the second sense resistor 310 is greater than the threshold voltage of the second differential transistor 314. Therefore, the pulse generated by the reset control signal on the second high voltage transistor 306 is allowed to pass through the comparator and the RS flip-flop 302 is placed in the reset state.

[0042] Although the level shifter 204 is configured to protect against parasitic pulse signals, the level shifter 204 is susceptible to common mode transients. Common mode transients can occur during zero voltage switching and zero current switching. For example, returning to Figure 1A, when the low-side transistor 108 is turned on (and the high-side transistor 106 is turned off), the current flows from the output VOUT to the low-side transistor 108 via the inductor 120. When the low-side transistor 108 is subsequently turned off, some residual current may be present in the LC filter formed by the inductor 120 and the first capacitor 122. Due to the polarization of the inductor 120, the residual current flows into the bridge node 118, which causes the voltage transition at the bridge node 118. This voltage transition at the bridge node 118 can apply current to the level shifter 204, which prevents the level shifter 204 from generating a large voltage difference between the first sensing resistor 308 and the second sensing resistor 310 in response to the pulse in the set or reset control signal. Therefore, when the set control signal changes from low to high and the reset control signal remains low, the common mode transient can prevent the level shifter 204 from placing the RS flip-flop 302 in the set state. Similarly, when the reset control signal changes from low to high while the set control signal remains low, the common mode transient may prevent the level shifter 204 from placing the RS flip-flop 302 in the reset state. In other words, the common mode transient may prevent the signal converter 116 from generating a pulse in the high-side output control signal in response to a pulse in the high-side input control signal HS_INPUT. For example, in Figure 4 In the response graph of , the pulse width of the second pulse in the set control signal and the reset control signal generated by the pulse generator 202 is shorter than the common mode transient (indicated by the transition in the top curve). Figure 4 As shown, the signal converter 116 does not generate a pulse in the high-side output control signal in response to a pulse in the set control signal generated by the pulse generator 202 during a common-mode transient.

[0043] One solution to address the effects of common-mode transients on level shifter 204 is to set the pulse width of the set and reset control signals to be large enough to last longer than the common-mode transient. For example, the pulse width of the set control signal may be set to be large enough to enable level shifter 204 to detect the pulse in the set control signal and place RS flip-flop 302 in the set state after the common-mode transient is complete. However, increasing the pulse width of the set and reset control signals also increases the power loss of level shifter 204. In current power converters (e.g., having a configuration that does not include a common-mode transient), the level shifter 204 may be subjected to a high power consumption. Figure 2 In the signal converter of the controller 206 of the power converter, the pulse widths of the set and reset control signals are predetermined and fixed. Therefore, designers of current power converters must set the pulse widths of the set and reset control signals to fixed values, which compromise between acceptable power loss and reliable transmission during common mode transients.

[0044] Figure 2The controller 206 eliminates the need to compromise between acceptable power loss and reliable transmission during common mode transients. In particular, the controller 206 generates a detection signal during a common mode transient, as will be described in more detail below, which causes the pulse generator 202 to increase the pulse width of the set and reset control signals during the common mode transient. Figure 5 is a partial schematic diagram and a partial block diagram of an example of a controller 206 according to some specific implementations of the present disclosure. Figure 5 The controller 206 shown includes a high voltage sensing capacitor 502, a load resistor 504, a Zener diode 506, a NAND gate 508, and a transistor 510. In some implementations, the controller 206 may include a Figure 5 For example, in some implementations, the controller 206 can include or be coupled to a bias source that applies a bias voltage to the sense terminal 226 of the controller 206 .

[0045] The high voltage sensing capacitor 502 is coupled to the bridge node 118 of the power converter 102 via the sensing terminal 226 of the controller 206. The high voltage sensing capacitor 502 is also coupled to the output terminal 232 of the controller 206. Before the common mode transient occurs at the bridge node 118, the sensing terminal 226 of the controller 206 is grounded and the high voltage sensing capacitor 502 is discharged. The load resistor 504 (which may include a passive element, an active element, or both) is coupled between the reference terminal 110 and the output terminal 232 of the controller 206. When the high voltage sensing capacitor 502 is discharged, the load resistor 504 grounds the output terminal 232 of the controller 206 to the reference terminal 110. Therefore, the controller 206 does not generate a detection signal before the common mode transient occurs at the bridge node 118. During the common mode transient at the bridge node 118, the high voltage sensing capacitor 502 conducts current. When the high voltage sensing capacitor 502 conducts current, the current from the high voltage sensing capacitor 502 flows through the load resistor 504. This current flowing through the load resistor 504 generates a voltage across the load resistor 504. The Zener diode 506 is coupled to the load resistor 504 in a parallel configuration and acts as a shunt device to maintain a constant voltage across the load resistor 504. Therefore, the high voltage sensing capacitor 502 is charged via the Zener diode 506 during the common mode transient. The constant voltage across the load resistor 504 sets the voltage level at the output terminal 232 of the controller 206 to a voltage level greater than the voltage level at the reference terminal 110. Therefore, the controller 206 generates a detection signal during the common mode transient at the bridge node 118. After the common mode transient at the bridge node 118, the high voltage sensing capacitor 502 stops conducting. When the high voltage sensing capacitor 502 stops conducting, the current flowing through the load resistor 504 charges the high voltage sensing capacitor 502, and the voltage level at the output terminal 232 of the controller 206 is set back to the voltage level at the reference terminal 110. Therefore, the controller 206 stops generating the detection signal after the common-mode transient at the bridge node 118 .

[0046] The NAND gate 508 and the transistor 510 are configured to reset the voltage level at the output terminal 232 of the controller 206 when both the set control signal and the reset control signal are set to low. The input of the NAND gate 508 is coupled to the first input terminal 228 and the second input terminal 230 of the controller 206 to receive the set and reset control signals generated by the pulse generator 202. The output of the NAND gate 508 is coupled to the gate terminal of the transistor 510. The transistor 510 is coupled between the reference terminal 110 and the output terminal 232 of the controller 206. When either the set or reset control signal is set to high, the output of the NAND gate 508 is set to low and the transistor 510 is turned off. When the transistor 510 is turned off, the controller 206 generates a detection signal during a common mode transient, as described above. Alternatively, when both the set control signal and the reset control signal are set to low, the output of the NAND gate 508 is set to high and the transistor 510 is turned on to maintain the voltage level at the output terminal 232 of the controller 206 at the voltage level at the reference terminal 110. Therefore, the NAND gate 508 and the transistor 510 prevent the controller 206 from generating a detection signal when both the set control signal and the reset control signal are set to low.

[0047] Pulse generator 202 provides reliable transmission of pulses in the set control signal during common mode transients by generating longer pulses in the set control signal during common mode transients. In addition, pulse generator 202 reduces overall power loss by generating shorter pulses in the set control signal when common mode transients do not occur. Figure 6 6 is a flow chart of an example of a method 600 for generating a pulse in a set control signal according to some specific implementations. To simplify the description, the method 600 is described as a series of operations performed by the pulse generator 202. However, the operations according to the method 600 may be performed by different components. At block 602, the pulse generator 202 detects the beginning of a pulse in an input control signal. For example, the pulse generator 202 may detect a rising edge in the high-side input control signal HS_INPUT. At block 604, the pulse generator 202 begins generating a pulse in the set control signal. For example, at Figure 7 In the response diagram of , the set control signal changes from low to high after the high-side input control signal HS_INPUT changes from low to high.

[0048] Return to Figure 6 At block 606 of the SET control signal generator 202, the pulse generator 202 determines whether it is receiving a detection signal. When the pulse generator 202 is not receiving a detection signal, at block 608, the pulse generator 202 waits for a predetermined period of time. For example, the pulse generator 202 may wait for approximately 20 nanoseconds. After the predetermined period of time, at block 610, the pulse generator 202 stops generating pulses in the SET control signal. For example, at Figure 7In the example above, there is no common-mode transient during the first pulse in the high-side input control signal HS_INPUT. Figure 7 As shown in , the first pulse in the set control signal lasts for a predetermined period of about 20 nanoseconds.

[0049] Return to Figure 6 At block 606 in the example, when the pulse generator 202 receives the detection signal while generating the pulse in the set control signal, the pulse generator 202 waits until the detection signal ends at block 612. Then, at block 608, the pulse generator 202 waits for the predetermined time period, and then stops generating the pulse in the set control signal at block 610. For example, at Figure 7 In FIG. 1 , there is a common mode transient during the second pulse in the high-side input control signal HS_INPUT (as indicated by the transition in the top curve). Figure 7 As shown in , the second pulse in the set control signal lasts about 20 nanoseconds after the common mode transient ends.

[0050] Pulse generator 202 provides reliable transmission of pulses in the reset control signal during common mode transients by generating longer pulses in the reset control signal during common mode transients. In addition, pulse generator 202 reduces overall power loss by generating shorter pulses in the reset control signal when common mode transients do not occur. Figure 8 8 is a flow chart of an example of a method 800 for generating a pulse in a reset control signal according to some specific implementations. To simplify the description, the method 800 is described as a series of operations performed by the pulse generator 202. However, the operations according to the method 800 may be performed by different components. At block 802, the pulse generator 202 detects the end of a pulse in an input control signal. For example, the pulse generator 202 may detect a falling edge in the high-side input control signal HS_INPUT. At block 804, the pulse generator 202 begins generating a pulse in the reset control signal. For example, at Fig. 9 In the response diagram of , the reset control signal changes from low to high after the high-side input control signal HS_INPUT changes from high to low.

[0051] Return to Figure 8 At block 806 of the embodiment, the pulse generator 202 determines whether it is receiving a detection signal. When the pulse generator 202 is not receiving a detection signal, at block 808, the pulse generator 202 waits for a predetermined period of time. For example, the pulse generator 202 may wait for approximately 20 nanoseconds. After the predetermined period of time, at block 810, the pulse generator 202 stops generating pulses in the reset control signal. For example, at Fig. 9 In the example above, there is no common-mode transient during the first pulse in the high-side input control signal HS_INPUT. Fig. 9As shown in , the first pulse in the reset control signal lasts for a predetermined period of about 20 nanoseconds.

[0052] Return to Figure 8 At block 806 in the reset control signal, when the pulse generator 202 receives the detection signal while generating the pulse in the reset control signal, the pulse generator 202 waits until the detection signal ends at block 812. Then, at block 808, the pulse generator 202 waits for the predetermined time period, and then stops generating the pulse in the reset control signal at block 810. For example, at Fig. 9 In FIG. 1 , there is a common mode transient during the second pulse in the high-side input control signal HS_INPUT (as indicated by the transition in the top curve). Fig. 9 As shown in , the second pulse in the reset control signal lasts about 20 nanoseconds after the common mode transient ends.

[0053] Overlapping pulses in the set and reset control signals may result in undesired operation. For example, overlapping pulses in the set control signal and the reset control signal may cause the RS flip-flop 302 in the level shifter 204 to enter an unstable state. To avoid this, the pulse generator 202 may generate pulses in only one of the set or reset control signals at any given time. As described above, the pulse generator 202 is configured to start generating pulses in the reset signal after the pulse in the high-side input control signal HS_INPUT ends. To avoid overlapping pulses, the pulse generator 202 is configured to stop generating pulses in the set control signal after the pulse in the high-side input control signal HS_INPUT ends. In some cases, the pulse generator 202 may stop generating pulses in the set control signal during a common-mode transient or during a predetermined time period after the common-mode transient ends. For example, during Fig. 9 In the example above, the second pulse in the high-side input control signal HS_INPUT ends before the common-mode transient ends. Fig. 9 As shown, the second pulse in the set control signal ends before the common mode transient ends.

[0054] Fig.10 1 is a flow chart of an example of a method 1000 for adaptive pulse control according to some specific implementations. To simplify the description, the method 1000 is described as a series of operations performed by different components of the signal converter 116. However, operations according to the method 1000 may be performed by other components. At block 1002, an input control signal for a transistor driver is received. For example, the pulse generator 202 may receive a control signal for a Figure 1A The high-side input control signal HS_INPUT of the high-side driver 112 is provided. In addition, the pulse generator 202 may receive a high-side input control signal HS_INPUT for Figure 1BAt block 1004, a set control signal is generated based on the input control signal. For example, when the pulse generator 202 detects a rising edge of the high-side input control signal HS_INPUT, the pulse generator 202 may generate a pulse in the set control signal. At block 1006, an output control signal is generated based on the set control signal. For example, when the level shifter 204 detects a pulse in the set control signal, the level shifter 204 may generate a pulse in the high-side output control signal. At block 1008, the output control signal is sent to the transistor driver. For example, the level shifter 204 may send the high-side output control signal to the transistor driver. Figure 1A In addition, the level shifter 204 can send the output control signal to the high-side driver 112. Figure 1B 138 of the floating driver 138. At block 1010, a common-mode transient is detected at a node coupled to the transistor driver. For example, the controller 206 may detect the common-mode transient at the bridge node 118 or at the high voltage power supply VBOOT. At block 1012, a pulse width of the set control signal is increased in response to detecting the common-mode transient. For example, when the controller 206 detects the common-mode transient at the bridge node 118 of the power converter 102, the pulse generator 202 may increase the pulse width of the pulse in the set control signal. In some implementations, the pulse generator 202 may also increase the pulse width of the pulse in the reset control signal when the controller 206 detects the common-mode transient, for example, at the bridge node 118 of the power converter 102.

[0055] In light of the foregoing disclosure, the examples of systems and methods listed in the following clauses are specifically contemplated and are intended as a non-limiting set of examples.

[0056] Clause 1. A signal converter comprising:

[0057] A pulse generator, the pulse generator being configured to:

[0058] receiving an input control signal for a switch driver, and

[0059] generating a set control signal based on the input control signal;

[0060] A level shifter, the level shifter being configured to:

[0061] generating an output control signal having a first amplitude greater than a second amplitude of the input control signal based on the set control signal, and

[0062] sending the output control signal to the switch driver; and

[0063] a controller configured to detect common mode transients at a node coupled to the switch driver,

[0064] The pulse generator is further configured to increase a pulse width of the set control signal when the controller detects the common mode transient.

[0065] Clause 2. A signal converter according to any clause herein, wherein the pulse generator is further configured to generate a reset control signal based on the input control signal, and wherein the level shifter is further configured to generate the output control signal based on the set control signal and the reset control signal.

[0066] Clause 3. A signal converter according to any clause herein, wherein the pulse width is a first pulse width, and wherein the pulse generator is further configured to increase a second pulse width of the reset control signal when the controller detects the common mode transient.

[0067] Clause 4. A signal converter according to any clause herein, wherein in order to increase the pulse width of the set control signal when the controller detects the common mode transient, the pulse generator is also configured to stop generating the set pulse in the set control signal after a predetermined time period after the end of the common mode transient.

[0068] Clause 5. The signal converter according to any clause herein, wherein to generate the set control signal based on the input control signal, the pulse generator is further configured to:

[0069] in response to detecting the start of an input pulse in the input control signal, starting to generate the set pulse in the set control signal, and

[0070] Responsive to detecting an end of the input pulse in the input control signal prior to the end of the common mode transient, generation of the set pulse in the set control signal is ceased.

[0071] Clause 6. The signal converter of any clause herein, wherein the switch driver is a high-side driver of a half-bridge driver.

[0072] Clause 7. A signal converter as described in any clause herein, wherein the switch driver is a floating driver.

[0073] Clause 8. A system for power conversion, comprising:

[0074] a power converter, the power converter comprising a transistor;

[0075] a driver configured to control the transistor; and

[0076] A signal converter, the signal converter being configured to:

[0077] receiving an input control signal for the driver,

[0078] generating a set control signal based on the input control signal,

[0079] generating an output control signal having a first voltage level higher than a second voltage level of the input control signal based on the set control signal,

[0080] sending the output control signal to the driver,

[0081] detects common-mode transients at nodes coupled to the driver, and

[0082] A pulse width of the set control signal is increased in response to detecting the common mode transient.

[0083] Clause 9. A system as described in any clause herein, wherein the transistor is a high-side transistor, wherein the power converter further comprises a low-side transistor, wherein the driver is a high-side driver, and wherein the system further comprises a low-side driver configured to control the low-side transistor.

[0084] Clause 10. The system of any clause herein, wherein the node coupled to the high-side driver is a bridge node coupled between the high-side transistor and the low-side transistor.

[0085] Clause 11. A system as described in any clause herein, wherein the driver is a floating driver, and wherein the power converter further comprises a diode having:

[0086] coupled to the cathode of the transistor, and

[0087] Anode coupled to the reference terminal.

[0088] Clause 12. A system according to any clause herein, wherein the signal converter is further configured to:

[0089] generating a reset control signal based on the input control signal, and

[0090] The output control signal is generated based on the set control signal and the reset control signal.

[0091] Clause 13. The system of any clause herein, wherein the pulse width is a first pulse width, and wherein the signal converter is further configured to increase a second pulse width of the reset control signal in response to detecting the common mode transient.

[0092] Clause 14. A system according to any clause herein, wherein in order to increase the pulse width of the set control signal in response to detecting the common mode transient, the signal converter is further configured to stop generating the set pulse in the set control signal after a predetermined time period after the end of the common mode transient.

[0093] Clause 15. A system according to any clause herein, wherein to generate the set control signal based on the input control signal, the signal converter is further configured to:

[0094] in response to detecting the start of an input pulse in the input control signal, starting to generate the set pulse in the set control signal, and

[0095] Responsive to detecting an end of the input pulse in the input control signal prior to the end of the common mode transient, generation of the set pulse in the set control signal is ceased.

[0096] Clause 16. A method for adaptive pulse control, the method comprising:

[0097] receiving an input control signal for a transistor driver;

[0098] generating a set control signal based on the input control signal;

[0099] generating an output control signal having a first amplitude greater than a second amplitude of the input control signal based on the set control signal;

[0100] sending the output control signal to the transistor driver;

[0101] detecting common mode transients at a node coupled to the transistor driver; and

[0102] A pulse width of the set control signal is increased in response to detecting the common mode transient.

[0103] Clause 17. A method according to any clause herein, further comprising:

[0104] generating a reset control signal based on the input control signal; and

[0105] The output control signal is generated based on the set control signal and the reset control signal.

[0106] Clause 18. The method of any clause herein, wherein the pulse width is a first pulse width, and wherein the method further comprises increasing a second pulse width of the reset control signal in response to detecting the common mode transient.

[0107] Clause 19. The method of any clause herein, wherein increasing the pulse width of the set control signal in response to detecting the common mode transient further comprises ceasing to generate set pulses in the set control signal after a predetermined period of time after the end of the common mode transient.

[0108] Clause 20. The method of any clause herein, wherein generating the set control signal based on the input control signal further comprises:

[0109] detecting the start of an input pulse in the input control signal,

[0110] in response to detecting the start of the input pulse in the input control signal, starting to generate the set pulse in the set control signal,

[0111] detecting the end of the input pulse in the input control signal, and

[0112] Responsive to detecting the end of the input pulse in the input control signal prior to the end of the common mode transient, ceasing to generate the set pulse in the set control signal.

[0113] Many electrical connections in the drawings are shown as directly coupled without intervening devices, but are not explicitly described as such in the above description. However, for electrical connections shown in the drawings without intervening devices, this paragraph should serve as an antecedent basis for the claims for referring to any electrical connection as "directly coupled."

[0114] The above discussion is intended to illustrate the principles and various embodiments of the present invention. Once the above disclosure is fully understood, many variations and modifications will become apparent to those skilled in the art. The following claims are interpreted as being intended to include all such variations and modifications.

Claims

1. A signal converter, comprising: A pulse generator, the pulse generator being configured to: receiving an input control signal for a switch driver, and generating a set control signal based on the input control signal; A level shifter, the level shifter being configured to: generating an output control signal having a first amplitude greater than a second amplitude of the input control signal based on the set control signal, and sending the output control signal to the switch driver; and a controller configured to detect common mode transients at a node coupled to the switch driver, The pulse generator is further configured to increase a pulse width of the set control signal when the controller detects the common mode transient.

2. The signal converter of claim 1, wherein the pulse generator is further configured to generate a reset control signal based on the input control signal, and wherein the level shifter is further configured to generate the output control signal based on the set control signal and the reset control signal. 3 . The signal converter of claim 2 , wherein the pulse width is a first pulse width, and wherein the pulse generator is further configured to increase a second pulse width of the reset control signal when the controller detects the common mode transient. The signal converter of claim 1 , wherein the switch driver is a high-side driver of a half-bridge driver. The signal converter of claim 1 , wherein the switch driver is a floating driver.

6. A method for adaptive pulse control, the method comprising: receiving an input control signal for a transistor driver; generating a set control signal based on the input control signal; generating an output control signal having a first amplitude greater than a second amplitude of the input control signal based on the set control signal; sending the output control signal to the transistor driver; detecting a common mode transient at a node coupled to the transistor driver; as well as A pulse width of the set control signal is increased in response to detecting the common mode transient.

7. The method according to claim 6, further comprising: generating a reset control signal based on the input control signal; as well as The output control signal is generated based on the set control signal and the reset control signal.

8. The method of claim 7, wherein the pulse width is a first pulse width, and wherein the method further comprises increasing a second pulse width of the reset control signal in response to detecting the common mode transient.

9. The method of claim 6, wherein increasing the pulse width of the set control signal in response to detecting the common mode transient further comprises ceasing to generate set pulses in the set control signal after a predetermined period of time after the common mode transient ends.

10. The method of claim 9, wherein generating the set control signal based on the input control signal further comprises: detecting the start of an input pulse in the input control signal, in response to detecting the start of the input pulse in the input control signal, starting to generate the set pulse in the set control signal, detecting the end of the input pulse in the input control signal, and Responsive to detecting the end of the input pulse in the input control signal prior to the end of the common mode transient, ceasing to generate the set pulse in the set control signal.

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