Chip power-on reset circuit

Abstract

A chip power-on reset circuit disclosed by the present invention comprises a sampling unit and a control unit, the control unit is connected with the sampling unit, the sampling unit is used for collecting the voltage when a chip is powered on and feeding back the voltage to the control unit, and the control unit feeds back a chip reset signal based on the feedback of the sampling unit and the working voltage range of the chip. The control unit comprises an eighth resistor, a ninth resistor, a tenth resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a second operational amplifier and a seventh operational amplifier, one end of the ninth resistor and one end of the thirteenth resistor are connected with the power supply, and the other end of the ninth resistor is connected with one end of the tenth resistor and the in-phase end of the second operational amplifier; the inverting end of the second operational amplifier is connected with one end of the eighth resistor, the output end of the second operational amplifier is connected with the other end of the eighth resistor, and the other end of the thirteenth resistor is connected with one end of the fourteenth resistor and the in-phase end of the seventh operational amplifier.

Description

Technical Field

[0001] The present invention relates to the technical field of on-chip power-on reset, and in particular to an on-chip power-on reset circuit. Background Art

[0002] Before and during the power-on process of the chip, the component states of the internal circuit of the chip are in an uncertain state. The power-on reset can clear these uncertain states and put the internal circuit of the chip into an initial state so that the chip can operate normally and output correct operation signals. Publication No. CN102111136A discloses a chip power-on reset circuit, which can reduce the power consumption of the power-on reset circuit after the power supply is stable. However, the circuit is not compatible with the reset methods required by different signal chips, nor can it feedback the required reset signal and reset method according to the voltage jitter state during power-on based on the operating voltage range of the chip. Summary of the invention

[0003] In view of the above technical problems, the purpose of the present invention is to provide a chip power-on reset circuit, including a sampling unit and a control unit, the control unit and the sampling unit are connected, the sampling unit is used to collect the voltage when the chip is powered on and feed it back to the control unit, the control unit feeds back a chip reset signal based on the feedback of the sampling unit and the working voltage range of the chip, the control unit includes an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a second operational amplifier U2, and a seventh operational amplifier U7, one end of the ninth resistor R9 and one end of the thirteenth resistor R13. The ninth resistor R9 is connected to the power supply, the other end of the ninth resistor R9 is connected to one end of the tenth resistor R10 and the in-phase end of the second operational amplifier U2, the inverting end of the second operational amplifier U2 is connected to one end of the eighth resistor R8, the output end of the second operational amplifier U2 is connected to the other end of the eighth resistor R8, the other end of the thirteenth resistor R13 is connected to one end of the fourteenth resistor R14 and the in-phase end of the seventh operational amplifier U7, the inverting end of the seventh operational amplifier U7 is connected to one end of the twelfth resistor R12, the output end of the seventh operational amplifier U7 is connected to the other end of the twelfth resistor R12, the other end of the tenth resistor R10, the other end of the fourteenth resistor R14 and the ground terminal are connected.

[0004] Furthermore, the control unit also includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eleventh resistor R11, a first operational amplifier U1, and a fifth operational amplifier U5, wherein one end of the first resistor R1 is connected to the output end of the first operational amplifier U1, the in-phase end of the first operational amplifier U1 is connected to one end of the second resistor R2 and one end of the third resistor R3, the other end of the third resistor R3 is connected to the output end of the second operational amplifier U2 and one end of the fifth resistor R5, and the first operational amplifier U1 is connected to the output end of the fifth resistor R5. The inverting end of the amplifier U1 is connected to the other end of the first resistor R1 and one end of the fourth resistor R4, the other end of the fourth resistor R4 is connected to one end of the seventh resistor R7 and the output end of the seventh operational amplifier U7, the other end of the seventh resistor R7 is connected to the other end of the fifth resistor R5 and the in-phase end of the fifth operational amplifier U5, the inverting end of the fifth operational amplifier U5 is connected to one end of the sixth resistor R6 and one end of the eleventh resistor R11, the other end of the sixth resistor R6 is connected to the output end of the fifth operational amplifier U5, and the other end of the second resistor R2, the other end of the eleventh resistor R11 are connected to the ground end.

[0005] Furthermore, the control unit also includes a third operational amplifier U3, a sixth operational amplifier U6, a third MOS tube Q3, a first diode D1, a second diode D2, and a first connector P1. The third operational amplifier U3 is connected to the inverting end of the sixth operational amplifier U6 and the first connector P1. The inverting end of the third operational amplifier U3 is connected to the output end of the fifth operational amplifier U5. The output end of the third operational amplifier U3 is connected to the anode of the second diode D2. The cathode of the second diode D2 is connected to the cathode of the first diode D1 and the gate of the third MOS tube Q3. The anode of the first diode D1 is connected to the output end of the sixth operational amplifier U6. The inverting end of the sixth operational amplifier U6 is connected to the output end of the first operational amplifier U1. The source of the third MOS tube Q3 is connected to the ground end.

[0006] Further, the control unit also includes a fifteenth resistor R15, a sixteenth resistor R16, a nineteenth resistor R19, a twentieth resistor R20, a twenty-first resistor R21, a first MOS tube Q1, a second MOS tube Q2, and a first capacitor C1, wherein one end of the fifteenth resistor R15 is connected to the power supply, the other end of the fifteenth resistor R15 is connected to one end of the sixteenth resistor R16 and the source of the first MOS tube Q1, the gate of the first MOS tube Q1 is connected to the output end of the sixth operational amplifier U6, the drain of the first MOS tube Q1 is connected to one end of the twentieth resistor R20 and the source of the second MOS tube Q2, the gate of the second MOS tube Q2 is connected to the output end of the third operational amplifier U3, the drain of the second MOS tube Q2 is connected to one end of the nineteenth resistor R19 and one end of the twenty-first resistor R21, the other end of the nineteenth resistor R19 is connected to one end of the first capacitor C1, and the other end of the sixteenth resistor R16, the other end of the twentieth resistor R20, the other end of the twenty-first resistor R21, and the other end of the first capacitor C1 are connected to the ground.

[0007] Furthermore, the control unit also includes a twenty-third resistor R23, a twenty-fourth resistor R24, a twenty-sixth resistor R26, a twenty-seventh resistor R27, a twenty-eighth resistor R28, a twenty-ninth resistor R29, a fourth operational amplifier U4, a fourth transistor Q4, and a second connector P2, one end of the twenty-sixth resistor R26 and one end of the twenty-ninth resistor R29 are connected to the power supply, the other end of the twenty-sixth resistor R26 and one end of the twenty-seventh resistor R27 are connected to the in-phase end of the fourth operational amplifier U4, and the inverting end of the fourth operational amplifier U4 is connected to the first transistor Q4. One end of the capacitor C1 is connected to the drain of the third MOS tube Q3, the output end of the fourth operational amplifier U4 is connected to one end of the twenty-third resistor R23 and the base of the fourth transistor Q4, the collector of the fourth transistor Q4 is connected to one end of the twenty-fourth resistor R24 ​​and the second connector P2, the emitter of the fourth transistor Q4 is connected to one end of the twenty-eighth resistor R28 and the other end of the twenty-ninth resistor R29, the other end of the twenty-third resistor R23, the other end of the twenty-fourth resistor R24, the other end of the twenty-seventh resistor R27, the other end of the twenty-eighth resistor R28 and the ground end are connected.

[0008] Furthermore, the control unit also includes a twenty-fifth resistor R25, a fifth MOS tube Q5, and a third connector P3, one end of the twenty-fifth resistor R25 is connected to the source of the fifth MOS tube Q5 and the third connector P3, the gate of the fifth MOS tube Q5 is connected to the base of the fourth transistor Q4, the drain of the fifth MOS tube Q5 is connected to the emitter of the fourth transistor Q4, and the other end of the twenty-fifth resistor R25 is connected to the ground end.

[0009] Furthermore, the control unit also includes a seventeenth resistor R17 and an eighteenth resistor R18, one end of the eighteenth resistor R18 is connected to the gate of the first MOS tube Q1, one end of the seventeenth resistor R17 is connected to the gate of the second MOS tube Q2, and the other end of the seventeenth resistor R17 and the other end of the eighteenth resistor R18 are connected to the ground end.

[0010] Furthermore, the control unit also includes a twenty-second resistor R22, one end of the twenty-second resistor R22 is connected to the gate of the third MOS transistor Q3, and the other end of the twenty-second resistor R22 is connected to the ground.

[0011] The beneficial effects of the present invention compared with the prior art are:

[0012] The present invention is compatible with the reset modes required by different signal chips, and can also feed back the required reset signal and reset mode according to the voltage jitter state during the power-on process based on the working voltage range of the chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the prior art and the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0014] Figure 1 The present invention provides an overall structural diagram.

[0015] Figure 2 This is a schematic diagram of the circuit structure of the control unit provided by the present invention. DETAILED DESCRIPTION

[0016] In order to make the objects and advantages of the present invention more clearly understood, the present invention is specifically described below in conjunction with embodiments. It should be understood that the following text is only used to describe one or several specific implementations of the present invention, and does not strictly limit the scope of protection specifically requested by the present invention.

[0017] The present invention discloses a chip power-on reset circuit, including a sampling unit and a control unit. The control unit is connected to the sampling unit. The sampling unit is used to collect the voltage when the chip is powered on and feed it back to the control unit. The control unit feeds back a chip reset signal based on the feedback of the sampling unit and the working voltage range of the chip. The control unit includes an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a second operational amplifier U2, and a seventh operational amplifier U7. One end of the ninth resistor R9 and one end of the thirteenth resistor R13 are connected to a power supply. The other end of the ninth resistor R9 is connected to one end of the tenth resistor R10 and the in-phase end of the second operational amplifier U2, the inverting end of the second operational amplifier U2 is connected to one end of the eighth resistor R8, the output end of the second operational amplifier U2 is connected to the other end of the eighth resistor R8, the other end of the thirteenth resistor R13 is connected to one end of the fourteenth resistor R14 and the in-phase end of the seventh operational amplifier U7, the inverting end of the seventh operational amplifier U7 is connected to one end of the twelfth resistor R12, the output end of the seventh operational amplifier U7 is connected to the other end of the twelfth resistor R12, the other end of the tenth resistor R10, the other end of the fourteenth resistor R14 and the ground end are connected.

[0018] Specifically, the control unit also includes a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eleventh resistor R11, a first operational amplifier U1, and a fifth operational amplifier U5. One end of the first resistor R1 is connected to the output end of the first operational amplifier U1, the in-phase end of the first operational amplifier U1 is connected to one end of the second resistor R2 and one end of the third resistor R3, the other end of the third resistor R3 is connected to the output end of the second operational amplifier U2 and one end of the fifth resistor R5, and the first operational amplifier U1 is connected to the output end of the fifth resistor R5. The inverting end of the amplifier U1 is connected to the other end of the first resistor R1 and one end of the fourth resistor R4, the other end of the fourth resistor R4 is connected to one end of the seventh resistor R7 and the output end of the seventh operational amplifier U7, the other end of the seventh resistor R7 is connected to the other end of the fifth resistor R5 and the in-phase end of the fifth operational amplifier U5, the inverting end of the fifth operational amplifier U5 is connected to one end of the sixth resistor R6 and one end of the eleventh resistor R11, the other end of the sixth resistor R6 is connected to the output end of the fifth operational amplifier U5, and the other end of the second resistor R2, the other end of the eleventh resistor R11 are connected to the ground end.

[0019] Specifically, the control unit also includes a third operational amplifier U3, a sixth operational amplifier U6, a third MOS tube Q3, a first diode D1, a second diode D2, and a first connector P1. The third operational amplifier U3 is connected to the inverting end of the sixth operational amplifier U6 and the first connector P1. The inverting end of the third operational amplifier U3 is connected to the output end of the fifth operational amplifier U5. The output end of the third operational amplifier U3 is connected to the anode of the second diode D2. The cathode of the second diode D2 is connected to the cathode of the first diode D1 and the gate of the third MOS tube Q3. The anode of the first diode D1 is connected to the output end of the sixth operational amplifier U6. The inverting end of the sixth operational amplifier U6 is connected to the output end of the first operational amplifier U1. The source of the third MOS tube Q3 is connected to the ground end.

[0020] Specifically, the control unit also includes a fifteenth resistor R15, a sixteenth resistor R16, a nineteenth resistor R19, a twentieth resistor R20, a twenty-first resistor R21, a first MOS transistor Q1, a second MOS transistor Q2, and a first capacitor C1. One end of the fifteenth resistor R15 is connected to the power supply, the other end of the fifteenth resistor R15 is connected to one end of the sixteenth resistor R16 and the source of the first MOS transistor Q1, the gate of the first MOS transistor Q1 is connected to the output end of the sixth operational amplifier U6, the drain of the first MOS transistor Q1 is connected to one end of the twentieth resistor R20 and the source of the second MOS transistor Q2, the gate of the second MOS transistor Q2 is connected to the output end of the third operational amplifier U3, the drain of the second MOS transistor Q2 is connected to one end of the nineteenth resistor R19 and one end of the twenty-first resistor R21, the other end of the nineteenth resistor R19 is connected to one end of the first capacitor C1, and the other end of the sixteenth resistor R16, the other end of the twentieth resistor R20, the other end of the twenty-first resistor R21, and the other end of the first capacitor C1 are connected to the ground.

[0021] Specifically, the control unit also includes a twenty-third resistor R23, a twenty-fourth resistor R24, a twenty-sixth resistor R26, a twenty-seventh resistor R27, a twenty-eighth resistor R28, a twenty-ninth resistor R29, a fourth operational amplifier U4, a fourth transistor Q4, and a second connector P2, one end of the twenty-sixth resistor R26 and one end of the twenty-ninth resistor R29 are connected to the power supply, the other end of the twenty-sixth resistor R26 and one end of the twenty-seventh resistor R27 are connected to the same phase end of the fourth operational amplifier U4, and the inverting end of the fourth operational amplifier U4 is connected to the first power supply. One end of the capacitor C1 is connected to the drain of the third MOS tube Q3, the output end of the fourth operational amplifier U4 is connected to one end of the twenty-third resistor R23 and the base of the fourth transistor Q4, the collector of the fourth transistor Q4 is connected to one end of the twenty-fourth resistor R24 ​​and the second connector P2, the emitter of the fourth transistor Q4 is connected to one end of the twenty-eighth resistor R28 and the other end of the twenty-ninth resistor R29, the other end of the twenty-third resistor R23, the other end of the twenty-fourth resistor R24, the other end of the twenty-seventh resistor R27, the other end of the twenty-eighth resistor R28 and the ground end are connected.

[0022] Specifically, the control unit also includes a twenty-fifth resistor R25, a fifth MOS tube Q5, and a third connector P3, one end of the twenty-fifth resistor R25 is connected to the source of the fifth MOS tube Q5 and the third connector P3, the gate of the fifth MOS tube Q5 is connected to the base of the fourth transistor Q4, the drain of the fifth MOS tube Q5 is connected to the emitter of the fourth transistor Q4, and the other end of the twenty-fifth resistor R25 is connected to the ground end.

[0023] Specifically, the control unit also includes a seventeenth resistor R17 and an eighteenth resistor R18, one end of the eighteenth resistor R18 is connected to the gate of the first MOS tube Q1, one end of the seventeenth resistor R17 is connected to the gate of the second MOS tube Q2, and the other end of the seventeenth resistor R17 and the other end of the eighteenth resistor R18 are connected to the ground end.

[0024] Specifically, the control unit further includes a twenty-second resistor R22, one end of the twenty-second resistor R22 is connected to the gate of the third MOS tube Q3, and the other end of the twenty-second resistor R22 is connected to the ground.

[0025] See attached Figure 1 , Attachment Figure 2In this embodiment, the sampling unit is used to collect the voltage when the chip is powered on and feed it back to the control unit. The control unit feeds back a chip reset signal based on the feedback of the sampling unit and the working voltage range of the chip. The power supply signal is looped to the ground terminal through the ninth resistor R9 and the tenth resistor R10. The signal at the tenth resistor R10 end is fed back to the in-phase terminal of the second operational amplifier U2. The signal amplitude at the tenth resistor R10 end can be changed by adjusting the resistance value of the tenth resistor R10. The signal amplitude at the tenth resistor R10 end is the setting amplitude of the working voltage of the chip. The output end of the second operational amplifier U2 is negatively fed back to the inverting terminal of the second operational amplifier U2 through the eighth resistor R8. The power supply signal is connected to prevent the lower circuit signal interference, and the power supply signal is looped to the ground terminal through the thirteenth resistor R13 and the fourteenth resistor R14. The signal amplitude at the fourteenth resistor R14 end can be changed by adjusting the resistance value of the fourteenth resistor R14. The signal amplitude at the fourteenth resistor R14 end is the specified deviation value of the chip's operating voltage. The signal at the fourteenth resistor R14 end is fed back to the in-phase terminal of the seventh operational amplifier U7. The output terminal of the seventh operational amplifier U7 is negatively feedback connected through the twelfth resistor R12 and the inverting terminal of the seventh operational amplifier U7 to prevent the lower circuit signal interference, thereby preventing the lower circuit interference while setting the chip's operating voltage and its specified deviation.

[0026] See attached Figure 2 In this embodiment, the output terminal signal of the second operational amplifier U2 is fed to the grounding terminal loop through the third resistor R3 and the second resistor R2, and the signal at the second resistor R2 terminal is fed back to the non-inverting terminal of the first operational amplifier U1. At the same time, the output terminal signal of the seventh operational amplifier U7 is fed back to the inverting terminal of the first operational amplifier U1 after passing through the fourth resistor R4. The output terminal of the first operational amplifier U1 is negatively feedback connected to the inverting terminal of the first operational amplifier U1 through the first resistor R1 and the inverting terminal of the first operational amplifier U1, so that the amplitude of the signal at the output terminal of the first operational amplifier U1 is the specified lower deviation value of the chip working voltage. The output terminal signal of the seventh operational amplifier U7 is fed back to the non-inverting terminal of the fifth operational amplifier U5 after passing through the seventh resistor R7. At the same time, the output terminal signal of the second operational amplifier U2 is fed back to the non-inverting terminal of the fifth operational amplifier U5 after passing through the fifth resistor R5. The output terminal signal of the fifth operational amplifier U5 is fed back to the grounding terminal loop through the sixth resistor R6 and the eleventh resistor R11. The signal at the eleventh resistor R11 terminal is fed back to the inverting terminal of the fifth operational amplifier U5, so that the amplitude of the signal at the output terminal of the fifth operational amplifier U5 is the specified upper deviation value of the chip working voltage, so that when the chip sets the working voltage and its specified deviation value, its working voltage range can be automatically calculated.

[0027] See attached Figure 2In this embodiment, the sampling unit collects the voltage when the chip is powered on and feeds it back to the first connector P1 on the control unit, the output signal of the first operational amplifier U1 is fed back to the non-inverting terminal of the sixth operational amplifier U6, and the output signal of the fifth operational amplifier U5 is fed back to the inverting terminal of the third operational amplifier U3. When the first connector P1 obtains a signal, the first connector P1 end signal is fed back to the inverting terminal of the sixth operational amplifier U6 and the non-inverting terminal of the third operational amplifier U3. When the voltage is in a jittering state during the power-on process and the amplitude is below the specified lower deviation of the working voltage, the sixth operational amplifier U6 outputs, and the output signal of the sixth operational amplifier U6 is fed back to the gate of the third MOS tube Q3 after passing through the first diode D1. The gate of the third MOS tube Q3 and the gate of the third MOS tube Q3 are fed back to the gate of the third MOS tube Q3. The voltage difference between the sources of the third MOS tube Q3 is higher than the conduction threshold, and the third MOS tube Q3 is turned on. When the voltage is in a jittering state during the power-on process and the amplitude is above the specified upper deviation of the working voltage, the third operational amplifier U3 outputs, and the output terminal signal of the third operational amplifier U3 is fed back to the gate of the third MOS tube Q3 after passing through the second diode D2, and the third MOS tube Q3 is turned on. When the third MOS tube Q3 is turned on, the hysteresis time of the silent state of the internal circuit of the chip is reset. The twenty-second resistor R22 is used to discharge the parasitic capacitance of the gate of the third MOS tube Q3, so that when the power-on voltage jitters violently during the initial power-on, the chip reset signal can be continuously fed back, so that the internal circuit of the chip is always in a silent state, and the unstable power-on voltage is prevented from causing erroneous operation, crash, and freeze of the chip.

[0028] See attached Figure 2In this embodiment, the power signal is looped to the ground terminal through the fifteenth resistor R15 and the sixteenth resistor R16. When the voltage changes from severe jitter to small jitter during the power-on process and the amplitude is within the operating voltage range of the chip, the sixth operational amplifier U6 is turned off, the third operational amplifier U3 is turned off, and the output signal of the sixth operational amplifier U6 is fed back to the gate of the first MOS tube Q1. The eighteenth resistor R18 is used to discharge the parasitic capacitance of the gate of the first MOS tube Q1. The output terminal signal of the third operational amplifier U3 is fed back to the gate of the second MOS tube Q2, the seventeenth resistor R17 is used to discharge the parasitic capacitance of the gate of the second MOS tube Q2, the signal of the sixteenth resistor R16 is connected to the ground loop via the source of the first MOS tube Q1, the drain of the first MOS tube Q1, and the twentieth resistor R20, the signal of the twentieth resistor R20 is connected to the ground loop via the source of the second MOS tube Q2, the drain of the second MOS tube Q2, and the twenty-first resistor R21, the signal of the twenty-first resistor R21 is connected to the ground loop via the nineteenth resistor R19, the potential of the first capacitor C1 is increased, and the output terminal signal of the third operational amplifier U3 is fed back to the gate of the second MOS tube Q2, when the power-on voltage shakes violently again and its amplitude is above the specified upper deviation of the working voltage, the output of the third operational amplifier U3, the gate of the second MOS tube Q2 and the second The voltage difference between the source of the MOS tube Q2 is higher than the conduction threshold, the second MOS tube Q2 is turned off, and the third MOS tube Q3 is turned on at the same time. The signal at the end of the first capacitor C1 is looped through the drain of the third MOS tube Q3 and the source of the third MOS tube Q3 to the ground terminal, and the signal at the output end of the sixth operational amplifier U6 is fed back to the gate of the first MOS tube Q1. When the power-on voltage fluctuates violently again and its amplitude is below the specified lower deviation of the working voltage, the sixth operational amplifier U6 outputs, and the voltage difference between the gate of the first MOS tube Q1 and the source of the first MOS tube Q1 is higher than the conduction threshold, the first MOS tube Q1 is turned off, and the third MOS tube Q3 is turned on at the same time, so that after the initial power-on and when its voltage fluctuates, its amplitude is within the working voltage range of the chip, and the internal circuit of the instantaneous hysteresis chip is in a silent state, thereby preventing the instantaneous voltage at the end of the feedback of the reset signal from fluctuating.

[0029] See attached Figure 2In this embodiment, the signal at the first capacitor C1 end is fed back to the inverting end of the fourth operational amplifier U4, the power signal is fed back to the grounding end loop through the twenty-sixth resistor R26 and the twenty-seventh resistor R27, the twenty-seventh resistor R27 end is fed back to the non-inverting end of the fourth operational amplifier U4, the signal amplitude at the twenty-seventh resistor R27 end can be changed by adjusting the resistance value of the twenty-seventh resistor R27, the signal amplitude at the twenty-seventh resistor R27 end is the signal amplitude of the silent state lag time of the internal circuit of the chip, when the potential of the first capacitor C1 rises to a certain amplitude, the fourth operational amplifier U4 is cut off, the power signal is fed back to the grounding end loop through the twenty-eighth resistor R28 and the twenty-ninth resistor R29 The grounding end loop, the signal at the end of the twenty-eighth resistor R28 passes through the emitter of the fourth transistor Q4, the base of the fourth transistor Q4, and the twenty-third resistor R23 to the grounding end loop, the emitter of the fourth transistor Q4 and the base of the fourth transistor Q4 are forward biased, the fourth transistor Q4 is turned on, the signal at the end of the twenty-eighth resistor R28 passes through the emitter of the fourth transistor Q4, the collector of the fourth transistor Q4, and the twenty-fourth resistor R24 ​​to the grounding end loop, the signal at the end of the twenty-fourth resistor R24 ​​is high level, when the fourth operational amplifier U4 outputs, the fourth transistor Q4 is turned off, the signal at the end of the twenty-fourth resistor R24 ​​is low level, and at the same time the output end of the fourth operational amplifier U4 The signal is synchronously fed back to the gate of the fifth MOS tube Q5. When the fourth operational amplifier U4 outputs, the voltage difference between the gate of the fifth MOS tube Q5 and the source of the fifth MOS tube Q5 is higher than the conduction threshold, and the fifth MOS tube Q5 is turned on. The power supply signal is looped to the ground terminal via the twenty-sixth resistor R26, the drain of the fifth MOS tube Q5, the source of the fifth MOS tube Q5, and the twenty-fifth resistor R25. The end of the twenty-fifth resistor R25 is high level. When the chip model is reset at a low level, the chip reset pin is connected to the control unit through the second connector P2. The signal at the end of the twenty-fourth resistor R24 ​​is fed back to the reset pin of the chip via the second connector P2. The chip is initially When the chip is powered on, when the chip reset pin obtains low-level feedback, the chip enters the reset state; when the chip reset pin obtains high-level feedback, the reset state is released; when the chip model is a high-level reset, the chip reset pin is connected to the control unit through the third connector P3, and the signal at the end of the twenty-fifth resistor R25 is fed back to the reset pin of the chip through the third connector P3. When the chip is initially powered on, when the chip reset pin obtains high-level feedback, the chip enters the reset state; when the chip reset pin obtains low-level feedback, the reset state is released; the connection is required according to the chip signal, so that the reset circuit can be compatible with the reset methods required by different models of chips.

[0030] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations within the meaning and scope of the equivalent elements of the claims be included in the invention. Any marking in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A chip power-on reset circuit, comprising a sampling unit and a control unit, characterized in that: The control unit is connected to the sampling unit, the sampling unit is used to collect the voltage when the chip is powered on and feed it back to the control unit, the control unit feeds back a chip reset signal based on the feedback of the sampling unit and the working voltage range of the chip, the control unit includes an eighth resistor, a ninth resistor, a tenth resistor, a twelfth resistor, a thirteenth resistor, a fourteenth resistor, a second operational amplifier, and a seventh operational amplifier, one end of the ninth resistor and one end of the thirteenth resistor are connected to the power supply, the other end of the ninth resistor is connected to one end of the tenth resistor and the in-phase end of the second operational amplifier, the inverting end of the second operational amplifier is connected to one end of the eighth resistor, the output end of the second operational amplifier is connected to the other end of the eighth resistor, the other end of the thirteenth resistor is connected to one end of the fourteenth resistor and the in-phase end of the seventh operational amplifier, the inverting end of the seventh operational amplifier is connected to one end of the twelfth resistor, the output end of the seventh operational amplifier is connected to the other end of the twelfth resistor, and the other end of the tenth resistor and the other end of the fourteenth resistor are connected to the ground.

2. The on-chip power-on reset circuit according to claim 1, characterized in that: The control unit also includes a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth resistor, a sixth resistor, a seventh resistor, an eleventh resistor, a first operational amplifier, and a fifth operational amplifier. One end of the first resistor is connected to the output end of the first operational amplifier, the in-phase end of the first operational amplifier is connected to one end of the second resistor and one end of the third resistor, the other end of the third resistor is connected to the output end of the second operational amplifier and one end of the fifth resistor, the inverting end of the first operational amplifier is connected to the other end of the first resistor and one end of the fourth resistor, the other end of the fourth resistor is connected to one end of the seventh resistor and the output end of the seventh operational amplifier, the other end of the seventh resistor is connected to the other end of the fifth resistor and the in-phase end of the fifth operational amplifier, the inverting end of the fifth operational amplifier is connected to one end of the sixth resistor and one end of the eleventh resistor, the other end of the sixth resistor is connected to the output end of the fifth operational amplifier, and the other ends of the second resistor and the eleventh resistor are connected to the ground.

3. The on-chip power-on reset circuit according to claim 2, characterized in that: The control unit also includes a third operational amplifier, a sixth operational amplifier, a third MOS tube, a first diode, a second diode, and a first connector. The third operational amplifier in-phase end is connected to the sixth operational amplifier inverting end and the first connector, the third operational amplifier inverting end is connected to the fifth operational amplifier output end, the third operational amplifier output end is connected to the second diode anode, the second diode cathode is connected to the first diode cathode and the third MOS tube gate, the first diode anode is connected to the sixth operational amplifier output end, the sixth operational amplifier in-phase end is connected to the first operational amplifier output end, and the third MOS tube source is connected to the ground end.

4. The on-chip power-on reset circuit according to claim 3, characterized in that: The control unit also includes a fifteenth resistor, a sixteenth resistor, a nineteenth resistor, a twentieth resistor, a twenty-first resistor, a first MOS tube, a second MOS tube, and a first capacitor. One end of the fifteenth resistor is connected to the power supply, the other end of the fifteenth resistor is connected to one end of the sixteenth resistor and the source of the first MOS tube, the gate of the first MOS tube is connected to the output end of the sixth operational amplifier, the drain of the first MOS tube is connected to one end of the twentieth resistor and the source of the second MOS tube, the gate of the second MOS tube is connected to the output end of the third operational amplifier, the drain of the second MOS tube is connected to one end of the nineteenth resistor and one end of the twenty-first resistor, the other end of the nineteenth resistor is connected to one end of the first capacitor, and the other ends of the sixteenth resistor, the twentieth resistor, the twenty-first resistor, and the first capacitor are connected to the ground.

5. The on-chip power-on reset circuit according to claim 3, characterized in that: The control unit also includes a twenty-third resistor, a twenty-fourth resistor, a twenty-sixth resistor, a twenty-seventh resistor, a twenty-eighth resistor, a twenty-ninth resistor, a fourth operational amplifier, a fourth transistor, and a second connector. One end of the twenty-sixth resistor and one end of the twenty-ninth resistor are connected to the power supply, the other end of the twenty-sixth resistor is connected to one end of the twenty-seventh resistor and the non-inverting end of the fourth operational amplifier, the inverting end of the fourth operational amplifier is connected to one end of the first capacitor and the drain of the third MOS tube, the output end of the fourth operational amplifier is connected to one end of the twenty-third resistor and the base of the fourth transistor, the collector of the fourth transistor is connected to one end of the twenty-fourth resistor and the second connector, the emitter of the fourth transistor is connected to one end of the twenty-eighth resistor and the other end of the twenty-ninth resistor, and the other end of the twenty-third resistor, the other end of the twenty-fourth resistor, the other end of the twenty-seventh resistor, and the other end of the twenty-eighth resistor are connected to the ground.

6. The on-chip power-on reset circuit according to claim 5, characterized in that: The control unit also includes a twenty-fifth resistor, a fifth MOS tube, and a third connector. One end of the twenty-fifth resistor is connected to the source of the fifth MOS tube and the third connector, the gate of the fifth MOS tube is connected to the base of the fourth transistor, the drain of the fifth MOS tube is connected to the emitter of the fourth transistor, and the other end of the twenty-fifth resistor is connected to the ground.

7. The on-chip power-on reset circuit according to claim 4, characterized in that: The control unit also includes a seventeenth resistor and an eighteenth resistor, one end of the eighteenth resistor is connected to the gate of the first MOS tube, one end of the seventeenth resistor is connected to the gate of the second MOS tube, and the other ends of the seventeenth resistor and the eighteenth resistor are connected to the ground end.

8. The on-chip power-on reset circuit according to claim 3, characterized in that: The control unit also includes a twenty-second resistor, one end of the twenty-second resistor is connected to the gate of the third MOS tube, and the other end of the twenty-second resistor is connected to the ground.

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