RapidIO line rate dynamic configuration method and switching network system

Abstract

The invention relates to the field of RapidIO switching networks, and provides a RapidIO line rate dynamic configuration method and a switching network system.The method comprises the steps that an RIO management node conducts link scanning on an FPGA node, and when the link state is poor, a RapidIO line rate dynamic configuration instruction is issued to the FPGA node; and after the FPGA node receives the instruction for dynamically configuring the RapidIO line rate, the RapidIO line rate dynamic configuration is started. According to the method, the link state is detected in real time through the RIO management node, when the link state is not good, the FPGA node is started to dynamically configure the RapidIO line rate in an instruction issuing mode, the problem that the link state of the FPGA node is not good is solved, normal communication of the RapidIO switching network can be effectively guaranteed, and software is easy to achieve.

Description

Technical Field

[0001] The present invention relates to the field of RapidIO switching networks, and in particular to a RapidIO line rate dynamic configuration method and a switching network system. Background Art

[0002] As a bus interconnection standard in the embedded field, RapidIO bus meets the needs of the rapid development of embedded systems with its high bandwidth, low latency, and high reliability. RapidIO bus is increasingly used for high-speed interconnection between chips and modules. Multiple chips and modules are interconnected with RapidIO switching chips through RapidIO bus and connected to RapidIO switching network.

[0003] At present, in the use of domestic RapidIO switching networks, there are cases where the link status is poor, causing the RapidIO nodes to go offline, causing abnormal interruption of communications, and further leading to system function failure.

[0004] The probability of the above poor link status will increase with the increase of RapidIO link line rate. Therefore, when the above problems occur, at the software level, the link quality is improved by reducing the RapidIO line rate of the node with poor link, thereby avoiding the problem of RapidIO node going offline and ensuring normal system communication.

[0005] In existing literature and patents, there is no method for dynamically adjusting the RapidIO line rate of an FPGA node. Summary of the invention

[0006] The present invention aims to provide a RapidIO line rate dynamic configuration method and a switching network system, which can solve the problem of poor FPGA node link status in a domestic RapidIO switching network without substantially increasing the system software cost. The method can effectively ensure normal system communication.

[0007] The present invention provides a RapidIO line rate dynamic configuration method, comprising:

[0008] The RIO management node scans the link of the FPGA node and sends a dynamic configuration RapidIO line rate instruction to the FPGA node when the link status is poor;

[0009] After receiving the instruction to dynamically configure the RapidIO line rate, the FPGA node starts the dynamic configuration of the RapidIO line rate.

[0010] In some embodiments, the RIO management node performs link scanning on the FPGA node by reading the value status of the RIO Port Error and Status CSR registers of the RapidIO switch chip port.

[0011] In some embodiments, after the RIO management node sends a dynamic configuration RapidIO line rate instruction to the FPGA node, it needs to determine whether an SPI response message from the FPGA node is received. If an SPI response message from the FPGA node is received, the RIO management node returns to the initial state and continues to scan the link of the FPGA node.

[0012] In some embodiments, the FPGA node receives a dynamic configuration RapidIO line rate instruction, and after the SPI control module parses and processes the configuration RapidIO line rate instruction, it outputs a RapidIO reconfiguration pulse signal RIO_recfg_pulse and a RapidIO reconfiguration line rate signal RIO_recfg_rate to the RIO line rate dynamic configuration module;

[0013] The RIO line rate dynamic configuration module receives the reconfiguration pulse signal RIO_recfg_pulse and the RapidIO reconfiguration line rate signal RIO_recfg_rate input from the SPI control module, and generates RapidIO line rate dynamic configuration related parameters under the control of the RapidIO reconfiguration line rate signal RIO_recfg_rate;

[0014] After the RapidIO line rate dynamic configuration related parameters are set, the RapidIO reconfiguration completion signal RIO_recfg_done is output to the SPI control module; after receiving the RapidIO reconfiguration completion signal RIO_recfg_done, the SPI control module feeds back SPI response information to the RIO management node.

[0015] In some embodiments, the FPGA node needs to monitor whether the RapidIO reconfiguration pulse signal RIO_recfg_pulse is valid, and if so, generates the RapidIO IP core dynamic configuration parameters according to the RapidIO reconfiguration line rate signal RIO_recfg_rate, and generates the RapidIO line rate dynamic configuration related parameters in the process of generating the RapidIO IP core dynamic configuration parameters according to the RapidIO reconfiguration line rate signal RIO_recfg_rate;

[0016] After the RapidIO line rate dynamic configuration related parameters are set, the Gt_reset signal in the RapidIO IP core dynamic configuration parameters is set to 1, and then the RapidIO reconfiguration completion signal RIO_recfg_done is generated through delay determination.

[0017] In some embodiments, the delay determination includes:

[0018] After setting the Gt_reset signal in the RapidIO IP core dynamic configuration parameters to 1, check whether the delay reaches the first threshold. If so, set the Gt_reset signal to 0.

[0019] After setting the Gt_reset signal to the 0 state, it is determined whether the delay reaches the second threshold. If so, a RapidIO reconfiguration completion signal RIO_recfg_done is generated.

[0020] The present invention also provides a RapidIO switching network system, including an FPGA node, a RapidIO switching chip and a RIO management node;

[0021] The FPGA node and the RIO management node are interconnected with the RapidIO switch chip via a RapidIO bus; the RIO management node is interconnected with the FPGA node via an SPI bus;

[0022] The RapidIO switching network adopts the above-mentioned RapidIO line rate dynamic configuration method to perform RapidIO line rate dynamic configuration.

[0023] In some embodiments, the FPGA node includes a RIO line rate dynamic configuration module and an SPI control module and a RapidIO IP core interconnected with the RIO line rate dynamic configuration module.

[0024] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are:

[0025] The present invention detects the link status in real time through the RIO management node. When the link status is not good, the FPGA node is started to dynamically configure the RapidIO line rate by issuing instructions, thereby solving the problem of poor link status of the FPGA node, effectively ensuring the normal communication of the RapidIO switching network, and the software implementation is simple. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 The following is a schematic diagram of the implementation principle of the RapidIO switching network in an embodiment of the present invention.

[0027] Figure 2The following is a flowchart of the RIO management node in an embodiment of the present invention.

[0028] Figure 3 The following is a schematic diagram of the RapidIO switching network and FPGA node implementation in an embodiment of the present invention.

[0029] Figure 4 for Figure 3 Figure 1 shows the workflow of the FPGA node. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0031] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] Example

[0033] See also Figure 1 A RapidIO switching network system in an embodiment of the present invention includes an FPGA node, a RapidIO switching chip, and a RIO management node;

[0034] The FPGA node is interconnected with the RapidIO switch chip via a RapidIO bus;

[0035] The RIO management node is interconnected with the RapidIO switch chip via a RapidIO bus;

[0036] The RIO management node is interconnected with the FPGA node via a SPI bus.

[0037] In some implementations, the FPGA node chip uses domestically produced K7, V7, Z7 and above FPGA devices;

[0038] In some implementations, the RapidIO switch chip uses CPS1848 or a corresponding domestically produced RapidIO switch device.

[0039] Based on the RapidIO switching network system implemented above, when performing the RapidIO line rate dynamic configuration method:

[0040] The RIO management node performs link scanning on the FPGA node, and when the link status is not good, sends a dynamic configuration RapidIO line rate instruction to the FPGA node;

[0041] After receiving the instruction for dynamically configuring the RapidIO line rate, the FPGA node starts the dynamic configuration of the RapidIO line rate.

[0042] See also Figure 2 In the RapidIO line rate dynamic configuration method, the working process of the RIO management node is as follows:

[0043] The link scan process of the RIO management node enters the initial state after the power-on reset is completed.

[0044] Then the RIO management node scans the link of the FPGA node by reading the RIO Port Error and StatusCSR register value status of the RapidIO switch chip port, and enters the link status determination process;

[0045] If the link status is not good, it will enter the SPI configuration command state to send the RapidIO line rate configuration command to the FPGA node through the SPI bus. After the RIO management node sends the dynamic configuration RapidIO line rate command to the FPGA node, it is necessary to determine whether the SPI response information from the FPGA node is received. If the SPI response information from the FPGA node is received, the RIO management node returns to the initial state and continues to scan the link of the FPGA node. If the link status is good, it will enter the RIO link configuration state and then the RIO scan end state.

[0046] See also Figure 3 In the RapidIO line rate dynamic configuration method, the working process of the FPGA node is as follows:

[0047] The FPGA node receives the RapidIO line rate configuration instruction issued by the RIO management node through the SPI bus, and after the SPI control module parses and processes the RapidIO line rate configuration instruction, outputs the RapidIO reconfiguration pulse signal RIO_recfg_pulse and the RapidIO reconfiguration line rate signal RIO_recfg_rate to the RIO line rate dynamic configuration module;

[0048] The RIO line rate dynamic configuration module receives the reconfiguration pulse signal RIO_recfg_pulse and the RapidIO reconfiguration line rate signal RIO_recfg_rate input from the SPI control module, and generates RapidIO line rate dynamic configuration related parameters under the control of the RapidIO reconfiguration line rate signal RIO_recfg_rate, including a sending queue depth parameter C_tx_depth, a receiving queue depth parameter C_rx_depth, a line rate mode parameter C_mode_xg, a receiving clock data recovery configuration parameter Rxcdr_cfg, a Cpll frequency division ratio parameter Cpll_fbdiv, an Rx end frequency division ratio parameter Rxout_div, a Tx end frequency division ratio parameter Txout_div, a receiving clock data recovery lock time parameter Rxcdr_lock_time, a clock multiplication coefficient parameter Clkfbout_mult_f, a clock frequency division coefficient parameter Clkout0_divde_f, a clock frequency division coefficient parameter Clkout1_divde_f, and a clock frequency division coefficient parameter Clkout2_divde_f;

[0049] After the above 12 RapidIO line rate dynamic configuration related parameters are set, the RapidIO reconfiguration completion signal RIO_recfg_done is output to the SPI control module; after receiving the RapidIO reconfiguration completion signal RIO_recfg_done, the SPI control module feeds back SPI response information to the RIO management node.

[0050] See also Figure 4 . The FPGA node line rate dynamic configuration process enters the initial state after the power-on reset is completed. The FPGA node needs to monitor whether the RapidIO reconfiguration pulse signal RIO_recfg_pulse is valid. If it is, the RapidIO IP core dynamic configuration parameters are generated according to the RapidIO reconfiguration line rate signal RIO_recfg_rate, and in the process of generating the RapidIO IP core dynamic configuration parameters according to the RapidIO reconfiguration line rate signal RIO_recfg_rate, the RapidIO line rate dynamic configuration related parameters are generated. After the RapidIO line rate dynamic configuration related parameters are set, the Gt_reset signal in the RapidIO IP core dynamic configuration parameters is set to 1, and then the RapidIO reconfiguration completion signal RIO_recfg_done is generated through delay judgment.

[0051] The delay determination includes:

[0052] After setting the Gt_reset signal in the RapidIO IP core dynamic configuration parameters to 1, check whether the delay reaches the first threshold. If so, set the Gt_reset signal to 0.

[0053] After setting the Gt_reset signal to the 0 state, it is determined whether the delay reaches the second threshold. If so, a RapidIO reconfiguration completion signal RIO_recfg_done is generated.

[0054] The first threshold is smaller than the second threshold. For example, the first threshold can be set to 1 ms and the second threshold can be set to 10 ms, which can be set according to actual needs.

[0055] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A RapidIO line rate dynamic configuration method, characterized in that: include: The RIO management node scans the link of the FPGA node and sends a dynamic configuration RapidIO line rate instruction to the FPGA node when the link status is poor; After receiving the instruction to dynamically configure the RapidIO line rate, the FPGA node starts the dynamic configuration of the RapidIO line rate.

2. The RapidIO line rate dynamic configuration method according to claim 1, characterized in that: The RIO management node performs link scan on the FPGA node by reading the RIO Port Error and Status CSR register values ​​of the RapidIO switch chip port.

3. The RapidIO line rate dynamic configuration method according to claim 1, characterized in that: After the RIO management node sends the dynamic configuration RapidIO line rate instruction to the FPGA node, it needs to determine whether it has received the SPI response information from the FPGA node. If it has received the SPI response information from the FPGA node, the RIO management node returns to the initial state and continues to scan the link of the FPGA node.

4. The RapidIO line rate dynamic configuration method according to claim 3, characterized in that: The FPGA node receives a dynamic configuration RapidIO line rate instruction, and after the SPI control module parses and processes the configuration RapidIO line rate instruction, outputs a RapidIO reconfiguration pulse signal RIO_recfg_pulse and a RapidIO reconfiguration line rate signal RIO_recfg_rate to the RIO line rate dynamic configuration module; The RIO line rate dynamic configuration module receives the reconfiguration pulse signal RIO_recfg_pulse and the RapidIO reconfiguration line rate signal RIO_recfg_rate input from the SPI control module, and generates RapidIO line rate dynamic configuration related parameters under the control of the RapidIO reconfiguration line rate signal RIO_recfg_rate; After the RapidIO line rate dynamic configuration related parameters are set, the RapidIO reconfiguration completion signal RIO_recfg_done is output to the SPI control module; after receiving the RapidIO reconfiguration completion signal RIO_recfg_done, the SPI control module feeds back SPI response information to the RIO management node.

5. The RapidIO line rate dynamic configuration method according to claim 4, characterized in that: The FPGA node needs to monitor whether the RapidIO reconfiguration pulse signal RIO_recfg_pulse is valid. If so, the RapidIO IP core dynamic configuration parameters are generated according to the RapidIO reconfiguration line rate signal RIO_recfg_rate, and in the process of generating the RapidIO IP core dynamic configuration parameters according to the RapidIO reconfiguration line rate signal RIO_recfg_rate, the RapidIO line rate dynamic configuration related parameters are generated; After the RapidIO line rate dynamic configuration related parameters are set, the Gt_reset signal in the RapidIO IP core dynamic configuration parameters is set to 1, and then the RapidIO reconfiguration completion signal RIO_recfg_done is generated through delay determination.

6. The RapidIO line rate dynamic configuration method according to claim 5, characterized in that: The delay determination includes: After setting the Gt_reset signal in the RapidIO IP core dynamic configuration parameters to 1, check whether the delay reaches the first threshold. If so, set the Gt_reset signal to 0. After setting the Gt_reset signal to the 0 state, it is determined whether the delay reaches the second threshold. If so, a RapidIO reconfiguration completion signal RIO_recfg_done is generated.

7. A RapidIO switching network system, characterized in that: Includes FPGA nodes, RapidIO switch chips, and RIO management nodes; The FPGA node and the RIO management node are interconnected with the RapidIO switch chip via a RapidIO bus; the RIO management node is interconnected with the FPGA node via an SPI bus; The RapidIO switching network system adopts the RapidIO line rate dynamic configuration method according to any one of claims 1 to 6 to perform RapidIO line rate dynamic configuration.

8. The RapidIO switching network system according to claim 7, characterized in that: The FPGA node includes a RIO line rate dynamic configuration module and an SPI control module and a RapidIO IPcore interconnected with the RIO line rate dynamic configuration module.

Images