RapidIO line rate adaptive matching method and switching network system

Abstract

The invention provides a RapidIO line rate adaptive matching method and a switching network system. The method comprises the following steps: detecting a link establishment signal Linkinit; and when the link building signal Linkinit is invalid, line rate matching between the FPGA node and the RapidIO exchange chip is automatically completed based on line rate traversal. Through a line rate traversal matching mode of the FPGA node and the RapidIO exchange chip, the problem that in a traditional design, multiple different RapidIO line rates of the RapidIO port of the exchange chip are matched by compiling multiple FPGA software versions is solved, the system development integration efficiency is improved, and software is easy to implement.

Description

Technical Field

[0001] The present invention relates to a RapidIO switching network of an integrated electronic information system, and in particular to a RapidIO line rate adaptive matching method and a switching network system. Background Art

[0002] As a bus interconnection standard in the embedded field, RapidIO bus meets the needs of the rapid development of embedded systems with its high bandwidth, low latency, and high reliability. RapidIO bus is increasingly used for high-speed interconnection between chips and modules. Multiple chips and modules are interconnected with RapidIO switching chips through RapidIO bus and connected to RapidIO switching network.

[0003] FPGA chips are programmable, highly flexible, have short development cycles, and have strong parallel processing capabilities. They are increasingly used in integrated electronic information system hardware platforms. In an integrated electronic information system with a large RapidIO switching network, dozens or even hundreds of FPGA chips may be used. There may be multiple RapidIO line rates (such as 6.125Gbps, 5Gbps, 3.125Gbps, 2.5Gbps, and 1.25Gbps, up to 5 types) between different subsystems and between different functions within a subsystem. Therefore, to adapt to RapidIO switching chip ports with different line rates, it is necessary to develop FPGA software programs for different RapidIO line rates.

[0004] In the early stage of system joint testing, many functions were not fully determined, which inevitably led to frequent modifications of FPGA software. For an integrated electronic information system with a large RapidIO switching network, each time the program is modified to involve RapidIO-related logic, multiple different FPGA software versions must be compiled for the various different RapidIO line rates. This will introduce the problem of multiple software version management on the one hand, and increase the workload of FPGA software adaptation on the other hand, reducing the efficiency of system software development and integration. Summary of the invention

[0005] The present invention aims to provide a RapidIO line rate adaptive matching method and a switching network system, which solves the problem that multiple FPGA software versions with different line rates need to be compiled for adaptation due to mismatch of RapidIO port line rates in a RapidIO switching network without substantially increasing the system software cost.

[0006] The present invention provides a RapidIO line rate adaptive matching method, comprising:

[0007] Detect link establishment signal Link_init;

[0008] When the link establishment signal Link_init is invalid, line rate matching between the FPGA node and the RapidIO switch chip is automatically completed based on line rate traversal.

[0009] In some embodiments, the detecting the link establishment signal Link_init includes:

[0010] Whether the link establishment signal Link_init is valid is determined by detecting the value of the link establishment signal Link_init;

[0011] in:

[0012] When the value of the link building signal Link_init is 0, the link building signal Link_init is invalid;

[0013] When the value of the link establishment signal Link_init is 1, the link establishment signal Link_init is valid.

[0014] In some embodiments, the line rate traversal is a line rate traversal from low to high.

[0015] In some embodiments, line rate traversal is implemented based on the line rate identification.

[0016] In some embodiments, implementing line rate traversal based on the line rate identifier includes:

[0017] S1, setting a plurality of line rate identifiers, each of which corresponds to a line rate configuration parameter;

[0018] S2, with a line rate identifier, sets the corresponding line rate configuration parameters;

[0019] S3, determine again whether the link establishment signal Link_init is valid:

[0020] If the link establishment signal Link_init is valid, it means that the line rate matching is successful and the state is turned to the end state;

[0021] If the link establishment signal Link_init is invalid, the process returns to step S2 with the next line rate identifier.

[0022] In some embodiments, after setting the corresponding line rate configuration parameters in executing step S2, the Gt_reset reset signal is set to 1, and then it is determined whether the delay T1 is reached. If the delay T1 has been reached, the Gt_reset reset signal is set to 0, and then it is determined whether the delay T2 is reached. If the delay T2 has been reached, step S2 is executed to return and determine again whether the link establishment signal Link_init is valid.

[0023] The present invention also provides a RapidIO switching network system, including an FPGA node and a RapidIO switching chip;

[0024] The FPGA node is interconnected with the RapidIO switching chip through the RapidIO bus and accesses the RapidIO switching network;

[0025] The FPGA node and the RapidIO switching chip use the above RapidIO line rate adaptive matching method to perform line rate matching.

[0026] In some embodiments, the FPGA node has a built-in RapidIO IP core and a RapidIO line rate adaptive matching module;

[0027] The RapidIO line rate adaptive matching module is used to execute the above RapidIO line rate adaptive matching method.

[0028] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are:

[0029] The present invention solves the problem of relying on compiling multiple FPGA software versions to match multiple different RapidIO line rates of the RapidIO port of the switching chip in the traditional design through the line rate traversal matching mode of the FPGA node and the RapidIO switching chip, thereby improving the system development integration efficiency and simplifying the software implementation. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 The following is a schematic diagram of the implementation principle of the RapidIO switching network system in an embodiment of the present invention.

[0031] Figure 2 The following is a schematic diagram of the RapidIO switching network and FPGA node implementation in an embodiment of the present invention.

[0032] Figure 3 FIG. 4 is a detailed flow chart of a RapidIO line rate adaptive matching method in an embodiment of the present invention. DETAILED DESCRIPTION

[0033] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0034] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0035] Example

[0036] See also Figure 1 This embodiment proposes a RapidIO switching network system, including an FPGA node and a RapidIO switching chip; the FPGA node is interconnected with the RapidIO switching chip through a RapidIO bus and connected to the RapidIO switching network.

[0037] In some embodiments, the FPGA node chip uses domestically produced K7, V7, Z7 and above FPGA devices;

[0038] In some embodiments, the RapidIO switch chip uses CPS1848 or a corresponding domestically produced RapidIO switch device.

[0039] For the above-mentioned RapidIO switching network system, this embodiment provides a RapidIO line rate adaptive matching method, including:

[0040] Detect link establishment signal Link_init;

[0041] When the link establishment signal Link_init is invalid, the line rate matching between the FPGA node and the RapidIO switch chip is automatically completed based on the line rate traversal.

[0042] See also Figure 2, the FPGA node has built-in RapidIO IP core and RapidIO line rate adaptive matching module. The RapidIO IP core works in the line rate 1.25Gbps mode by default, and outputs the link establishment signal Link_init to the RapidIO line rate adaptive matching module. The RapidIO line rate adaptive matching module determines whether the link establishment signal Link_init is valid by detecting the value of the link establishment signal Link_init. When the link establishment signal Link_init is invalid (that is, the value is 0), the RapidIO line rate is dynamically configured by traversing the line rate from low to high until the link establishment signal Link_init is valid (that is, the value is 1); when the link establishment signal Link_init is valid, the RapidIO line rate adaptive matching module outputs the setting parameters Cdr_cfg_para and clk_cfg_para, and outputs the Gt_reset reset signal to the RapidIO IP core to complete the RapidIO line rate adaptive matching.

[0043] In some embodiments, line rate traversal is implemented based on the line rate identifier, as follows:

[0044] S1, setting a plurality of line rate identifiers, each of which corresponds to a line rate configuration parameter;

[0045] S2, with a line rate identifier, sets the corresponding line rate configuration parameters;

[0046] S3, determine again whether the link establishment signal Link_init is valid:

[0047] If the link establishment signal Link_init is valid, it means that the line rate matching is successful and the state is turned to the end state;

[0048] If the link establishment signal Link_init is invalid, the process returns to step S2 with the next line rate identifier.

[0049] In some embodiments, after setting the corresponding line rate configuration parameters in executing step S2, the Gt_reset reset signal is set to 1, and then it is determined whether the delay T1 is reached. If the delay T1 has been reached, the Gt_reset reset signal is set to 0, and then it is determined whether the delay T2 is reached. If the delay T2 has been reached, step S2 is executed to return and determine again whether the link establishment signal Link_init is valid.

[0050] See also Figure 3 A specific example of implementing line rate traversal based on line rate identification is:

[0051] The RapidIO line rate adaptive matching module enters the initial state after the power-on reset is completed, and then sets the line rate flag to the 3'b001 state;

[0052] When the line rate identifier is 3'b001, set the line rate configuration parameters to 2.5Gbps; then set the line rate identifier to 3'b010, set the Gt_reset reset signal to 1, and then determine whether the delay T1 is reached. If the delay T1 has been reached, set the Gt_reset reset signal to 0, and then determine whether the delay T2 is reached. If the delay T2 has been reached, return to determine whether the link establishment signal Link_init is valid again. When the link establishment signal Link_init is valid, it means that the line rate is matched successfully and enters the end state. Otherwise, configure the RapidIO line rate according to the line rate identifier 3'b010.

[0053] When the line rate identifier is 3'b010, set the line rate configuration parameters to 3.125Gbps; then set the line rate identifier to 3'b011, set the Gt_reset reset signal to 1, and then determine whether the delay T1 is reached. If the delay T1 has been reached, set the Gt_reset reset signal to 0, and then determine whether the delay T2 is reached. If the delay T2 has been reached, return to determine whether the link establishment signal Link_init is valid again. When the link establishment signal Link_init is valid, it means that the line rate matching is successful and enters the end state. Otherwise, configure the RapidIO line rate according to the line rate identifier 3'b011.

[0054] When the line rate identifier is 3'b011, set the line rate configuration parameters to 5 Gbps; then set the line rate identifier to 3'b100, set the Gt_reset reset signal to 1, and then determine whether the delay T1 is reached. If the delay T1 has been reached, set the Gt_reset reset signal to 0, and then determine whether the delay T2 is reached. If the delay T2 has been reached, return to determine whether the link establishment signal Link_init is valid again. When the link establishment signal Link_init is valid, it means that the line rate matching is successful and enters the end state. Otherwise, configure the RapidIO line rate according to the line rate identifier 3'b100.

[0055] When the line rate identifier is 3'b011, set the line rate configuration parameters to 6.25Gbps; then set the line rate identifier to 3'b101, set the Gt_reset reset signal to 1, and then determine whether the delay T1 is reached. If the delay T1 has been reached, set the Gt_reset reset signal to 0, and then determine whether the delay T2 is reached. If the delay T2 has been reached, return to determine whether the link establishment signal Link_init is valid again. When the link establishment signal Link_init is valid, it means that the line rate is matched successfully and enters the end state. Otherwise, configure the RapidIO line rate according to the line rate identifier 3'b101.

[0056] By analogy, the RapidIO line rate is dynamically configured by traversing the line rate from low to high based on the line rate identifier. It should be noted that the line rate identifier, the corresponding line rate and the corresponding step size can be set as needed. At the same time, the delay T1 and the delay T2 can also be set according to actual needs. Usually T1<T2, for example, T1=1ms, T2=10ms.

[0057] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A RapidIO line rate adaptive matching method, characterized in that: include: Detect link establishment signal Link_init; When the link establishment signal Link_init is invalid, line rate matching between the FPGA node and the RapidIO switch chip is automatically completed based on line rate traversal.

2. The RapidIO line rate adaptive matching method according to claim 1, characterized in that: The detecting link establishment signal Link_init comprises: Whether the link establishment signal Link_init is valid is determined by detecting the value of the link establishment signal Link_init; in: When the value of the link building signal Link_init is 0, the link building signal Link_init is invalid; When the value of the link establishment signal Link_init is 1, the link establishment signal Link_init is valid.

3. The RapidIO line rate adaptive matching method according to claim 1, characterized in that: The line rate traversal is a traversal from low to high line rate.

4. The RapidIO line rate adaptive matching method according to claim 1, characterized in that: Line rate traversal is implemented based on line rate identification.

5. The RapidIO line rate adaptive matching method according to claim 4, characterized in that: The implementing line rate traversal based on the line rate identifier includes: S1, setting a plurality of line rate identifiers, each of which corresponds to a line rate configuration parameter; S2, with a line rate identifier, sets the corresponding line rate configuration parameters; S3, determine again whether the link establishment signal Link_init is valid: If the link establishment signal Link_init is valid, it means that the line rate matching is successful and the state is turned to the end state; If the link establishment signal Link_init is invalid, the process returns to step S2 with the next line rate identifier.

6. The RapidIO line rate adaptive matching method according to claim 5, characterized in that: After setting the corresponding line rate configuration parameters in step S2, set the Gt_reset reset signal to 1, and then determine whether the delay T1 is reached. If the delay T1 has been reached, set the Gt_reset reset signal to 0, and then determine whether the delay T2 is reached. If the delay T2 has been reached, execute step S2 and return to determine again whether the link establishment signal Link_init is valid.

7. A RapidIO switching network system, characterized in that: Includes FPGA nodes and RapidIO switch chips; The FPGA node is interconnected with the RapidIO switching chip through the RapidIO bus and accesses the RapidIO switching network; The FPGA node and the RapidIO switching chip perform line rate matching using the RapidIO line rate adaptive matching method as described in any one of claims 1 to 6.

8. The RapidIO switching network system according to claim 7, characterized in that: The FPGA node has a built-in RapidIO IP core and a RapidIO line rate adaptive matching module; The RapidIO line rate adaptive matching module is used to execute the RapidIO line rate adaptive matching method according to any one of claims 1 to 6.

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