Software implementation method for simulating video signal character superposition

Abstract

The invention relates to the technical field of image transmission, and particularly discloses a software implementation method for character superposition of analog video signals, which comprises the following steps of: S1, generating a comparison voltage by a digital-to-analog converter, and inputting the comparison voltage into an inverted input port of a comparator for comparison; s2, the storage access controller transmits the synchronization time point to a slave timer, and a master timer triggers graphic conversion and generates a corresponding image storage memory; s3, the storage access controller carries the data in the image storage memory to the two specified GPIOs; and S4, jointly controlling an analog switch to generate an analog video signal after character superposition under the assistance of a digital-to-analog converter, and finally outputting the analog video signal to an analog video output port. According to the method and the device, the characters are superposed in the CVBS video signals, the CVBS synchronous signals are accurately tracked, the character dot matrix data of the OSD are quickly stretched, analog signal output is operated through GPIO, the integration level is high, the cost is low, the flexibility is higher, and the data generation and transmission logic of the analog video signals with the superposed characters is optimized.

Description

Technical Field

[0001] The invention relates to the technical field of image transmission, and in particular to a software implementation method for simulating character superposition of video signals. Background Art

[0002] With the development of electronic display technology, the character overlay (OSD, On-Screen Display) function is widely used in consumer electronics, industrial control, security monitoring and unmanned systems. For example, devices such as TVs, surveillance cameras, and drone displays often use OSD technology to overlay timestamps, status information, icons, and menu content on the video screen. This information overlay plays an important role in the interactivity, monitoring, and visualization of the device.

[0003] At present, the character overlay function is realized by using peripheral hardware chips in most cases. Traditional character overlay functions mostly rely on dedicated character overlay chips (OSD control chips) to achieve. The typical solution is to draw the character or icon information through an independent OSD chip and combine it with the video signal into a complete output picture.

[0004] After searching, the Chinese invention patent application with patent application number CN202410078096.7 discloses a method, device, computer equipment and storage medium for character overlay of video images, wherein the method for character overlay of video images includes: when the first FPGA chip receives the video stream to be overlaid with characters, the video synchronization signal corresponding to the video stream is sent to the second FPGA chip; the second FPGA chip is configured with peripheral storage resources; based on the second FPGA chip, the OSD identification information corresponding to the video synchronization signal is obtained; further, the OSD identification information is returned to the first FPGA chip, and the video stream is overlaid with characters according to the OSD identification information. Through this application, the problem that the FPGA logic resources where the OSD module is located are tight and the video OSD overlay function cannot be realized in the multi-FPGA system is solved, and the character overlay based on the multi-FPGA system is realized, and the overall resource utilization of the system is improved.

[0005] For another example, a Chinese invention patent with patent application number CN202111596064.9 discloses an OSD screen generating device, chip, display device and method, wherein the device includes an OSD memory for storing a first OSD resource; a layer module for obtaining the first OSD resource from the OSD memory, and processing the first OSD resource to generate a first layer; other memories for storing second OSD resources; a graphics controller for obtaining the second OSD resource from other memories, and processing the second OSD resource to generate a second layer; a first mixer for mixing the first layer and the second layer to generate an OSD screen; wherein the second OSD resource is a resource corresponding to a screen containing special attributes in the OSD screen. The second OSD resource can be stored in other memories in the above manner, and the first OSD resource and the second OSD resource can be processed by the resource processing method of the invention to output the OSD screen, thereby solving the problem of large OSD resource space demand and reducing the chip area.

[0006] Although dedicated OSD chips have advantages in performance, their use also brings the following limitations:

[0007] 1. High hardware cost: It is necessary to purchase and integrate special chips, which increases the bill of materials (BOM).

[0008] 2. Increased circuit complexity: It is necessary to handle communication and synchronization between multiple chips, which makes the design complex.

[0009] 3. Lack of flexibility: The hardware-customized OSD function has poor scalability and is not suitable for scenarios where requirements change frequently.

[0010] 4. Power consumption issue: Multi-chip design will increase the overall system power consumption, which is not conducive to the application of low-power scenario equipment. Summary of the invention

[0011] The technical problem to be solved by the present invention is to provide a software implementation method for simulating video signal character overlay in response to the defects existing in the above-mentioned prior art, so as to solve the problems of high hardware cost, increased circuit complexity, insufficient flexibility and high power consumption existing in the existing method for implementing video signal character overlay.

[0012] In order to solve the above technical problems, the technical solution of the present invention is:

[0013] A software implementation method for simulating video signal character overlay, comprising the following steps:

[0014] Step S1, the analog video waveform is transmitted to the analog switch and the in-phase input port of the comparator, and at the same time, the digital-to-analog converter generates a specified comparison voltage which is input to the inverting input port of the comparator for comparison, and the comparison result is output to the main timer, which captures a synchronization time point;

[0015] Step S2, using the storage access controller to transfer the synchronization time point and its configuration captured by the master timer to the slave timer, and at the same time, the master timer triggers the image conversion function algorithm corresponding to the image operation instruction issued by the instruction source according to the format of the line signal and the field signal to perform the graphic conversion at this synchronization time point, and generate the corresponding image storage memory;

[0016] Step S3, the slave timer periodically triggers the storage access controller to move the data of the image storage memory to the two designated GPIOs according to the configuration transmitted by the master timer, thereby generating two corresponding signal pulses;

[0017] Step S4, with the assistance of the digital-to-analog converter, jointly control the analog switch to generate an analog video signal after character superposition, and finally output it to the analog video output port.

[0018] Preferably, the master timer interrupt is used to parse the synchronization signal and execute the row synchronization signal callback; the slave timer interrupt is used for delay and signal counting; the comparator is a voltage comparator, which is used to set the comparison threshold of the voltage comparator in real time; the analog-to-digital converter is used to sample the analog signal and convert it into a digital quantity, and the sampling time is required to be less than 2uS; the digital-to-analog converter is used to output the digital-to-analog converter module pin of the black level; the storage access controller is used for data transmission and handling.

[0019] Preferably, the GPIO generates two built-in image cache memory data. When a line synchronization signal appears, the last cached data is converted into a specified format in the interrupt of the main timer, and then the overlay cache data of the next line is set through a preset callback function. This data is ultimately used to store the control data sent by the access controller.

[0020] Preferably, the comparator detects the format, line and field synchronization signals of CVBS and outputs a hardware-level line synchronization timing; the line and field synchronization signals of CVBS are both pulses with a negative voltage lower than 0.

[0021] Preferably, the negative pulse width of the horizontal synchronization signal is 4.7uS.

[0022] Preferably, the negative pulse of the field synchronization:

[0023] Balanced pulse width: 2.35uS narrow pulse, denoted by VA later;

[0024] Vertical sync pulse width: 27uS wide pulse, denoted by VB later;

[0025] Among them, NTSC field synchronization 1: entire line period + VA*6 + VB*6 + VA*6 + H*13;

[0026] NTSC field synchronization 2: half line period + VA*6 + VB*6 + VA*6 + H*13;

[0027] PAL field synchronization 1: half line period + VA*5 + VB*5 + VA*5 + H*17;

[0028] PAL field sync 2: entire line period + VA*5 + VB*5 + VA*5 + H*17.

[0029] Preferably, there is sufficient time in the field equalization pulse (VA) and the field vertical synchronization pulse (VB) to perform ADC sampling of the voltage value of the synchronization signal. When the overflow interrupt of the main timer determines that it is a VA or VB signal:

[0030] VA pulse, the value read from ADC is the value of 0IRE;

[0031] VB pulse, the value read from ADC is -40IRE for NTSC and -43IRE for PAL;

[0032] Regardless of whether it is NTSC or PAL, calculating (VA-VB) / 4 will give an accurate voltage comparison value;

[0033] Distinguish the format: NTSC: 720*480; PAL: 720*576. An image is scanned in odd and even fields. The number of lines between any two fields can be calculated to distinguish the format. Take the median value. If it is less than 264 lines, it is NTSC format, and if it is greater than 264 lines, it is PAL format.

[0034] Preferably, when a row synchronization signal is detected in a comparison interrupt, the software is set to mask the interrupt and update the overflow time of the main timer until the next overflow of the main timer occurs, and the interrupt is restored to prevent interference signals that may occur during the period from destroying the synchronization time.

[0035] By adopting the above technical solution, the present invention provides a software implementation method for simulating video signal character overlay, which has the following advantages by realizing the OSD function based on a general embedded chip:

[0036] 1. Cost optimization: cancel the dedicated OSD chip, reduce material cost and design complexity; high integration and low cost, a single device can not only save the cost of traditional hardware OSD chip, but also free up the layout space of OSD chip;

[0037] 2. Circuit simplification: reduce the interface communication design between chips to make the system simpler and more reliable;

[0038] 3. Enhanced flexibility: OSD function is realized through software algorithm, character style and display content can be adjusted according to needs, which is more flexible and compatible with more different types of analog video signal cameras;

[0039] 4. Low power consumption design: Integrate OSD function inside MCU to reduce overall power consumption; can effectively speed up the development of data compatible with different types of superimposed fonts, and optimize the data generation and transmission logic of analog video signals of superimposed characters. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 The present invention is a flow chart of a software implementation method for simulating video signal character superposition. DETAILED DESCRIPTION

[0041] The specific embodiments of the present invention are further described below in conjunction with the accompanying drawings. It should be noted that the description of these embodiments is used to help understand the present invention, but does not constitute a limitation of the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0042] In the description of the present invention, it is to be understood that the terms “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “up”, “down”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, “clockwise”, “counterclockwise”, “axial”, “radial”, “circumferential”, etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0043] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0044] like Figure 1 As shown, in a flowchart of a software implementation method for superimposing characters of a simulated video signal of the present invention, the following parts are included:

[0045] 1. Software method for superimposing characters in CVBS video signals;

[0046] 2. Methods for accurately tracking CVBS synchronization signals;

[0047] 3. A method for fast stretching of character dot matrix data suitable for OSD;

[0048] 4. Method of analog signal output through GPIO operation;

[0049] First, the software solution for superimposing characters in CVBS video signals requires two master and slave timers (TIM), a voltage comparator (CMP), an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), and a memory access controller (DMA). The master timer interrupt is used to parse the synchronization signal and execute the line synchronization callback; the slave timer interrupt is used for delay and signal counting; the voltage comparator is used to set the comparison threshold of the voltage comparator in real time, which requires: the comparison level is programmable; the input falling edge can trigger a reset mode of a slave timer by hardware; both the falling edge and the rising edge can generate interrupts, and the interrupt preemption priority is the highest; the analog-to-digital converter is used to sample the analog signal and convert it into a digital quantity, and the sampling time is required to be less than 2uS; the digital-to-analog converter is used to output the DAC module pin of the black level. If there is no such hardware, it can be left blank (returned directly), and the memory access controller is used for data transmission and handling. Through the above functional modules, the function of superimposing characters in the analog video signal can be realized, and finally the signal that has been superimposed with characters is generated into an analog video waveform through the analog switch.

[0050] Secondly, if a 47uF DC blocking capacitor is retained when outputting to the image transmission end, the superimposed characters are prone to jitter in certain scenarios. Because the output impedance of a camera is 75 ohms, the synchronization signal will be affected by the input impedance of the image transmission, which is similar to the presence of a DC blocking capacitor at the input end. The method to accurately track the CVBS synchronization signal is to optimize the configuration of the voltage comparator by software so that both edges can generate interrupts, and the interrupt preemption priority is the highest (0). At the same time, the falling edge can be captured by a slave timer. The overflow or trigger comparison time of the slave timer is fixed between 9.3uS and 9.4uS (a slight adjustment of this time can correct the time error of a pixel clock). When the overflow or trigger comparison occurs, a hardware behavior that triggers DMA transmission can be generated. The overflow time of the main timer is variable, and an interrupt is generated when it overflows. The interrupt preemption priority is not higher than the interrupt preemption priority of the comparator. At the same time, the signal detection when each line of data is sent is shielded. When a line synchronization signal is detected in the comparison interrupt, the software sets the interrupt to be shielded and the overflow time of the main timer is updated until the next overflow of the main timer occurs. This interrupt is restored to prevent interference signals that may occur during the period from destroying the synchronization time. Therefore, the CVBS synchronization signal can be accurately tracked.

[0051] Third, a method for fast stretching of character dot matrix data suitable for OSD: using designated host computer software to implement character original font data of different communication protocols, the supported communication protocols include common protocols of flight control systems such as Betaflight and iNav. In addition, the present invention also refers to the instruction parsing logic of the MAX7645 chip, designs and optimizes an efficient instruction parsing algorithm to improve character rendering efficiency. This method can quickly and accurately acquire and parse character data between different protocols, and efficiently realize the scaling and display of character dot matrix, providing more flexible and real-time display capabilities for the OSD system.

[0052] Fourth, the method of operating analog signal output through GPIO: two general GPIOs are used to generate two built-in image cache memory data. When the line synchronization signal appears, the last cached data is converted into the specified format in the interrupt of the main timer, and then the overlay cache data of the next row is set through the preset callback function. This data is finally used for the control data sent by DMA, with a total length of 720+32 bytes, which conforms to the MAX7456 format for a whole row of overlay cache data, a total of 180 bytes, each 2 bits represents 1 pixel, and a total of 720 pixels can be represented.

[0053] like Figure 1 As shown, the analog video waveform is transmitted to the analog switch and the in-phase input port of the MCU chip comparator, and at the same time, the DAC generates a specified comparison voltage and inputs it to the inverting input port of the comparator for comparison. The result of the comparison is output to the main timer, which captures a synchronous time point, and then uses DMA to pass the time point captured by the main timer and its configuration to the slave timer. At the same time, the main timer triggers the image conversion function algorithm corresponding to the image operation instruction issued by the instruction source according to the format of the line signal and the field signal to perform the graphic conversion at this synchronous time point and generate the corresponding image storage memory. Then, the slave timer will periodically trigger DMA according to the configuration transmitted by the master timer to move the data of the image storage memory to the specified two GPIOs, thereby generating two corresponding signal pulses, and jointly controlling the analog switch with the assistance of the DAC to generate the analog video signal after character superposition, and finally output it to the analog video output port; this is a complete process of analog video character superposition.

[0054] By setting the comparator inside the chip to detect the CVBS format, line and field synchronization signals, a hardware-level line synchronization timing is output.

[0055] Key signals:

[0056] The sync signals of CVBS lines and fields are both pulses with negative voltages below 0. When analyzing the signals, we only need to pay attention to the width of the negative voltage, where:

[0057] Negative pulse width of line synchronization: 4.7uS. The signal in this interval must be the line synchronization signal. When this signal appears, the signal transmission of image mixing can begin, which is indicated by H later.

[0058] Negative pulse of field synchronization:

[0059] -Balanced pulse width: 2.35uS narrow pulse, denoted by VA;

[0060] -Vertical sync pulse width: 27uS wide pulse, denoted by VB later;

[0061] -NTSC field synchronization 1: full line period + VA*6 + VB*6 + VA*6 + H*13

[0062] -NTSC field sync 2: half line period + VA*6 + VB*6 + VA*6 + H*13

[0063] -PAL field sync 1: half line period + VA*5 + VB*5 + VA*5 + H*17

[0064] -PAL field sync 2: full line period + VA*5 + VB*5 + VA*5 + H*17

[0065] Hardware feature requirements:

[0066] 1. Voltage comparator, DAC

[0067] - Voltage comparator with programmable comparison level;

[0068] -The falling edge of the comparator input can hardware trigger a capture of the slave timer;

[0069] - Both the falling and rising edges of the comparator can generate interrupts;

[0070] 2. From the timer

[0071] -Can capture the falling edge of voltage comparison output;

[0072] - Hardware-triggered DMA transfer can be set to start at a certain time point after the falling edge of the captured voltage comparison output, with a time better than 37nS;

[0073] - At least two timers;

[0074] 3.DMA

[0075] - The optional timer is used as the trigger source, and the hardware automatically starts a data transfer to the peripheral device;

[0076] 4.ADC

[0077] -Can work simultaneously with comparator;

[0078] 5. Kernel

[0079] - The interrupt priority can be set;

[0080] -Can only mask interrupts below the specified priority level;

[0081] -It is best to have a bit zone;

[0082] Synchronous implementation logic:

[0083] Everything starts from the falling edge of a negative pulse. Let's first emphasize a few key time points, all of which start from the falling edge of the negative pulse:

[0084] 2.35uS: VA rising edge time point,

[0085] 4.7uS:H rising edge time point,

[0086] 5.3uS:H color synchronization time point,

[0087] 9.4uS:H black level end time point;

[0088] Configure the voltage comparator to generate an interrupt on both edges, with the interrupt preemption priority set to the highest (0), and the falling edge can be captured by a slave timer;

[0089] Configure the overflow or trigger comparison time of the slave timer to be fixed between 9.3uS and 9.4uS (fine-tuning this time can correct the time error of a pixel clock). When overflow or trigger comparison occurs, a hardware behavior that triggers DMA transfer can be generated;

[0090] The overflow time of the configured main timer is variable, an interrupt is generated when it overflows, and the interrupt preemption priority is not higher than the interrupt preemption priority of the comparator.

[0091] There are two interrupt lines in total, and the preemption priorities from high to low are: edge interrupt of voltage comparator (0), overflow interrupt of main timer. The main things done by these two interrupts are: 1. Edge interrupt of voltage comparator (0): when the interrupt is low level (the counter value of slave timer is captured at this time), the software resets and starts the counter of main timer; when the interrupt is high level, read the counter of main timer, according to the time of negative pulse, if the recording time is about 2.35uS, it is VA signal, if the time is about 4.7uS, it is H signal and immediately set to prepare for a DMA transfer; 2. Overflow interrupt of main timer (1): according to the signal type given by edge interrupt of voltage comparator (0), further parse out the format, field, line number, and perform image conversion action;

[0092] Signal amplitude and sampling time:

[0093] There is enough time in the field equalization pulse (VA) and the field vertical synchronization pulse (VB) to sample the voltage value of the synchronization signal by ADC. When the overflow interrupt of the main timer determines that it is a VA or VB signal:

[0094] VA pulse, the value read from ADC is the value of 0IRE;

[0095] VB pulse, the value read from ADC is -40IRE for NTSC and -43IRE for PAL;

[0096] Regardless of the NTSC or PAL format, calculating (VA-VB) / 4 can give an accurate voltage comparison value.

[0097] Differentiate between formats: NTSC: 720*480; PAL: 720*576

[0098] An image is scanned in odd and even fields. The number of lines between any two fields can be counted to distinguish the format. The median value is taken. If less than 264 lines, it is NTSC format, and if more than 264 lines, it is PAL format.

[0099] Distinguishing between odd and even fields: Regardless of whether it is NTSC or PAL, the obvious common feature is that the period of the last line is only half of the normal line period.

[0100] Image Processing:

[0101] Two built-in image buffer memories: s_graphics_data[], a whole row of overlay buffer data arranged in MAX7456 format, a total of 180 bytes, each 2 bits represents 1 pixel, a total of 720 pixels can be represented;

[0102] Each time a line sync signal appears, the last cached data is converted to the format of s_dma_data[] in the interrupt of the main timer, and then the overlay cache data of the next line is set through the preset callback function. s_dma_data[] is the control data finally used for DMA transmission, with a total length of 720+32 bytes. Each byte represents the output flip control logic of the high 8 bits or low 8 bits of a GPIO port, and each bit represents the pin number corresponding to the GPIO port; each time a line sync signal appears, the source memory of the output register to be transferred to the GPIO by DMA is set in the comparison interrupt; two steps are performed in the interrupt of the main timer: 1. Convert the set font data s_graphics_data[] to the memory format, 2. Execute the callback function to pre-set the data of the next line, so that before each data is actually transmitted by DMA, the data can be refreshed at the fastest and most stable speed higher than the actual transmission speed.

[0103] Other details: Shield the detection when the line data is sent: When the line synchronization signal is detected in the comparison interrupt, the software sets the interrupt to be shielded and the overflow time of the main timer is updated until the next overflow of the main timer occurs. This is to prevent the interference signal that may appear during the period from destroying the synchronization time. Automatically shield the overly long line superimposed data: When the falling edge appears in the comparison interrupt, record whether the line s_graphics_data[] has been sent. If it is found that it has not been sent, set the trimming length to avoid the risk of image loss caused by the synchronization signal being interfered by the superimposed signal due to unpredictable reasons. Generation of s_graphics_to_dma_tab[]: Execute _init_s_graphics_to_dma_tab() to print out the preemption priority of the static array interrupt: the comparison interrupt must be the highest preemption priority, the entire interrupt process size is about 1.1uS, and it is also the maximum time to interrupt the SPI slave response. Theoretically, it supports a maximum communication clock frequency of 8MHz; the processing time of the main timer is slightly longer, but about 5uS of redundant time is reserved. The interrupt preemption priority should be lower than the interrupt preemption priority of the SPI slave to ensure that the SPI slave can respond to the data from the host in time; the interrupt preemption priority of the SPI slave should be higher than the main timer to ensure a stable response to each received byte, but the maximum interrupt processing time should not exceed the redundant time set by the main timer.

[0104] It can be understood that, compared with the prior art, the beneficial effects and significant improvements of the present invention are:

[0105] (1) The character overlay function solution of the present invention has high integration and low cost. A single device can not only save the cost of traditional hardware OSD chips, but also free up the layout space of OSD chips;

[0106] (2) The solution using the character overlay function described in the present invention is more flexible and can be compatible with more different types of analog video signal cameras;

[0107] (3) The present invention can effectively speed up the development of data compatible with different types of superimposed character libraries;

[0108] (4) The present invention optimizes the data generation and transmission logic of the analog video signal with superimposed characters.

[0109] The embodiments of the present invention are described in detail above with reference to the accompanying drawings, but the present invention is not limited to the described embodiments. For those skilled in the art, various changes, modifications, substitutions and variations of these embodiments are made without departing from the principles and spirit of the present invention, and still fall within the scope of protection of the present invention.

Claims

1. A software implementation method for simulating video signal character overlay, characterized in that: The following steps are involved: Step S1, the analog video waveform is transmitted to the analog switch and the in-phase input port of the comparator, and at the same time, the digital-to-analog converter generates a specified comparison voltage which is input to the inverting input port of the comparator for comparison, and the comparison result is output to the main timer, which captures a synchronization time point; Step S2, using the storage access controller to transfer the synchronization time point and its configuration captured by the master timer to the slave timer, and at the same time, the master timer triggers the image conversion function algorithm corresponding to the image operation instruction issued by the instruction source according to the format of the line signal and the field signal to perform the graphic conversion at this synchronization time point, and generate the corresponding image storage memory; Step S3, the slave timer periodically triggers the storage access controller to move the data of the image storage memory to the two designated GPIOs according to the configuration transmitted by the master timer, thereby generating two corresponding signal pulses; Step S4, with the assistance of the digital-to-analog converter, jointly control the analog switch to generate an analog video signal after character superposition, and finally output it to the analog video output port.

2. The software implementation method for simulating video signal character superposition according to claim 1, characterized in that: The master timer interrupt is used to parse the synchronization signal and execute the line synchronization signal callback; the slave timer interrupt is used for delay and signal counting; the comparator is a voltage comparator, which is used to set the comparison threshold of the voltage comparator in real time; The analog-to-digital converter is used to sample analog signals and convert them into digital quantities, and the sampling time is required to be less than 2uS; the digital-to-analog converter is used to output the digital-to-analog converter module pin of the black level; the storage access controller is used for data transmission and handling.

3. The software implementation method for simulating video signal character overlay according to claim 2, characterized in that: The GPIO generates two built-in image cache memory data. When a line synchronization signal appears, the last cached data is converted into a specified format in the interrupt of the main timer, and then the overlay cache data of the next line is set through a preset callback function. This data is ultimately used to store the control data sent by the access controller.

4. The software implementation method for simulating video signal character overlay according to claim 1, characterized in that: The comparator detects the CVBS format, line and field synchronization signals, and outputs a hardware-level line synchronization timing; the line and field synchronization signals of the CVBS are both pulses with a negative voltage lower than 0.

5. The software implementation method for simulating video signal character overlay according to claim 4, characterized in that: The negative pulse width of the horizontal synchronization signal is 4.7uS.

6. The software implementation method for simulating video signal character overlay according to claim 4, characterized in that: The negative pulse of the field synchronization: Balanced pulse width: 2.35uS narrow pulse, denoted by VA later; Vertical sync pulse width: 27uS wide pulse, denoted by VB later; Among them, NTSC field synchronization 1: entire line period + VA*6 + VB*6 + VA*6 + H*13; NTSC field synchronization 2: half line period + VA*6 + VB*6 + VA*6 + H*13; PAL field synchronization 1: half line period + VA*5 + VB*5 + VA*5 + H*17; PAL field sync 2: entire line period + VA*5 + VB*5 + VA*5 + H*17.

7. The software implementation method for simulating video signal character overlay according to claim 6, characterized in that: There is enough time in the field equalization pulse (VA) and the field vertical synchronization pulse (VB) to sample the voltage value of the synchronization signal by ADC. When the overflow interrupt of the main timer determines that it is a VA or VB signal: VA pulse, the value read from ADC is the value of 0IRE; VB pulse, the value read from ADC is -40IRE for NTSC and -43IRE for PAL; Regardless of whether it is NTSC or PAL, calculating (VA-VB) / 4 will give an accurate voltage comparison value; Distinguish the format: NTSC: 720*480; PAL: 720*576. An image is scanned in odd and even fields. The number of lines between any two fields can be calculated to distinguish the format. Take the median value. If it is less than 264 lines, it is NTSC format, and if it is greater than 264 lines, it is PAL format.

8. The software implementation method for simulating video signal character overlay according to claim 6, characterized in that: When a row synchronization signal is detected in the comparison interrupt, the software sets the interrupt to be masked and updates the overflow time of the main timer until the next overflow of the main timer occurs. This is to prevent possible interference signals from destroying the synchronization time.

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