Semiconductor structure, preparation method thereof and storage system

Abstract

The invention provides a semiconductor structure, a preparation method thereof and a storage system, relates to the technical field of semiconductor chips, and aims to solve the problem of how to reduce electromagnetic interference generated between transistors. The semiconductor structure includes a plurality of active pillars, a gate structure, and an isolation structure. The plurality of active columns are arranged in an array along a first direction and a second direction. The gate structures extend in the first direction and are located between two adjacent rows of active columns. The isolation structures extend in the first direction and are located between two adjacent rows of active columns. Wherein the isolation structures and the gate structures are alternately arranged in the second direction and are respectively located at two opposite sides of the active columns. The isolation structure comprises a shielding layer, a first dielectric layer and a first insulating layer, the first insulating layer is located on one side of the shielding layer in the third direction, and the first dielectric layer is at least partially located on the other side, away from the first insulating layer, of the shielding layer. The semiconductor structure is used for realizing data reading and writing operations.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor chip technology, and in particular to a semiconductor structure and a preparation method thereof, and a storage system. Background Art

[0002] Dynamic Random Access Memory (DRAM) is composed of multiple storage cells, each of which is composed of a storage capacitor controlled by a transistor, that is, DRAM is a storage cell of 1 transistor and 1 storage capacitor (1T1C).

[0003] As the integration of memory arrays increases, the distance between transistors becomes closer and closer. How to reduce the electromagnetic interference generated between transistors is a problem that needs to be solved at present. Summary of the invention

[0004] The embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, and a storage system, which aim to solve the problem of how to reduce electromagnetic interference generated between transistors.

[0005] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:

[0006] In one aspect, a semiconductor structure is provided. The semiconductor structure comprises a plurality of active pillars, a gate structure and an isolation structure. The plurality of active pillars are arranged in an array along a first direction and a second direction, and the first direction and the second direction intersect. The gate structure extends along the first direction and is located between two adjacent rows of active pillars. The isolation structure extends along the first direction and is located between two adjacent rows of active pillars.

[0007] The isolation structure and the gate structure are alternately arranged in the second direction and are respectively located on opposite sides of the active pillar. The isolation structure includes a shielding layer, a first dielectric layer and a first insulating layer. Along the third direction, the first insulating layer is located on one side of the shielding layer, and the first dielectric layer is at least partially located on the other side of the shielding layer away from the first insulating layer; the first direction and the second direction are both perpendicular to the third direction.

[0008] In the semiconductor structure provided by the above-mentioned embodiments of the present disclosure, the shielding layer can be directly formed on the first dielectric layer. The height of the shielding layer can be controlled by the height of the first dielectric layer, which is beneficial to improving the height uniformity between multiple shielding layers and to improving the precise control of the height of the two ends of the shielding layer in the third direction. In this way, on the basis of avoiding the shielding layer causing leakage current to be generated in the first transistor, the overlapping area between the shielding layer and the adjacent gate layer is larger, thereby effectively isolating the interference between the two adjacent gate layers located on the opposite sides of the isolation structure.

[0009] In some embodiments, the first dielectric layer includes a first portion and a second portion. The first portion is located on a side of the shielding layer away from the first insulating layer. The second portion is located between the shielding layer and the active pillar, and between the first insulating layer and the active pillar.

[0010] In some embodiments, the thickness of the second portion is greater than or equal to the thickness of the first portion.

[0011] In some embodiments, the isolation structure further includes a second insulating layer, and the second insulating layer is disposed on a side of the first portion away from the first insulating layer.

[0012] In some embodiments, the isolation structure further includes a first isolation layer, wherein the first isolation layer is located between the first dielectric layer and the active pillar, and between the second insulating layer and the active pillar.

[0013] In some embodiments, the first isolation layer and the first dielectric layer are made of the same material.

[0014] In some embodiments, a material of the first dielectric layer includes at least one of silicon oxide, silicon nitride, silicon oxynitride, and aluminum oxide.

[0015] In some embodiments, the gate structure includes a gate layer, a gate dielectric layer and an insulating structure. The gate layer extends along the first direction and is disposed on the sidewall of the active column. The gate dielectric layer is disposed between the gate layer and the corresponding active column. The insulating structure at least covers both ends of the gate layer in the third direction.

[0016] In some embodiments, the insulating structure includes a first insulating portion and a second insulating portion. The first insulating portion includes a third portion and a fourth portion. Along the second direction, the third portion is located between gate layers in the same gate structure; along the third direction, the fourth portion covers the gate layer and one end of the third portion, and is located between gate dielectric layers in the same gate structure. The second insulating portion is disposed between two adjacent active pillars. Along the third direction, the second insulating portion covers the gate layer, the gate dielectric layer, and the other end of the third portion away from the fourth portion.

[0017] In some embodiments, the gate structure further includes a second isolation layer, wherein the second isolation layer is located between the gate dielectric layer and the active pillar, and between the second insulating portion and the active pillar.

[0018] In some embodiments, an orthographic projection of the shielding layer on a reference plane at least partially overlaps with an orthographic projection of an adjacent gate layer on the reference plane. The reference plane is perpendicular to the second direction.

[0019] In some embodiments, the orthographic projection of the shielding layer on the reference plane is located within the range of the orthographic projection of any adjacent gate layer on the reference plane.

[0020] In another aspect, a method for preparing a semiconductor structure is provided, comprising:

[0021] An intermediate semiconductor structure is formed. The intermediate semiconductor structure includes a substrate, a first sacrificial layer, and a second sacrificial layer. The substrate includes a base and a plurality of active pillars disposed on the base, the plurality of active pillars are arranged in an array along a first direction and a second direction, and the first direction intersects the second direction. The first sacrificial layer and the second sacrificial layer are alternately arranged in the second direction and are respectively located between two adjacent rows of active pillars.

[0022] A portion of the first sacrificial layer is removed to form a first sub-groove. An isolation structure is formed in the first sub-groove. The isolation structure includes a shielding layer and a first dielectric layer, and the first dielectric layer is at least located between the shielding layer and the remaining first sacrificial layer.

[0023] In some embodiments, forming an isolation structure in the first sub-groove includes: forming a first dielectric layer in the first sub-groove; the first dielectric layer covers the bottom wall and side walls of the first sub-groove; and forming a shielding layer in the first sub-groove.

[0024] In some embodiments, after forming the shielding layer in the first sub-groove, forming the isolation structure in the first sub-groove further includes: forming a first insulating layer in the first sub-groove.

[0025] In some embodiments, after forming the isolation structure in the first sub-groove, the preparation method further includes: removing the substrate and the remaining first sacrificial layer in sequence until the first dielectric layer is exposed; removing the remaining first sacrificial layer to form a second sub-groove; and forming a second insulating layer in the second sub-groove.

[0026] In some embodiments, the manufacturing method further includes: removing the second sacrificial layer to form a second trench, and forming a gate structure in the second trench.

[0027] In some embodiments, forming the intermediate semiconductor structure includes: preparing a substrate, wherein the substrate includes a first trench and a second trench extending along the first direction, wherein the first trench and the second trench are alternately arranged in the second direction and are respectively located between two adjacent rows of active pillars.

[0028] A first mask layer is formed on the substrate, the first mask layer covers the side of the active pillar away from the base and exposes the first trench and the second trench, and a second sacrificial layer is formed in the first trench and the second trench.

[0029] A second mask layer is formed on the side of the second sacrificial layer and the first mask layer away from the substrate. The second mask layer is located on the side of the first mask layer away from the substrate, at least covers the second sacrificial layer located in the second groove, and exposes the second sacrificial layer located in the first groove. The second sacrificial layer located in the first groove is removed, and a first sacrificial layer is formed in the first groove.

[0030] In some embodiments, during the process of removing the second sacrificial layer in the first groove, a portion of the first mask layer is also removed so that the width of the first groove in the second direction at one end away from the substrate is greater than the width of the first groove in the second direction at one end close to the substrate.

[0031] In some embodiments, before forming the first mask layer on the substrate, forming the intermediate semiconductor structure further comprises: forming a first isolation film on the substrate; the first isolation film covers the sidewalls and bottom walls of the first trench and the second trench. And / or,

[0032] Between forming a first mask layer on the substrate and forming a second sacrificial layer in the first trench and the second trench, the forming of the intermediate semiconductor structure also includes: forming a second isolation film in the first trench and the second trench; the second isolation film covers the side walls and bottom walls of the first trench and the second trench.

[0033] In some embodiments, the materials of the first sacrificial layer and the second sacrificial layer include titanium nitride and / or soluble organic carbon.

[0034] In another aspect, a storage system is provided, wherein the storage system comprises a memory and a controller, wherein the memory comprises the semiconductor structure described in any one of the above embodiments, and the controller is coupled to the memory to control the memory to store data.

[0035] It can be understood that the beneficial effects that can be achieved by the semiconductor structure preparation method and storage system provided by the above embodiments of the present disclosure can refer to the beneficial effects of the semiconductor structure described above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.

[0037] Figure 1 is a three-dimensional structural diagram of a memory according to some embodiments;

[0038] Figure 2 is a cross-sectional view of a memory according to some embodiments;

[0039] Figure 3 for Figure 1 A structural diagram of a storage unit in ;

[0040] Figure 4 for Figure 3 The equivalent circuit diagram of the memory cell shown;

[0041] Figure 5 is a top view of a semiconductor structure according to some embodiments;

[0042] Figure 6 for Figure 5 A cross-sectional view along the section line AA;

[0043] Figure 7 for Figure 5 Another cross-sectional view along the section line AA;

[0044] Figure 8 for Figure 5 Another cross-sectional view along section line AA;

[0045] Fig. 9 for Figure 5 Another cross-sectional view along section line AA;

[0046] Fig.10 for Figure 5 Another cross-sectional view along section line AA;

[0047] Figures 11 to 18 is a flow chart of a method for preparing a semiconductor structure according to some embodiments;

[0048] Figure 19 to Figure 22 is a process step diagram of a method for preparing a semiconductor structure according to some embodiments;

[0049] Fig.23is a top view of a substrate according to some embodiments;

[0050] Fig.24 is a block diagram of a storage system according to some embodiments;

[0051] Fig.25 is a block diagram of a storage system according to some other embodiments. DETAILED DESCRIPTION

[0052] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.

[0053] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0054] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0055] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0056] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.

[0057] “At least one of A, B, and C” has the same meaning as “at least one of A, B, or C” and both include the following combinations of A, B, and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0058] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0059] The use of "adapted to" or "configured to" herein is meant to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0060] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0061] In the context of the present disclosure, the meanings of “on,” “over,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “over” or “above” means not only “above” or “over” something, but also includes the meaning of “above” or “over” something without intervening features or layers therebetween (i.e., directly on something).

[0062] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0063] As used herein, the term "substrate" refers to a material on which subsequent material layers may be added. The substrate itself may be patterned. The material added to the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of non-conductive materials such as glass, plastic, or sapphire wafers.

[0064] Figure 1 is a three-dimensional structural diagram of a memory according to some embodiments, Figure 2 is a cross-sectional view of a memory according to some embodiments, Figure 3 for Figure 1 The structure diagram of a storage unit in Figure 4 for Figure 3 The equivalent circuit diagram of the memory cell is shown.

[0065] It should be noted that in Figure 1 and Figure 2 In the embodiment, the memory 10 extends in the XY plane, and the first direction X and the second direction Y are, for example, two orthogonal directions in the plane where the memory 10 is located (for example, the plane where the source layer SL is located): the first direction X is, for example, the extension direction of the word line WL, and the second direction Y is, for example, the extension direction of the bit line BL. The third direction Z is perpendicular to the plane where the memory 10 is located, that is, perpendicular to the XY plane.

[0066] See also Figure 1 and Figure 2 Some embodiments of the present disclosure provide a memory 10 including a semiconductor device 100 and a peripheral device 200. The peripheral device 200 may be disposed on one side of the semiconductor device 100.

[0067] like Figure 2 As shown, the semiconductor device 100 may include a memory cell array 110 and a source layer SL. The peripheral device 200 may be disposed on a side of the memory cell array 110 away from the source layer SL, for example.

[0068] See also Figure 2 and Figure 3 The source layer SL may be connected to a first reference voltage, which may be a ground voltage or other voltages. The source layer SL may include a semiconductor material, such as single crystal silicon, single crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, and other suitable semiconductor materials. The source layer SL may be partially or fully doped. Exemplarily, the source layer SL may include a doped region, which is doped with a p-type dopant. The source layer SL may also include a non-doped region.

[0069] See also Figure 1 and Figure 2The memory cell array 110 includes a plurality of memory cells 111 arranged in an array along a first direction X and a second direction Y.

[0070] Among them, Figure 3 and Figure 4 As shown, the memory cell 111 includes a first transistor T1 and a capacitor C. The first electrode of the first transistor T1 is connected to the bit line BL, the second electrode of the first transistor T1 is connected to one plate of the capacitor C, and the other plate of the capacitor C can be connected to the source layer SL. The gate of the first transistor T1 is connected to the word line WL. In this way, the first transistor T1 can be turned on or off by applying a voltage through the word line WL, and when the first transistor T1 is turned on, the bit line BL performs a read or write operation on the first transistor T1.

[0071] In some embodiments, see Figure 1 and Figure 2 The semiconductor device 100 may further include an array interconnect layer 120 . The array interconnect layer 120 may be coupled to the memory cell 111 .

[0072] The array interconnect layer 120 may include a word line WL and a bit line BL. The word line WL may be coupled to the gate of the first transistor T1 in at least one memory cell 111. The bit line BL may be coupled to the first electrode of the first transistor T1 in at least one memory cell 111.

[0073] For example, Figure 2 As shown, the array interconnect layer 120 may include one or more first interconnect conductor layers 121 , one or more first interlayer insulating layers 122 , and a plurality of first contacts 123 insulated from each other by the first interlayer insulating layers 122 .

[0074] The first interconnect conductor layer 121 may include a plurality of bit lines BL and word lines WL (see Figure 1 ), etc., different first interconnect conductor layers 121 may be coupled via first contacts 123. The plurality of first contacts 123 may include, for example, bit line contacts and / or word line contacts, the bit line contacts being coupled to the bit lines BL, and the word line contacts being coupled to the word lines WL.

[0075] The material of the first interconnect conductor layer 121 and the first contact 123 may be a conductive material, such as a combination of one or more of tungsten, cobalt, copper, aluminum, and metal silicide, or other suitable materials.

[0076] The material of the first interlayer insulating layer 122 is an insulating material, and the insulating material is, for example, a combination of one or more of silicon oxide, silicon nitride, and a high dielectric constant insulating material, or may be other suitable materials.

[0077] like Figure 2As shown, the peripheral device 200 may include a peripheral circuit. The peripheral circuit is configured to control and sense the array device. The peripheral circuit may be any suitable digital, analog, and / or mixed signal control and sensing circuit for supporting the operation (or work) of the array device, including but not limited to a page buffer, a decoder (e.g., a row decoder and a column decoder), a sense amplifier, a driver (e.g., a word line driver), a charge pump, a current or voltage reference, or any active or passive component of the circuit (e.g., a transistor, a diode, a resistor, or a capacitor). The peripheral circuit may also include any other circuit compatible with an advanced logic process, including a logic circuit (e.g., a processor and a programmable logic device (PLD) or a storage circuit (e.g., a static random access memory (SRAM)).

[0078] In some embodiments, Figure 2 As shown, the peripheral device 200 may include a substrate 210, a second transistor T2 disposed on the substrate 210, and a peripheral interconnect layer 220 disposed on the substrate 210. The peripheral circuit may include the second transistor T2.

[0079] The substrate 210 may be made of single crystal silicon or other suitable materials, such as silicon germanium, germanium or silicon-on-insulator thin film. The peripheral interconnection layer 220 is coupled to the second transistor T2 to transmit electrical signals between the transistor T2 and the peripheral interconnection layer 220 .

[0080] For example, Figure 2 As shown, the peripheral interconnection layer 220 may include one or more second interconnection conductor layers 231, one or more second interlayer insulating layers 232, and a plurality of second contacts 233 insulated from each other by the second interlayer insulating layers 232. Different second interconnection conductor layers 231 may be coupled via the second contacts 233.

[0081] The second interconnect conductor layer 231 and the second contact 233 may be made of a conductive material, such as tungsten, cobalt, copper, aluminum, or a combination of one or more metal silicides, or other suitable materials.

[0082] The material of the second interlayer insulating layer 232 is an insulating material, and the insulating material is, for example, a combination of one or more of silicon oxide, silicon nitride, and a high dielectric constant insulating material, or other suitable materials.

[0083] The peripheral interconnect layer 220 can be coupled to the array interconnect layer 120, so that the semiconductor device 100 and the peripheral device 200 can be coupled. Specifically, since the peripheral interconnect layer 220 is coupled to the array interconnect layer 120, the peripheral circuit in the peripheral device 200 can be coupled to the memory cell 111 in the semiconductor device 100 to achieve the transmission of electrical signals between the peripheral circuit and the memory cell 111.

[0084] In some possible implementations, the peripheral interconnect layer 220 is bonded to the array interconnect layer 120, so that the second contact 233 in the peripheral interconnect layer 220 contacts the corresponding first contact 123 in the array interconnect layer 120, so that the peripheral circuit in the peripheral device 200 can be coupled to the memory cell 111 in the semiconductor device 100. The surface where the peripheral interconnect layer 220 and the array interconnect layer 120 contact can be referred to as a bonding surface S.

[0085] See also Figure 1 and Figure 2 , some embodiments of the present disclosure provide a semiconductor structure 400. The memory 10 includes the semiconductor structure 400. Exemplarily, the semiconductor structure 400 may be the memory 10, for example, the semiconductor structure 400 includes a semiconductor device 100 and a peripheral device 200. Exemplarily, the semiconductor structure 400 may also be a part of the memory 10, for example, the semiconductor structure 400 is the semiconductor device 100 in the memory 10, which is not specifically limited in the embodiments of the present disclosure.

[0086] In some embodiments, see Figure 2 and Figure 5 , the semiconductor structure 400 includes a plurality of active pillars 410 , a gate structure 420 and an isolation structure 430 .

[0087] like Figure 5 As shown, a plurality of active pillars 410 are arranged in an array along a first direction X and a second direction Y.

[0088] For example, see Figure 5 and Figure 6 The active pillar 410 extends along the third direction Z and includes a first electrode 411, a channel 412 and a second electrode 413 of the first transistor T1. The first electrode 411 and the second electrode 413 are two opposite ends of the active pillar 410 in the third direction Z, and the channel 412 is located between the first electrode 411 and the second electrode 413.

[0089] The material of the channel 412 includes a semiconductor material, and the materials of the first electrode and the second electrode may include a semiconductor material doped with a P-type dopant or an N-type dopant.

[0090] It should be noted that the semiconductor material is, for example, single crystal silicon, polycrystalline silicon, single crystal germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials and other suitable semiconductor materials. The P-type dopant includes boron or gallium. The N-type dopant includes phosphorus or arsenic.

[0091] like Figure 5 As shown, the gate structure 420 extends along the first direction X and is located between two adjacent rows of active pillars 410 .

[0092] For example, see Figure 5 and Figure 6 The gate structure 420 includes a gate layer 421 and a gate dielectric layer 422. The gate layer 421 is disposed on the sidewall of the active pillar 410 to form the gate of the first transistor T1. The gate dielectric layer 422 is disposed between the gate layer 421 and the corresponding active pillar 410 to insulate the gate layer 421 from the active pillar 410.

[0093] It should be noted that the orthographic projection of the channel 412 on the reference plane is located within the range of the orthographic projection of the gate layer 421 on the reference plane, so that the first pole 411 and the second pole 413 at both ends of the channel 412 can be turned on or off under the control of the voltage of the gate layer 421. The reference plane is perpendicular to the second direction Y.

[0094] Based on this, the gate layer 421 and the corresponding active pillar 410 form a first transistor T1. When the voltage received by the gate layer 421 from the word line WL is greater than the threshold voltage of the first transistor T1, the first transistor T1 is turned on. When the voltage received by the gate layer 421 from the word line WL is less than or equal to the threshold voltage of the first transistor T1, the first transistor T1 is turned off.

[0095] like Figure 5 As shown, the isolation structure 430 extends along the first direction X and is located between two adjacent rows of active pillars 410 , so that two adjacent active pillars 410 in the second direction Y are insulated.

[0096] The isolation structures 430 and the gate structures 420 are alternately arranged in the second direction Y and are respectively located on two opposite sides of the active pillar 410 .

[0097] For example, see Figure 5 and Figure 6 The isolation structure 430 includes a shielding layer 431, which can be connected to a second reference voltage to isolate the interference of one gate layer 421 on the active pillar 410 corresponding to the other gate layer 421 in two adjacent gate layers 421 located on opposite sides of the isolation structure 430, thereby reducing the electromagnetic interference generated between adjacent first transistors T1.

[0098] It should be noted that the second reference voltage may be, for example, a negative voltage, or other voltages. The material of the shielding layer 431 includes a conductive material; for example, the material of the shielding layer 431 includes titanium nitride.

[0099] It should be understood that the orthographic projection of the shielding layer 431 on the reference plane at least partially overlaps with the orthographic projection of the adjacent gate layer 421 on the reference plane, so as to reduce interference between two adjacent gate layers 421 located on opposite sides of the isolation structure 430 .

[0100] When the orthographic projection of the shielding layer 431 on the reference plane covers the gate layer 421 , the shielding layer 431 will have an adverse effect on the conduction and cutoff of the channel 412 , thereby increasing the risk of leakage current of the first transistor T1 .

[0101] Based on this, the orthographic projection of the shielding layer 431 on the reference plane is located within the range of the orthographic projection of any adjacent gate layer 421 on the reference plane, so as to prevent the shielding layer 431 from causing leakage current of the first transistor T1 .

[0102] In addition, when the second reference voltage is fixed, the larger the overlap area of ​​the orthographic projection of the shielding layer 431 on the reference plane and the orthographic projection of the adjacent gate layer 421 on the reference plane is, the better the shielding effect of the shielding layer 431 is. Therefore, it is very important to control the height of both ends of the shielding layer 431 in the third direction Z (the distance from the bonding surface S).

[0103] It should be understood that when the shielding layer 431 is directly etched to control the height of both ends of the shielding layer 431 in the third direction Z, the shielding layer 431 needs to undergo at least two etching processes. The first etching is to etch from the side of the shielding layer 431 away from the bonding surface S, so that the end of the shielding layer 431 away from the bonding surface S is lower than the end of the gate layer 421 away from the bonding surface S. The second etching is to etch from the side of the shielding layer 431 close to the bonding surface S, so that the end of the shielding layer 431 close to the bonding surface S is higher than the end of the gate layer 421 close to the bonding surface S.

[0104] However, there are other process steps between the first etching and the second etching, and the process conditions of at least one of the other process steps include high temperature, which causes the lattice of the shielding layer 431 to change and reorganize, resulting in holes in the shielding layer 431. Since holes are generated in the shielding layer 431, in the second etching, the etching depth cannot be accurately controlled by directly etching the shielding layer 431, which makes it difficult to control the height of the end of the shielding layer 431 close to the bonding surface S.

[0105] Based on this, see Figure 5 and Figure 6In the semiconductor structure 400 provided in the present disclosure, the isolation structure 430 further includes a first dielectric layer 432, and the first dielectric layer 432 is at least partially located on a side of the shielding layer 431 away from the bonding surface S. In this case, the shielding layer 431 can be directly formed on the first dielectric layer 432, and the height of the end of the shielding layer 431 close to the bonding surface S can be controlled by the height of the first dielectric layer 432, which is conducive to improving the uniformity of the heights between the multiple shielding layers 431, and is conducive to improving the precise control of the heights of the two ends of the shielding layer 431 in the third direction Z. The specific process method can be referred to below, and the embodiments of the present disclosure will not be described in detail here.

[0106] At this time, the precise control of the height of the two ends of the shielding layer 431 in the third direction Z can make the overlapping area between the shielding layer 431 and the adjacent gate layer 421 larger while avoiding the shielding layer 431 causing leakage current in the first transistor T1, thereby effectively isolating the interference between the two adjacent gate layers 421 located on the opposite sides of the isolation structure 430.

[0107] It should be noted that the material of the first dielectric layer 432 includes at least one of silicon oxide, silicon nitride, silicon oxynitride and aluminum oxide; for example, the material of the first dielectric layer 432 includes silicon oxide.

[0108] In some embodiments, Figure 6 As shown, the first dielectric layer 432 includes a first portion 4321 and a second portion 4322, wherein the first portion 4321 is located on a side of the shielding layer 431 close to the bonding surface S, and the second portion 4322 is located between the shielding layer 431 and the active pillar 410. In the process of forming the second portion 4322, the first portion 4321 can be formed simultaneously, and the first portion 4321 can play an insulating protection role, and the process is simple.

[0109] The thickness of the second portion 4322 is greater than or equal to the thickness of the first portion 4321. The second portion 4322 of the first dielectric layer 432 can be used as a stop layer for etching the sacrificial material from one side of the bonding surface S, which is helpful to simplify the difficulty of the etching process.

[0110] In some embodiments, Figure 6 As shown, the isolation structure 430 further includes a first insulating layer 433, and the first insulating layer 433 is located on one side of the shielding layer 431 along the third direction Z. For example, along the third direction Z, the first insulating layer 433 is located on one side of the shielding layer 431 away from the bonding surface S, and the first dielectric layer 432 is at least partially located on the other side of the shielding layer 431 away from the first insulating layer 433.

[0111] It should be noted that the material of the first insulating layer 433 includes any one of silicon oxide, silicon nitride, silicon oxynitride and a high dielectric constant insulating material. For example, the material of the first insulating layer 433 includes silicon nitride.

[0112] When the first dielectric layer 432 includes a first portion 4321 and a second portion 4322 , the first portion 4321 is located on a side of the shielding layer 431 away from the first insulating layer 433 , and the second portion 4322 is also located between the first insulating layer 433 and the active pillar 410 .

[0113] The end of the first insulating layer 433 away from the shielding layer 431 is flush with the end of the active pillar 410, that is, the first insulating layer 433 fills the gap between the active pillars 410 on the upper side of the shielding layer 431 to play a flat and supporting role.

[0114] In addition, the first insulating layer 433 and the first dielectric layer 432 may be made of the same material or different materials. Figure 8 As shown, the structure formed by the first insulating layer 433 and the first dielectric layer 432 surrounds the shielding layer 431. Moreover, the upper end of the structure formed by the first insulating layer 433 and the first dielectric layer 432 is flush with the upper ends of the active pillars 410 on both sides, and the lower end is higher than the lower ends of the active pillars 410 on both sides. At the same time, the thickness of the portion located on the upper side of the shielding layer 431 is greater than the thickness of the portion located on the lower side of the shielding layer 431.

[0115] In some embodiments, Figure 6 As shown, the isolation structure 430 further includes a second insulating layer 434 , and the second insulating layer 434 is disposed on a side of the first portion 4321 away from the first insulating layer 433 .

[0116] The end of the second insulating layer 434 away from the shielding layer 431 is flush with the end of the active pillar 410, that is, the second insulating layer 434 fills the gap between the active pillars 410 under the shielding layer 431 to play a flat and supporting role.

[0117] It should be noted that the material of the second insulating layer 434 includes any one of silicon oxide, silicon nitride, silicon oxynitride and a high dielectric constant insulating material; for example, the material of the second insulating layer 434 includes silicon nitride.

[0118] In addition, the materials of the first insulating layer 433, the second insulating layer 434 and the first dielectric layer 432 may be the same or different. In the case where the materials of the first insulating layer 433, the second insulating layer 434 and the first dielectric layer 432 are the same, as Fig. 9As shown, the structure formed by the first insulating layer 433, the first dielectric layer 432 and the second insulating layer 434 surrounds the shielding layer 431. The two ends of the structure formed by the first insulating layer 433, the first dielectric layer 432 and the second insulating layer 434 in the third direction Z are flush with the active pillars 410 on both sides.

[0119] In some embodiments, Figure 6 As shown, the isolation structure 430 further includes a first isolation layer 435, which is located between the first dielectric layer 432 and the active pillar 410, and between the second insulating layer 434 and the active pillar 410, so as to play an insulating protection role and prevent the sidewall of the active pillar 410 from being damaged by etching.

[0120] It should be noted that the material of the first isolation layer 435 includes any one of silicon oxide, silicon nitride, silicon oxynitride and a high dielectric constant insulating material; for example, the material of the first isolation layer 435 includes silicon oxide.

[0121] The material of the first isolation layer 435 and the material of the first dielectric layer 432 may be the same or different. For example, the material of the first isolation layer 435 and the material of the first dielectric layer 432 are the same.

[0122] In addition, see Figure 6 and Figure 7 , the first isolation layer 435 can be a single-layer structure or a multi-layer structure. Figure 6 As shown, the first isolation layer 435 is a single-layer structure. Figure 7 As shown, the first isolation layer 435 includes two first isolation sub-layers 4351 sequentially disposed away from the active pillar 410 , and the materials of the two first isolation sub-layers 4351 may be different.

[0123] In addition, the materials of the first isolation layer 435, the first insulating layer 433, the second insulating layer 434 and the first dielectric layer 432 may be the same or different. In the case where the materials of the first isolation layer 435, the first insulating layer 433, the second insulating layer 434 and the first dielectric layer 432 are the same, as Fig.10 As shown, the structure formed by the first isolation layer 435, the first insulating layer 433, the second insulating layer 434 and the first dielectric layer 432 surrounds the shielding layer 431 and contacts the active pillar 410. At the same time, the structure formed by the first isolation layer 435, the first insulating layer 433, the second insulating layer 434 and the first dielectric layer 432 is flush with the active pillars 410 on both sides at both ends in the third direction Z.

[0124] In some embodiments, Figure 6As shown, the gate structure 420 further includes an insulating structure 423, which covers at least two ends of the gate layer 421 in the third direction Z to play a supporting role, thereby reducing the risk of collapse of the semiconductor structure 400. At the same time, the insulating structure 423 can also play an insulating role to prevent the gate layer 421 from being short-circuited with other conductive structures (such as the first pole 411 of the active pillar 410).

[0125] For example, see Figure 6 , the insulating structure 423 includes a first insulating portion 4230 and a second insulating portion 4240 .

[0126] like Figure 6 As shown, the first insulating portion 4230 includes a third portion 4231 and a fourth portion 4232. Along the second direction Y, the third portion 4231 is located between the gate layers 421 in the same gate structure 420 to reduce the risk of short circuit between the gate layers 421 in the same gate structure 420 and provide support. Along the third direction Z, the fourth portion 4232 covers the gate layer 421 and one end of the third portion 4231, and is located between the gate dielectric layers 422 in the same gate structure 420 to play a flat and support role.

[0127] like Figure 6 As shown, the second insulating portion 4240 is disposed between two adjacent active pillars 410. Along the third direction Z, the second insulating portion 4240 covers the gate layer 421, the gate dielectric layer 422 and the other end of the third portion 4231 away from the fourth portion 4232 to prevent the gate layer 421 from shorting with the first pole 411 of the active pillar 410 and provide support.

[0128] In some embodiments, see Figure 6 , the second insulating part 4240 includes a third insulating layer 4241 and a fourth insulating layer 4242 .

[0129] like Figure 6 As shown, the third insulating layer 4241 is located between the fourth insulating layer 4242 and the active pillars 410 on both sides, and on the side of the fourth insulating layer 4242 away from the first insulating portion 4230. The portion of the third insulating layer 4241 located on the side of the fourth insulating layer 4242 away from the first insulating portion 4230 may be flush with the end of the active pillar 410.

[0130] In some embodiments, Figure 6 As shown, the gate structure 420 further includes a second isolation layer 424, which is located between the gate dielectric layer 422 and the active pillar 410, and between the second insulating portion 4240 and the active pillar 410, so as to play an insulating protection role and prevent the sidewall of the active pillar 410 from being etched and damaged.

[0131] It should be noted that the material of the second isolation layer 424 includes any one of silicon oxide, silicon nitride, silicon oxynitride and a high dielectric constant insulating material; for example, the material of the second isolation layer 424 includes silicon oxide.

[0132] The material of the second isolation layer 424 and the material of the first isolation layer 435 may be the same or different. For example, the material of the second isolation layer 424 and the material of the first isolation layer 435 are the same.

[0133] In addition, the second isolation layer 424 may be a single-layer structure or a multi-layer structure. Figure 6 As shown, the second isolation layer 424 is a single-layer structure. Figure 7 As shown, the second isolation layer 424 includes two second isolation sub-layers 4243 sequentially disposed away from the active pillar 410 , and the materials of the two second isolation sub-layers 4243 may be different.

[0134] In some embodiments, see Figure 6 In the case where the first isolation layer 435 is a single-layer structure, the second isolation layer 424 is a single-layer structure, and the first isolation layer 435 and the second isolation layer 424 are prepared in the same process step, and the process is simple.

[0135] In other embodiments, see Figure 7 In the case where the first isolation layer 435 includes two first isolation sub-layers 4351, the second isolation layer 424 includes two second isolation sub-layers 4243. The first isolation sub-layer 4351 that is closer to the corresponding active pillar 410 and the second isolation sub-layer 4243 that is closer to the corresponding active pillar 410 are prepared in the same process step; the first isolation sub-layer 4351 that is farther away from the corresponding active pillar 410 and the second isolation sub-layer 4243 that is farther away from the corresponding active pillar 410 are prepared in the same process step, and the process is simple.

[0136] The embodiment of the present disclosure provides a method for preparing a semiconductor structure 400, such as Fig.11 As shown, the preparation method includes steps S100 to S300.

[0137] S100: See Fig.19 and Fig.21 , forming an intermediate semiconductor structure 400'.

[0138] In the above steps, the intermediate semiconductor structure 400' includes a substrate 500, a first sacrificial layer 610, and a second sacrificial layer 620. Fig.23As shown, the substrate 500 includes a base 510 and a plurality of active pillars 410 disposed on the base 510, and the plurality of active pillars 410 are arranged in an array along a first direction X and a second direction Y. The first sacrificial layer 610 and the second sacrificial layer 620 are alternately arranged in the second direction Y and are respectively located between two adjacent rows of active pillars 410.

[0139] It should be noted that the materials of the first sacrificial layer 610 and the second sacrificial layer 620 include titanium nitride and / or soluble organic carbon.

[0140] For some examples, see Fig.12 , S100 includes S110~S150.

[0141] S110: See Fig.19 and Fig.21 , prepare a substrate 500.

[0142] In the above steps, if Fig.23 As shown, the substrate 500 includes a first trench 520 and a second trench 530 extending along a first direction X. The first trench 520 and the second trench 530 are alternately arranged in a second direction Y and are respectively located between two adjacent rows of active pillars 410 .

[0143] Among them, see Fig.13 , S110 may specifically include S111 to S112.

[0144] S111: See Fig.19 and Fig.21 , providing an initial substrate 500'.

[0145] In the above steps, the initial substrate 500 ′ includes a first base 511 , and a second base 512 and a semiconductor layer 513 are sequentially formed on the first base 511 .

[0146] The substrate 510 includes a first substrate 511 and a second substrate 512 , and the active pillar 410 is located in a semiconductor layer 513 .

[0147] It should be noted that the material of the first substrate 511 may include at least one of single crystal silicon, polycrystalline silicon, single crystal germanium, III-V compound semiconductor materials, IIVI compound semiconductor materials, or other semiconductor materials known in the art. The material of the second substrate 512 may include silicon oxide, and the material of the semiconductor layer 513 may include polycrystalline silicon.

[0148] S112: See Fig.19 and Fig.21 , forming a first trench 520 and a second trench 530 .

[0149] In the above steps, the first trench 520 and the second trench 530 penetrate the semiconductor layer 513 and stop at the second substrate 512. Here, the first trench 520 and the second trench 530 can be formed by a dry or wet etching process.

[0150] In one feasible implementation, in the process of S120, a third trench 540 extending along the second direction Y may be formed, and the third trench 540 intersects with the first trench 520 and the second trench 530, so that the semiconductor layer 513 is patterned into a plurality of array-arranged active pillars 410. In another feasible implementation, the third trench 540 extending along the second direction Y may be formed separately.

[0151] It should be noted that an insulating material is filled between two adjacent active pillars 410 along the first direction X, so that the two adjacent active pillars 410 along the first direction X are insulated.

[0152] S120: See Fig.19 and Fig.21 , a first mask layer 630 is formed on the substrate 500 .

[0153] In the above steps, the first mask layer 630 covers the side of the active pillar 410 away from the substrate 510 and exposes the first trench 520 and the second trench 530. Here, the first mask layer 630 can be formed by, for example, sequentially using a coating process, an exposure process, and a development process.

[0154] S130: See Fig.19 and Fig.21 , a second sacrificial layer 620 is formed in the first trench 520 and the second trench 530 .

[0155] In the above steps, the second sacrificial layer 620 can be formed by first depositing sacrificial material on the entire surface of the second sacrificial layer 620 using a thin film deposition process, so that the sacrificial material fills the first trench 520 and the second trench 530; then, a dry or wet etching process is used to remove the portion covering the upper side of the first mask layer 630. The thin film deposition process includes any one of chemical vapor deposition (CVD), physical vapor deposition (PVD), and atomic layer deposition (ALD).

[0156] S140: See Fig.19 and Fig.21 A second mask layer 640 is formed on a side of the second sacrificial layer 620 and the first mask layer 630 away from the substrate 510 .

[0157] In the above steps, the second mask layer 640 is located on the side of the first mask layer 630 away from the substrate 510. The second mask layer 640 at least covers the second sacrificial layer 620 located in the second groove 530, and exposes the second sacrificial layer 620 located in the first groove 520. Here, the second mask layer 640 can be formed by, for example, a coating process, an exposure process, and a development process in sequence.

[0158] It should be noted that the width of the opening of the second mask layer 640 in the second direction Y may be, for example, greater than the width of the first trench 520 in the second direction Y, so as to facilitate the subsequent removal of the second sacrificial layer 620 in the first trench 520 .

[0159] S150: See Fig.19 and Fig.21 , remove the second sacrificial layer 620 in the first trench 520 , and form a first sacrificial layer 610 in the first trench 520 .

[0160] In the above steps, the first sacrificial layer 610 may also cover the surface of the second mask layer 640 away from the substrate 510. The second sacrificial layer 620 may be removed by, for example, a dry or wet etching process. The first sacrificial layer 610 may be formed by, for example, a thin film deposition process.

[0161] In addition, in the process of removing the first sacrificial layer 610 located in the first groove 520 in S150, part of the first mask layer 630 can also be removed, so that the width of the first groove 520 at the end away from the substrate 510 in the second direction Y is greater than the width of the first groove 520 at the end close to the substrate 510 in the second direction Y. This is conducive to depositing materials in the first groove 520 and facilitating the formation of an isolation structure 430 in the first groove 520.

[0162] In some embodiments, see Fig.14 , before 120, S100 also includes S160.

[0163] S160: See Fig.19 , a first isolation film 650 is formed on the substrate 500 .

[0164] In the above steps, the first isolation film 650 covers the sidewalls and bottom walls of the first trench 520 and the second trench 530. The first isolation film 650 can be formed by, for example, a thin film deposition process.

[0165] When the first isolation layer 435 and the second isolation layer 424 are a single-layer structure, the portion of the first isolation film 650 located in the first trench 520 forms the first isolation layer 435 , and the portion of the first isolation film 650 located in the second trench 530 forms the second isolation layer 424 .

[0166] When the first isolation layer 435 and the second isolation layer 424 are a multi-layer structure, the portion of the first isolation film 650 located in the first trench 520 forms a first isolation sublayer 4351 , and the portion of the first isolation film 650 located in the second trench 530 forms a second isolation sublayer 4243 .

[0167] In some embodiments, see Fig.14 , between S120 and S130, S100 also includes S170.

[0168] S170: See Fig.21 , a second isolation film 660 is formed in the first trench 520 and the second trench 530 .

[0169] In the above steps, the second isolation film 660 covers the side walls and bottom walls of the first trench 520 and the second trench 530. The second isolation film 660 can be formed by, for example, first depositing an insulating material on the entire surface using a thin film deposition process; then, using a dry or wet etching process to remove the portion covering the upper side of the first mask layer 630.

[0170] S200: See Fig. 20 and Fig. 22 , a portion of the first sacrificial layer 610 is removed to form a first sub-groove 521 .

[0171] In the above steps, the portion of the first sacrificial layer 610 removed can be specifically determined according to the required height of the shielding layer 431 formed in a subsequent process close to the end of the substrate 510, so that the height of the shielding layer 431 away from the substrate 510 close to the end of the substrate 510 is higher than the height of the gate layer 421 formed subsequently close to the end of the substrate 510. For example, the first sacrificial layer 610 can be partially removed by controlling the etching time using a dry or wet etching process.

[0172] S300: See Fig. 20 and Fig. 22 , an isolation structure 430 is formed in the first sub-groove 521 .

[0173] In the above steps, the isolation structure 430 includes a shielding layer 431 and a first dielectric layer 432, and the first dielectric layer 432 is at least located between the shielding layer 431 and the remaining first sacrificial layer 610. Exemplarily, the first dielectric layer 432 covers the sidewalls and the bottom wall of the first sub-groove 521, and the first dielectric layer 432 covers a portion of the bottom wall of the first sub-groove 521, and is located between the shielding layer 431 and the remaining first sacrificial layer 610.

[0174] In some embodiments, see Fig.15 , S300 includes S310~S320.

[0175] S310: See Fig. 20 and Fig. 22 , a first dielectric layer 432 is formed in the first sub-groove 521 .

[0176] In the above steps, the first dielectric layer 432 covers the bottom wall and sidewalls of the first sub-groove 521. The first dielectric layer 432 can be formed by depositing insulating material on the entire surface using a thin film deposition process, and then removing the portion covering the upper side of the second mask layer 640 using a dry or wet etching process.

[0177] S320: See Fig. 20 and Fig. 22 , a shielding layer 431 is formed in the first sub-groove 521 .

[0178] In the above steps, the height of the end of the shielding layer 431 away from the substrate 510 is lower than the height of the active pillar 410. The height of the end of the shielding layer 431 away from the substrate 510 can be specifically preset so that the height of the end of the shielding layer 431 away from the substrate 510 is lower than the height of the end of the gate layer 421 formed subsequently away from the substrate 510. The shielding layer 431 can be formed by, for example, depositing a conductive material on the entire surface using a thin film deposition process; and then removing the portion covering the upper side of the second mask layer 640 using a dry or wet etching process.

[0179] In some embodiments, see Fig.15 , after S320, S300 also includes S330.

[0180] S330: See Fig. 20 and Fig. 22 , a first insulating layer 433 is formed in the first sub-groove 521 .

[0181] In the above steps, the first insulating layer 433 fills the first sub-groove 521. The first insulating layer 433 can be formed by depositing insulating material on the entire surface using a thin film deposition process, and then removing the portion covering the upper side of the second mask layer 640 using a dry or wet etching process.

[0182] In some embodiments, see Fig. 20 The material of the first sacrificial layer 610 is an insulating material, for example, soluble organic carbon.

[0183] At this time, if Fig. 20 As shown, the remaining first sacrificial layer 610 may not be removed. In the subsequent process, only the substrate 510 is removed, and the intermediate semiconductor structure 400 ′ after the substrate 510 is removed is connected to the capacitor C.

[0184] It should be noted that, before removing the substrate 510 , the intermediate semiconductor structure 400 ′ may also be firstly prepared with a capacitor C and a source layer SL.

[0185] In other embodiments, see Fig.16 The above preparation method also includes S400 to S500.

[0186] S400: See Fig. 22 , the substrate 510 and the remaining first sacrificial layer 610 are removed in sequence until the first dielectric layer 432 is exposed.

[0187] In the above steps, the substrate 510 can be removed by any one of a dry etching process, a wet etching process and a planarization process, for example. For example, the substrate 510 can be removed by chemical mechanical polishing. The remaining first sacrificial layer 610 can be removed by a dry or wet etching process, for example.

[0188] It should be noted that the etching selectivity ratio between the first sacrificial layer 610 and the first dielectric layer 432 may be greater than 1, so that the first dielectric layer 432 can be used as a stop layer for the first sacrificial layer 610 , thereby reducing the difficulty of the process.

[0189] When the preparation method includes S160 , in the process of S400 , the portion of the first isolation film 650 covering the bottom wall of the first trench 520 and the second trench 530 is further removed.

[0190] When the preparation method includes S170 , in the process of S400 , the portion of the second isolation film 660 covering the bottom wall of the first trench 520 and the second trench 530 is further removed.

[0191] S500: See Fig. 22 , a second insulating layer 434 is formed in the second sub-groove 531 .

[0192] In the above steps, after removing the remaining first sacrificial layer 610, the second sub-groove 531 is formed. That is, the second sub-groove 531 is a gap formed after removing the first sacrificial layer 610. The second insulating layer 434 can be formed by first depositing an insulating material using a thin film deposition process, and then removing the portion covering the semiconductor layer 513 using a dry or wet etching process.

[0193] In some embodiments, see Fig.17 Before S400, the preparation method further includes S600 to S700.

[0194] S600: See Fig. 20 and Fig. 22 , remove the second sacrificial layer 620 and form a second trench 530 .

[0195] In the above steps, the second sacrificial layer 620 may be removed by, for example, a dry or wet etching process.

[0196] In the case where the above preparation method includes S140, before removing the second sacrificial layer 620, the second mask layer 640 is first removed to expose the second sacrificial layer 620. The second mask layer 640 can be removed by, for example, a chemical mechanical polishing process, and in the process of removing the second mask layer 640, the portion of the first insulating layer 433 located in the opening of the second mask layer 640 can also be removed.

[0197] S700: See Fig. 20 and Fig. 22 , a gate structure 420 is formed in the second trench 530 .

[0198] In the above steps, the gate structure 420 may include, for example, a gate layer 421 , a gate dielectric layer 422 and an insulating structure 423 . The insulating structure 423 may include, for example, a first insulating portion 4230 and a second insulating portion 4240 .

[0199] In some embodiments, see Fig.18 , S700 includes S710~S720.

[0200] S710: See Fig. 20 and Fig. 22 , a second insulating portion 4240 is formed in the second trench 530 .

[0201] In the above steps, the second insulating portion 4240 may be formed by, for example, depositing an insulating material using a deposition process, and then removing a portion covering the sidewall of the second trench 530 using a dry or wet etching process.

[0202] S720: See Fig. 20 and Fig. 22 A gate dielectric film 422 ′, a gate layer 421 and an insulating filling film 4230 ′ are sequentially formed in the second trench 530 , and portions of the gate dielectric film 422 ′ and the insulating filling film 4230 ′ located in the semiconductor layer 513 away from the substrate 510 are removed.

[0203] In the above steps, the gate dielectric film 422' and the insulating filling film 4230' can be formed, for example, by a deposition process. The gate layer 421 can, for example, first deposit a conductive material by a deposition process, and then remove the portion covering the bottom wall of the second trench 530, the portion located in the semiconductor layer 513 away from the substrate 510, and the portion covering the sidewall of the second trench 530 away from the substrate 510 by a dry or wet etching process.

[0204] In addition, the gate dielectric film 422' and the insulating filling film 4230' located in the semiconductor layer 513 away from the substrate 510 can be removed by, for example, any one of a dry etching process, a wet etching process, or a planarization process. For example, the gate dielectric film 422' and the insulating filling film 4230' located in the semiconductor layer 513 away from the substrate 510 can be removed simultaneously by chemical mechanical polishing.

[0205] In the case where the above-mentioned preparation method includes S160, in the process of removing the gate dielectric film 422' and the insulating filling film 4230' located at the portion of the semiconductor layer 513 away from the substrate 510, the first isolation film 650 may also be removed. In the case where the above-mentioned preparation method includes S120, in the process of removing the gate dielectric film 422' and the insulating filling film 4230' located at the portion of the semiconductor layer 513 away from the substrate 510, the first mask layer 630 and the portion of the first insulating layer 433 located in the opening of the first mask layer 630 may also be removed.

[0206] Fig.24 is a block diagram of a storage system according to some embodiments. Fig.25 is a block diagram of a storage system according to some other embodiments.

[0207] See also Fig.24 and Fig.25 Some embodiments of the present disclosure further provide a storage system 1000. The storage system 1000 includes a controller 20 and a memory 10 according to some embodiments above. The controller 20 is coupled to the memory 10 to control the memory 10 to store data.

[0208] The storage system 1000 may be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an Embedded Multi Media Card (eMMC) package). That is, the storage system 1000 may be applied to and packaged into different types of electronic products, for example, mobile phones (e.g., cell phones), desktop computers, tablet computers, laptop computers, servers, vehicle-mounted devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices having storage therein.

[0209] In some embodiments, see Fig.24, the storage system 1000 includes a controller 20 and a memory 10, and the storage system 1000 can be integrated into a memory card.

[0210] Among them, the memory card includes any one of PC card (PCMCIA, Personal Computer Memory Card International Association), Compact Flash (CF) card, Smart Media (SM) card, memory stick, Multimedia Card (MMC), Secure Digital (SD) card, and UFS.

[0211] In other embodiments, see Fig.25 The storage system 1000 includes a controller 20 and a plurality of memories 10, and the storage system 1000 is integrated into a solid state drive (SSD).

[0212] In the storage system 1000, in some embodiments, the controller 20 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones.

[0213] In other embodiments, the controller 20 is configured to operate in a high duty cycle environment SSD or eMMC used for data storage in mobile devices such as smartphones, tablets, notebooks, and enterprise storage arrays.

[0214] In some embodiments, the controller 20 may be configured to manage data stored in the memory 10 and communicate with an external device (e.g., a host). In some embodiments, the controller 20 may also be configured to control operations of the memory 10, such as read, erase, and program operations. In some embodiments, the controller 20 may also be configured to manage various functions regarding data stored or to be stored in the memory 10, including at least one of bad block management, garbage collection, logical to physical address conversion, and wear leveling. In some embodiments, the controller 20 is also configured to process error correction codes regarding data read from or written to the memory 10.

[0215] Of course, the controller 20 may also perform any other suitable functions, such as formatting the memory 10; for example, the controller 20 may communicate with an external device (eg, a host) via at least one of various interface protocols.

[0216] It should be noted that the interface protocol includes at least one of the USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer interface (SCSI) protocol, enhanced minidisk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, and Firewire protocol.

[0217] Some embodiments of the present disclosure also provide an electronic device. The electronic device may be any one of a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc.

[0218] The electronic device may include the storage system 1000 described above, and may also include at least one of a central processing unit (CPU) and a cache.

[0219] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that: include: A plurality of active pillars are arranged in an array along a first direction and a second direction, wherein the first direction and the second direction intersect; A gate structure extending along the first direction and located between two adjacent rows of active pillars; An isolation structure extending along the first direction and located between two adjacent rows of active pillars; Wherein, the isolation structure and the gate structure are alternately arranged in the second direction and are respectively located on two opposite sides of the active column; The isolation structure includes a shielding layer, a first dielectric layer and a first insulating layer. Along a third direction, the first insulating layer is located on one side of the shielding layer, and the first dielectric layer is at least partially located on the other side of the shielding layer away from the first insulating layer; the first direction and the second direction are both perpendicular to the third direction.

2. The semiconductor structure according to claim 1, characterized in that: The first dielectric layer comprises: A first portion is located at a side of the shielding layer away from the first insulating layer; The second portion is located between the shielding layer and the active pillar, and between the first insulating layer and the active pillar.

3. The semiconductor structure according to claim 2, characterized in that: The thickness of the second portion is greater than or equal to the thickness of the first portion.

4. The semiconductor structure according to claim 2, characterized in that: The isolation structure also includes: The second insulating layer is arranged on a side of the first portion away from the first insulating layer.

5. The semiconductor structure according to claim 4, characterized in that: The isolation structure also includes: The first isolation layer is located between the first dielectric layer and the active pillar, and between the second insulating layer and the active pillar.

6. The semiconductor structure according to claim 5, characterized in that: The first isolation layer and the first dielectric layer are made of the same material.

7. The semiconductor structure according to claim 1, characterized in that: The material of the first dielectric layer includes at least one of silicon oxide, silicon nitride, silicon oxynitride and aluminum oxide.

8. The semiconductor structure according to any one of claims 1 to 7, characterized in that: The gate structure comprises: a gate layer extending along the first direction and disposed on a sidewall of the active column; A gate dielectric layer, disposed between the gate layer and the corresponding active column; The insulating structure at least covers two ends of the gate layer in the third direction.

9. The semiconductor structure according to claim 8, characterized in that: The insulating structure comprises: A first insulating portion, comprising a third portion and a fourth portion; along the second direction, the third portion is located between gate layers in the same gate structure; along the third direction, the fourth portion covers the gate layer and one end of the third portion, and is located between gate dielectric layers in the same gate structure; The second insulating portion is disposed between two adjacent active pillars; along the third direction, the second insulating portion covers the gate layer, the gate dielectric layer and the other end of the third portion away from the fourth portion.

10. The semiconductor structure according to claim 9, characterized in that: The gate structure further includes a second isolation layer, wherein the second isolation layer is located between the gate dielectric layer and the active pillar, and between the second insulating portion and the active pillar.

11. The semiconductor structure according to claim 8, characterized in that: The orthographic projection of the shielding layer on the reference plane at least partially overlaps with the orthographic projection of the adjacent gate layer on the reference plane; the reference plane is perpendicular to the second direction.

12. The semiconductor structure according to claim 11, characterized in that: The orthographic projection of the shielding layer on the reference plane is located within the range of the orthographic projection of any adjacent gate layer on the reference plane.

13. A method for preparing a semiconductor structure, characterized in that: include: An intermediate semiconductor structure is formed; the intermediate semiconductor structure comprises a substrate, a first sacrificial layer and a second sacrificial layer; the substrate comprises a base and a plurality of active pillars disposed on the base, the plurality of active pillars are arranged in an array along a first direction and a second direction, the first direction intersects the second direction; the first sacrificial layer and the second sacrificial layer are alternately arranged in the second direction and are respectively located between two adjacent rows of active pillars; removing a portion of the first sacrificial layer to form a first sub-groove; An isolation structure is formed in the first sub-groove; the isolation structure comprises a shielding layer and a first dielectric layer, and the first dielectric layer is at least located between the shielding layer and the remaining first sacrificial layer.

14. The preparation method according to claim 13, characterized in that: The forming of the isolation structure in the first sub-groove comprises: forming a first dielectric layer in the first sub-groove; the first dielectric layer covers the bottom wall and side walls of the first sub-groove; A shielding layer is formed in the first sub-groove.

15. The preparation method according to claim 14, characterized in that: After forming the shielding layer in the first sub-slot, forming the isolation structure in the first sub-slot further includes: A first insulating layer is formed in the first sub-groove.

16. The preparation method according to claim 13, characterized in that: After forming the isolation structure in the first sub-groove, the preparation method further includes: removing the substrate and the remaining first sacrificial layer in sequence until the first dielectric layer is exposed; removing the remaining first sacrificial layer to form a second sub-groove; A second insulating layer is formed in the second sub-groove.

17. The preparation method according to any one of claims 13 to 16, characterized in that: Also includes: removing the second sacrificial layer to form a second trench; A gate structure is formed in the second trench.

18. The preparation method according to any one of claims 13 to 16, characterized in that: The forming of the intermediate semiconductor structure comprises: Prepare a substrate; the substrate comprises a first trench and a second trench extending along the first direction, the first trench and the second trench are alternately arranged in the second direction and are respectively located between two adjacent rows of active pillars; forming a first mask layer on the substrate; the first mask layer covers a side of the active pillar away from the base and exposes the first trench and the second trench; forming a second sacrificial layer in the first trench and the second trench; forming a second mask layer on a side of the second sacrificial layer and the first mask layer away from the substrate; the second mask layer is located on a side of the first mask layer away from the substrate, at least covers the second sacrificial layer located in the second groove, and exposes the second sacrificial layer located in the first groove; The second sacrificial layer in the first trench is removed, and a first sacrificial layer is formed in the first trench.

19. The preparation method according to claim 18, characterized in that: In the process of removing the second sacrificial layer located in the first groove, part of the first mask layer is also removed, so that the width of the first groove at one end away from the substrate in the second direction is greater than the width of the first groove at one end close to the substrate in the second direction.

20. The preparation method according to claim 18, characterized in that: Before forming the first mask layer on the substrate, forming the intermediate semiconductor structure further comprises: forming a first isolation film on the substrate; the first isolation film covers the sidewalls and bottom walls of the first trench and the second trench; and / or, Between forming a first mask layer on the substrate and forming a second sacrificial layer in the first trench and the second trench, forming the intermediate semiconductor structure further comprises: A second isolation film is formed in the first trench and the second trench; the second isolation film covers the sidewalls and bottom walls of the first trench and the second trench.

21. The preparation method according to claim 18, characterized in that: Materials of the first sacrificial layer and the second sacrificial layer include titanium nitride and / or soluble organic carbon.

22. A storage system, characterized in that: include: A memory, comprising a semiconductor structure as claimed in any one of claims 1 to 12; The controller is coupled to the memory to control the memory to store data.

Images