Manufacturing method of ETOX NOR type flash memory device

Abstract

The invention provides a manufacturing method of an ETOX NOR type flash memory device, which comprises the following steps of: providing a substrate, and forming a pad oxide layer and a hard mask layer on the surface of the substrate; manufacturing a shallow trench isolation structure on the substrate; performing ion implantation to form a deep N well and a high-voltage N well in the substrate; etching to remove the pad oxide layer, and forming a tunneling oxide layer, a floating gate layer, an ONO layer and a control gate layer on the surface of the substrate; etching to form a control gate structure and a floating gate structure; executing a lightly doped drain injection process to form a lightly doped drain region in the substrate; executing a self-aligned source electrode ion implantation process to form a self-aligned source electrode P-type bag-shaped doped region and a self-aligned source electrode N-type heavily doped region in the substrate; forming a side wall; and forming a source electrode and a drain electrode. According to the invention, the threshold voltage adjustment injection originally carried out after the high-voltage N well is adjusted to be combined with the self-aligned source injection in the subsequent process, so that the threshold voltage adjustment injection photomask is omitted under the condition that the performance of the device is not influenced, and the purposes of reducing the process cost and improving the product competitiveness are achieved.

Description

Technical Field

[0001] The invention relates to the technical field of semiconductor manufacturing, and in particular to a method for manufacturing an ETOX NOR type flash memory device. Background Art

[0002] The threshold voltage (Vt) is one of the main performance parameters of transistors. Generally, the threshold voltage depends on a variety of device materials and process parameters, such as substrate doping concentration, gate electrode material, gate dielectric material and thickness, dielectric and interface charge density, etc. However, when the gate dielectric and electrode materials and process conditions are determined, the only parameter that can adjust the device threshold voltage is the substrate doping concentration, that is, the well region doping. Research results show that the impurity concentration in the depletion region under the gate dielectric is the main factor affecting the threshold voltage. In the device manufacturing process, the threshold voltage adjustment injection (Vtadjust implant) method is usually used to achieve the purpose of adjusting the threshold voltage. For N-type devices, that is, after the well ion implantation, a P-type impurity is implanted so that the transistor surface has a suitable P-type impurity concentration distribution and the expected threshold voltage is obtained.

[0003] 4X ETOX (EPROM with Tunnel Oxid) NOR flash memory is reducing the number of plates to improve product competitiveness. Considering that the CVT (Cell Vtadjust) implant requires a separate photolithography plate for CVT ion implantation, and this ion implantation is only to increase the impurity concentration at the device channel to obtain the expected threshold voltage, in order to save costs, this photolithography is attempted to be omitted and this implantation is attempted to be combined with other boron implants. Summary of the invention

[0004] In view of this, the present invention provides a method for manufacturing an ETOX NOR flash memory device, so as to improve the competitiveness of the product and achieve the purpose of saving the number of versions without affecting the threshold voltage of the device.

[0005] The present invention provides a method for manufacturing an ETOX NOR flash memory device, comprising the following steps:

[0006] Step 1, providing a substrate, wherein a pad oxide layer and a hard mask layer are formed on the surface of the substrate;

[0007] Step 2: fabricating a shallow trench isolation structure on the substrate;

[0008] Step 3: Perform ion implantation to form a deep N-well and a high-voltage N-well in the substrate;

[0009] Step 4: etching and removing the pad oxide layer to form a stack on the surface of the substrate, the stack from bottom to top including a tunneling oxide layer, a floating gate layer, an ONO layer and a control gate layer;

[0010] Step 5: etching the stack to form a control gate and a floating gate structure;

[0011] Step 6: performing a lightly doped drain implantation process to form a lightly doped drain region in the substrate;

[0012] Step 7: Perform a self-aligned source ion implantation process to form a self-aligned source implantation region in the substrate, wherein the self-aligned source implantation region includes a self-aligned source P-type pocket doping region and a self-aligned source N-type heavily doped region;

[0013] Step eight, making a sidewall, wherein the sidewall covers the self-aligned source injection region;

[0014] Step nine: perform source and drain ion implantation to form a source and a drain.

[0015] Preferably, the substrate in step one is a silicon substrate.

[0016] Preferably, the material of the hard mask layer in step 1 is silicon nitride.

[0017] Preferably, step 2 comprises: defining an active area by means of a photomask, dry etching the hard mask layer, the pad oxide layer and the substrate to form shallow trench isolation, filling with silicon dioxide, and removing the hard mask layer after smoothing by chemical mechanical polishing.

[0018] Preferably, in step three, the high-voltage N-well is located above the deep N-well.

[0019] Preferably, in step 4, the material of the floating gate layer and the control gate layer is polysilicon.

[0020] Preferably, the ONO layer in step 4 is a three-layer stacked structure, including a silicon oxide layer, a silicon nitride layer and a silicon oxide layer.

[0021] Preferably, the etching in step five is a dry etching process.

[0022] Preferably, in step seven, the self-aligned source P-type pocket doped region surrounds the self-aligned source N-type heavily doped region.

[0023] Preferably, the material of the sidewall in step eight is an ONO layer.

[0024] Usually, in the integration process of ETOX NOR Flash devices, a separate mask is required for CVT ion implantation. In order to reduce the process cost, the present invention combines the CVT implantation step into the SAS (Self Aligned Source) implantation, thereby eliminating a mask. Under the premise of not affecting other devices and other performances of the flash, the expected threshold voltage is obtained, thereby achieving the purpose of eliminating the CVT mask and not affecting the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0026] Figure 1 A flowchart showing a method for manufacturing an ETOX NOR flash memory device according to an embodiment of the present invention;

[0027] Figures 2 to 8 It is a structural schematic diagram showing each step of a method for manufacturing a NOR flash memory device according to an embodiment of the present invention;

[0028] Fig. 9 Shown is a comparison table of simulation results of the threshold voltage of devices formed by the existing process and the method of the embodiment of the present invention.

[0029] The following are the descriptions of the reference numerals:

[0030] 101-substrate, 102-pad oxide layer, 103-tunneling oxide layer, 104-floating gate layer, 105-ONO layer, 106-control gate layer, 107-lightly doped drain region, 108-deep N well (DNW), 109-high voltage N well (HVNW), 110-1 self-aligned source P-type pocket doped region, 110-2 self-aligned source N-type heavily doped region, 1111-sidewall, 112-source and drain S / D, 501-hard mask layer. DETAILED DESCRIPTION

[0031] The present invention is described below based on embodiments, but the present invention is not limited to these embodiments. In the detailed description of the present invention below, some specific details are described in detail. It is possible for a person skilled in the art to fully understand the present invention without the description of these details. In order to avoid confusing the essence of the present invention, known methods, processes, flows, components and circuits are not described in detail.

[0032] In addition, persons of ordinary skill in the art will appreciate that the drawings provided herein are for illustration purposes and are not necessarily drawn to scale.

[0033] Unless the context clearly requires otherwise, the words "include", "comprising" and similar words throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, the meaning is "including but not limited to".

[0034] In the description of the present invention, it should be understood that the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, "plurality" means two or more.

[0035] Considering the boron injection of 4X Etox Nor Flash, cell devices, only HVPW and SAS (Self Aligned Source) contain boron injection. However, changes in HVPW injection will also have corresponding effects on other devices, and SAS injection is only a process step performed on the flash area. Therefore, it was decided to concentrate the pocket (halo / pocket) injection of SAS and adjust the injection process parameters to obtain the expected threshold voltage without affecting other devices and other flash performances, thereby achieving the effect of adjusting the threshold voltage. Therefore, the present invention proposes a method for manufacturing an ETOX NOR flash memory device, which is used to achieve the purpose of eliminating the threshold voltage adjustment injection (Vt adjust implant, CVT) mask without affecting the device. The technical solution of the present invention is further illustrated below in conjunction with the accompanying drawings and through specific implementation methods.

[0036] Figure 1 FIG. 4 is a flow chart showing a method for manufacturing an ETOX NOR flash memory device according to an embodiment of the present invention. Figures 2 to 8 The structure diagram of each step of the method for manufacturing a NOR flash memory device according to an embodiment of the present invention is shown. Figure 1 As shown, the method for manufacturing the ETOX NOR flash memory device according to the embodiment of the present invention comprises the following steps:

[0037] Step 1: Figure 2 As shown, a substrate is provided, and a pad oxide layer and a hard mask layer are formed on the surface of the substrate.

[0038] The material of the substrate 101 may be silicon, germanium, silicon germanium or silicon carbide, etc., or may be silicon on insulator (SOI) or germanium on insulator (GOI), or may be other materials, such as III and V group compounds such as gallium arsenide, and further, it may be an undoped or lightly doped silicon substrate. In an embodiment of the present invention, the substrate 101 is a silicon substrate, and further, it is a P-type silicon substrate. The material of the pad oxide layer 102 is silicon oxide, and the material of the hard mask layer 501 is silicon nitride. Typically, the thickness of the silicon nitride hard mask layer 501 is relatively large, which is convenient for the subsequent planarization process.

[0039] Step 2: Figure 3 As shown, a shallow trench isolation structure is fabricated on a substrate.

[0040] In the embodiment of the present invention, step 2 includes: defining the active area by photomask, dry etching the hard mask layer 501, the pad oxide layer 102 and the substrate 101 to form shallow trench isolation, HDP filling silicon dioxide, and removing the hard mask layer 501 after being polished by chemical mechanical polishing (CMP). Of course, it also includes process steps such as removing photoresist and high temperature annealing, which will not be repeated here. Wet etching or other suitable methods can be used to remove the hard mask layer 501.

[0041] Step 3: Figure 3 As shown, ion implantation is performed to form a deep N well and a high-voltage N well in the substrate.

[0042] The impurity ions implanted by ion implantation may be P-type impurity ions or N-type impurity ions. The N-type impurity ions are one or more of phosphorus ions, arsenic ions, and antimony ions, and the P-type impurity ions are one or more of boron ions, gallium ions, or indium ions. In the embodiment of the present invention, N-type impurity ions are implanted in the substrate 101, and after the implantation, the well is pushed at high temperature to form a deep N well (DNW) 108 and a high voltage N well (HVNW) 109, and the high voltage N well 109 is located above the deep N well 108.

[0043] Step 4: Figure 4 As shown, the pad oxide layer is removed by etching to form a stacked layer on the surface of the substrate, and the stacked layer includes a tunneling oxide layer, a floating gate layer, an ONO layer and a control gate layer from bottom to top.

[0044] Etching to remove the pad oxide layer can adopt dry or wet etching process. Preferably, in the embodiment of the present invention, wet etching is adopted to remove the pad oxide, such as HF solution. A tunneling oxide layer 103, a floating gate layer 104, an ONO layer 105 and a control gate layer 106 are sequentially formed on the surface of the substrate. The ONO layer is a three-layer stacked structure, including a silicon oxide layer, a silicon nitride layer and a silicon oxide layer ONO layer, and is formed by a low-pressure chemical vapor deposition method. The material of the tunneling oxide layer 103 is silicon oxide, and the material of the floating gate layer 104 and the control gate layer 106 is polysilicon.

[0045] Step 5: Figure 5 As shown, the stack is etched to form a control gate and a floating gate structure.

[0046] A photoresist layer is formed on the control gate layer 106, a photoresist pattern is defined, and the control gate layer 105, the ONO layer 105, the floating gate layer 104, and the tunnel oxide layer 103 are etched to form a control gate structure and a floating gate structure. In the embodiment of the present invention, a dry etching process is used to etch the control gate layer 105, the ONO layer 105, the floating gate layer 104, and the tunnel oxide layer 103. The dry etching process includes, but is not limited to, reactive ion etching (RIE), ion beam etching, plasma etching, or laser cutting.

[0047] Step six: performing a lightly doped drain implantation process to form a lightly doped drain region in the substrate.

[0048] The embodiment of the present invention does not specifically describe the process conditions of the lightly doped ion implantation process (CLDD ion implantation process), such as the implantation angle, implantation energy, and implantation dose, which are set according to actual needs. Figure 6 As shown, a lightly doped drain region 107 is formed by performing a lightly doped drain implantation process in the substrate.

[0049] Step seven: perform a self-aligned source ion implantation process to form a self-aligned source implantation region in the substrate, wherein the self-aligned source implantation region includes a self-aligned source P-type pocket doping region and a self-aligned source N-type heavily doped region.

[0050] Usually, during the integration process of ETOX NOR Flash devices, a separate mask is required for CVT ion implantation. In the embodiment of the present invention, the CVT implantation step is merged into the SAS (Self Aligned Source) implantation. By using the SAS implantation mask, the SAS implantation pocket is implanted and concentrated, so that the device threshold voltage matches the device threshold voltage that does not change, thereby achieving the effect of adjusting the threshold voltage. Figure 7 As shown, a self-aligned source P-type pocket doping region 110-1 and a self-aligned source N-type heavily doped region 110-2 are formed in the substrate. The self-aligned source P-type pocket doping region 110-1 surrounds the self-aligned source N-type heavily doped region 110-2.

[0051] Step 8: Make sidewalls, which cover the self-aligned source injection area.

[0052] In the embodiment of the present invention, the material of the sidewall is an ONO layer, and the ONO layer is deposited and etched to form the sidewall 111. Figure 7 As shown, a spacer 111 is formed on the sidewalls of the control gate structure and the floating gate structure, and the spacer 111 between the gate structures will completely cover the self-aligned source (SAS) implantation region.

[0053] Step nine: perform source and drain ion implantation to form a source and a drain.

[0054] like Figure 8 As shown, source and drain ion implantation is performed to form source and drain S / D112.

[0055] Fig. 9 The table shows the comparison of the simulation results of the threshold voltage of the device formed by the existing process and the method of the embodiment of the present invention. Fig. 9 As shown, after skipping the CVT injection, the Vt of the device drops from 1.609V to 0.212V, a drop of nearly 90%. However, by adopting the method of the embodiment of the present invention, CVT lithography and injection are omitted, and the SAS injection mask is used to concentrate the pocket injection of the SAS injection, so as to achieve the effect of adjusting the threshold voltage. The final device Vt reaches 1.616V. Compared with the baseline value of 1.609V, the deviation is less than 0.5%, and it can be considered that there is no deviation. In other words, the process steps of the embodiment of the present invention can make the device Vt match the baseline value, and the impact on other performance of the device is very small.

[0056] In summary, the present invention adjusts the CVT injection originally performed after the HVNW is formed to be combined with the SAS injection in the subsequent process, thereby eliminating the CVT mask without affecting the device performance and threshold voltage, thereby achieving the purpose of reducing process costs and improving product competitiveness.

[0057] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A method for manufacturing an ETOX NOR flash memory device, characterized in that: The following steps are involved: Step 1, providing a substrate, wherein a pad oxide layer and a hard mask layer are formed on the surface of the substrate; Step 2: fabricating a shallow trench isolation structure on the substrate; Step 3: Perform ion implantation to form a deep N-well and a high-voltage N-well in the substrate; Step 4: etching and removing the pad oxide layer to form a stack on the surface of the substrate, the stack from bottom to top including a tunneling oxide layer, a floating gate layer, an ONO layer and a control gate layer; Step 5: etching the stack to form a control gate and a floating gate structure; Step 6: performing a lightly doped drain implantation process to form a lightly doped drain region in the substrate; Step 7: Perform a self-aligned source ion implantation process to form a self-aligned source implantation region in the substrate, wherein the self-aligned source implantation region includes a self-aligned source P-type pocket doping region and a self-aligned source N-type heavily doped region; Step eight, making a sidewall, wherein the sidewall covers the self-aligned source injection region; Step nine: perform source and drain ion implantation to form a source and a drain.

2. The method for manufacturing the ETOX NOR flash memory device according to claim 1, characterized in that: The substrate in step 1 is a silicon substrate.

3. The method for manufacturing the ETOX NOR flash memory device according to claim 1, characterized in that: The material of the hard mask layer in step 1 is silicon nitride.

4. The method for manufacturing the ETOX NOR flash memory device according to claim 1, characterized in that: Step 2 includes: defining the active area by photomask, dry etching the hard mask layer, the pad oxide layer and the substrate to form shallow trench isolation, filling with silicon dioxide, and removing the hard mask layer after chemical mechanical polishing.

5. The method for manufacturing the ETOX NOR flash memory device according to claim 1, characterized in that: In step three, the high-voltage N-well is located above the deep N-well.

6. The method for manufacturing the ETOX NOR flash memory device according to claim 1, characterized in that: In step 4, the material of the floating gate layer and the control gate layer is polysilicon.

7. The method for manufacturing the ETOX NOR flash memory device according to claim 1, characterized in that: The ONO layer in step 4 is a three-layer stacked structure, including a silicon oxide layer, a silicon nitride layer and a silicon oxide layer.

8. The method for manufacturing the ETOX NOR flash memory device according to claim 1, characterized in that: The etching in step five is a dry etching process.

9. The method for manufacturing the ETOX NOR flash memory device according to claim 1, characterized in that: The self-aligned source P-type pocket doped region in step seven surrounds the self-aligned source N-type heavily doped region.

10. The method for manufacturing the ETOX NOR flash memory device according to claim 1, characterized in that: The material of the side wall in step eight is an ONO layer.

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