Novel shield gate MOSFET structure, preparation method thereof and chip

Abstract

The invention belongs to the technical field of power devices, and provides a novel shield gate MOSFET structure, a preparation method thereof and a chip, a composite dielectric material layer and a shield gate polycrystalline silicon layer are arranged in a groove of an N-type drift region, the composite dielectric material layer isolates the shield gate polycrystalline silicon layer from the bottom and two side walls of the groove of the N-type drift region, and in addition, the shield gate polycrystalline silicon layer is separated from the bottom and two side walls of the groove of the N-type drift region. The composite dielectric material layer comprises a first dielectric material layer and a second dielectric material layer, the first dielectric material layer is in contact with the N-type drift region, the first dielectric material layer with a lower dielectric constant is arranged on one side close to the N-type drift region, and the second dielectric material layer with a higher dielectric constant is arranged on one side close to the shield gate polycrystalline silicon layer. By utilizing the high dielectric constant characteristic of the second dielectric material layer, the same auxiliary depletion effect can be achieved under the condition that the shield gate oxide layer is thicker, so that the breakdown voltage of the bottom of the shield gate is enhanced, and meanwhile, due to the approximate auxiliary depletion effect, the influence on the on-resistance of the device is relatively low.

Description

Technical Field

[0001] The present application belongs to the technical field of power devices, and in particular, relates to a novel shielded gate MOSFET structure and a preparation method and chip thereof. Background Art

[0002] Shielded gate MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor, SJMOSFET) has the advantages of low internal resistance, large saturation current, strong output capability and low power consumption. It is widely used in digital circuits, analog circuits, power management, radio frequency applications and other fields.

[0003] Existing shielded gate MOSFETs usually use silicon dioxide (SiO2) as the gate oxide layer of the shielded gate. This design can improve the device's withstand voltage strength to a certain extent, but due to the physical characteristics of silicon dioxide's low dielectric constant, the thickness of the gate oxide layer of the shielded gate cannot be too thick, otherwise the shielded gate cannot deplete the drift region, and although a thin SiO2 layer can achieve a better auxiliary depletion effect, it will cause the thin SiO2 of the device to break down. In summary, the above two points lead to a low breakdown voltage of the device. Summary of the invention

[0004] In order to solve the above technical problems, the embodiments of the present application provide a new shielded gate MOSFET structure and a preparation method and chip thereof, which can improve the breakdown voltage of the new shielded gate MOSFET structure device.

[0005] A first aspect of an embodiment of the present application provides a novel shielded gate MOSFET structure, comprising: N-type substrate; An N-type drift region, wherein the N-type drift region is a concave structure; A composite dielectric material layer and a shielding gate polysilicon layer, wherein the composite dielectric material layer is used to isolate the shielding gate polysilicon layer from the bottom and two side walls of the N-type drift region groove; wherein the composite dielectric material layer comprises a first dielectric material layer and a second dielectric material layer, the dielectric constant of the first dielectric material layer is smaller than the dielectric constant of the second dielectric material layer, and the first dielectric material layer is in contact with the N-type drift region; A gate dielectric material layer and a control gate polysilicon layer, wherein the gate dielectric material layer is disposed in the groove of the N-type drift region, and the gate dielectric material layer wraps the control gate polysilicon layer; A first P-type base region and a second P-type base region, wherein the first P-type base region and the second P-type base region are in an L-shaped structure and are respectively arranged at two sides of the N-type drift region; a first N-type doping region and a second N-type doping region, wherein the first N-type doping region is located on a horizontal portion of the first P-type base region of the L-shaped structure and contacts the gate dielectric material layer, and the second N-type doping region is located on a horizontal portion of the second P-type base region of the L-shaped structure and contacts the gate dielectric material layer; a source layer, contacting the first N-type doping region, the second N-type doping region, the first P-type base region and the second P-type base region, and contacting the shield gate polysilicon layer; A drain layer is disposed on the back side of the N-type substrate.

[0006] In some embodiments, the gate dielectric material layer is located on the upper side of the first dielectric material layer, the second dielectric material layer and the shielding gate polysilicon layer, the bottom of the gate dielectric material layer and the first dielectric material layer form a closed cavity, and the shielding gate polysilicon layer and the second dielectric material layer are located in the closed cavity.

[0007] In some embodiments, the first dielectric material layer and the gate dielectric material layer are made of the same material.

[0008] In some embodiments, the first dielectric material layer and the gate dielectric material layer are silicon dioxide; and the second dielectric material layer is hafnium dioxide.

[0009] In some embodiments, the composite dielectric material layer further includes: a third dielectric material layer, the third dielectric material layer is disposed between the second dielectric material layer and the shielding gate polysilicon layer, and the dielectric constant of the third dielectric material layer is greater than or equal to the dielectric constant of the first dielectric material layer.

[0010] In some embodiments, the shielding gate polysilicon layer is a stepped structure, and the width of the shielding gate polysilicon layer gradually increases from the drain layer to the source layer.

[0011] In some embodiments, the thickness of the second dielectric material layer gradually decreases from the drain layer to the source layer.

[0012] In some embodiments, the first dielectric material layer and the second dielectric material layer are in a stepped structure.

[0013] A second aspect of the embodiment of the present application further provides a method for preparing a novel shielded gate MOSFET structure, the method comprising: Epitaxially forming an N-type drift layer on the front side of the N-type substrate; Forming a first deep trench in the central region of the N-type drift layer by etching, and forming an N-type drift region with a concave structure; A composite dielectric material layer is formed after a first dielectric material layer and a second dielectric material layer are sequentially formed along the inner wall of the N-type drift region, and a shielding gate polysilicon layer is formed in the groove of the composite dielectric material layer; wherein the composite dielectric material layer is used to isolate the shielding gate polysilicon layer from the bottom and two side walls of the groove of the N-type drift region, the dielectric constant of the first dielectric material layer is smaller than the dielectric constant of the second dielectric material layer, and the first dielectric material layer is in contact with the N-type drift region; A concave gate dielectric material layer is formed in the first deep groove, and is filled with a polysilicon layer material to obtain a control gate polysilicon layer; the gate dielectric material layer wraps the control gate polysilicon layer; Implanting P-type doping ions into the side of the N-type drift region to form a first P-type base region and a second P-type base region, wherein the first P-type base region and the second P-type base region are respectively arranged on both sides of the N-type drift region; Implanting N-type doping ions into partial regions of the first P-type base region and the second P-type base region to form a first N-type doping region and a second N-type doping region, and making the first P-type base region and the second P-type base region present an L-shaped structure, wherein the first N-type doping region is located on a horizontal portion of the first P-type base region of the L-shaped structure and contacts the gate dielectric material layer, and the second N-type doping region is located on a horizontal portion of the second P-type base region of the L-shaped structure and contacts the gate dielectric material layer; forming a source layer in contact with the first N-type doping region, the second N-type doping region, the first P-type base region and the second P-type base region, and in contact with the shield gate polysilicon layer; A drain layer is formed on the back side of the N-type substrate.

[0014] A third aspect of the embodiments of the present application further provides a chip, comprising the novel shielded gate MOSFET structure as described in any of the above embodiments.

[0015] The beneficial effects of the embodiments of the present application are as follows: by arranging a composite dielectric material layer and a shielding gate polysilicon layer in the groove of the N-type drift region, the shielding gate polysilicon layer is isolated from the bottom and two side walls of the groove of the N-type drift region by the composite dielectric material layer, and the composite dielectric material layer includes a first dielectric material layer and a second dielectric material layer, the first dielectric material layer is in contact with the N-type drift region, by arranging a first dielectric material layer with a lower dielectric constant on the side close to the N-type drift region, and arranging a second dielectric material layer with a higher dielectric constant on the side close to the shielding gate polysilicon layer, by utilizing the high dielectric constant characteristics of the second dielectric material layer, the same auxiliary depletion effect can be achieved with a thicker shielding gate oxide layer, thereby enhancing the breakdown voltage at the bottom of the shielding gate, and at the same time, due to the proximity of the auxiliary depletion effect, the impact on the on-resistance of the device is low. The novel shielding gate MOSFET structure proposed in the present application is realized to optimize the breakdown voltage of the device without changing the trench width and platform width of the device, and will not increase the design cost of the shielding gate device. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a first structural schematic diagram of a novel shielded gate MOSFET structure provided in an embodiment of the present application; Figure 2 is a second structural schematic diagram of the novel shielded gate MOSFET structure provided in an embodiment of the present application; Figure 3 is a third structural schematic diagram of the novel shielded gate MOSFET structure provided in an embodiment of the present application; Figure 4 is a fourth structural schematic diagram of the novel shielded gate MOSFET structure provided in an embodiment of the present application; Figure 5 A comparison diagram of output characteristic curve simulation results of the comparative structure 1, comparative structure 2 and improved structure provided in the embodiments of the present application; Figure 6 A comparison chart of breakdown voltage simulation results of the comparative structure 1, comparative structure 2 and improved structure provided in the embodiments of the present application; Figure 7 It is a schematic flow chart of a method for preparing a novel shielded gate MOSFET structure provided in an embodiment of the present application; Figure 8 is a schematic diagram of forming an N-type drift layer on an N-type substrate layer provided by an embodiment of the present application; Fig. 9 is a schematic diagram of forming an N-type drift region provided in an embodiment of the present application; Fig.10 is a schematic diagram of forming a first dielectric material layer in a first deep trench provided by an embodiment of the present application; Fig.11is a schematic diagram of forming a second dielectric material layer provided in an embodiment of the present application; Fig.12 is a first schematic diagram of forming a shield gate polysilicon layer provided by an embodiment of the present application; Fig.13 is a second schematic diagram of forming a shield gate polysilicon layer provided in an embodiment of the present application; Fig.14 is a schematic diagram of forming a gate dielectric material layer provided by an embodiment of the present application; Fig.15 is a schematic diagram of forming a control gate polysilicon layer provided in an embodiment of the present application; Fig.16 It is a schematic diagram of forming a first P-type base region, a second P-type base region, a first N-type doping region, and a second N-type doping region provided in an embodiment of the present application. DETAILED DESCRIPTION

[0017] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0018] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0019] It should be understood that the orientation or position relationship indicated by terms such as "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0020] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "plurality" means one or more, unless otherwise clearly and specifically defined.

[0021] Existing shielded gate MOSFETs usually use silicon dioxide (SiO2) as the gate oxide layer of the shielded gate. This design can improve the device's withstand voltage strength to a certain extent, but due to the physical characteristics of silicon dioxide's low dielectric constant, the thickness of the gate oxide layer of the shielded gate cannot be too thick, otherwise the shielded gate cannot deplete the drift region, and although a thin SiO2 layer can achieve a better auxiliary depletion effect, it will cause the thin SiO2 of the device to break down. In summary, the above two points lead to a low breakdown voltage of the device.

[0022] The current better solution is to replace silicon dioxide with an oxide with a higher dielectric constant, such as hafnium dioxide. However, after replacing it with a high dielectric constant material, a thicker oxide layer can be designed under the same auxiliary depletion effect, but due to the large change in the dielectric constant, the device's trench width and platform width usually need to be redesigned, thereby increasing the device's design cost. In addition, due to the physical properties of the material, the dielectric constant of a single oxide layer can usually only change suddenly and cannot be flexibly selected.

[0023] The embodiments of the present application provide a novel shielded gate MOSFET structure, which can improve the breakdown voltage of the novel shielded gate MOSFET structure device without redesigning the groove width and platform width of the device.

[0024] See also Figure 1 As shown, the first aspect of an embodiment of the present application provides a new shielded gate MOSFET structure, including: an N-type substrate 210, an N-type drift region 220, a composite dielectric material layer 31, a shielding gate polysilicon layer 320, a gate dielectric material layer 411, a control gate polysilicon layer 412, a first P-type base region 521, a second P-type base region 522, a first N-type doped region 511, a second N-type doped region 512, a source layer 120 and a drain layer 110.

[0025] The N-type drift region 220 is a concave structure, the composite dielectric material layer is used to isolate the shielding gate polysilicon layer 320 from the bottom and two side walls of the groove of the N-type drift region 220, the composite dielectric material layer includes a first dielectric material layer 311 and a second dielectric material layer 312, the dielectric constant of the first dielectric material layer 311 is less than the dielectric constant of the second dielectric material layer 312, and the first dielectric material layer 311 is in contact with the N-type drift region 220; the gate dielectric material layer 411 is arranged in the groove of the N-type drift region 220, and the gate dielectric material layer 411 wraps the control gate polysilicon layer; the first P-type base region 521 and the second P-type base region 5 22 is an L-shaped structure, which is respectively arranged on both sides of the N-type drift region 220; the first N-type doping region 511 is located on the horizontal part of the first P-type base region 521 of the L-shaped structure, and is in contact with the gate dielectric material layer 411, and the second N-type doping region 512 is located on the horizontal part of the second P-type base region 522 of the L-shaped structure, and is in contact with the gate dielectric material layer 411; the source layer 120 is in contact with the first N-type doping region 511, the second N-type doping region 512, the first P-type base region 521 and the second P-type base region 522, and is in contact with the shielding gate polysilicon layer 320; the drain layer 110 is arranged on the back side of the N-type substrate 210.

[0026] The present application arranges a composite dielectric material layer and a shielding gate polysilicon layer 320 in the groove of the N-type drift region 220, and the composite dielectric material layer isolates the shielding gate polysilicon layer 320 from the bottom and two side walls of the groove of the N-type drift region 220. The composite dielectric material layer includes a first dielectric material layer 311 and a second dielectric material layer 312, and the first dielectric material layer 311 is in contact with the N-type drift region 220. By arranging the first dielectric material layer 311 with a lower dielectric constant on the side close to the N-type drift region 220 and arranging the second dielectric material layer 312 with a higher dielectric constant on the side close to the shielding gate polysilicon layer 320, the high dielectric constant characteristics of the second dielectric material layer 312 can be used to achieve the same auxiliary depletion effect with a thicker shielding gate oxide layer, thereby enhancing the breakdown voltage at the bottom of the shielding gate, and because the auxiliary depletion effect is close, the impact on the on-resistance of the device is low. The novel shielded gate MOSFET structure proposed in the present application optimizes the breakdown voltage of the device without changing the trench width and platform width of the device, and does not increase the design cost of the shielded gate device.

[0027] In one embodiment of the present application, Figure 1As shown, the gate dielectric material layer 411 can be located on the upper side of the first dielectric material layer 311, the second dielectric material layer 312 and the shielding gate polysilicon layer 320, so that the control gate polysilicon layer and the shielding gate polysilicon layer 320 are distributed up and down. In addition, the bottom of the gate dielectric material layer 411 can form a closed cavity with the first dielectric material layer 311, and the shielding gate polysilicon layer 320 and the second dielectric material layer 312 are located in the closed cavity.

[0028] In the present application embodiment, Figure 1 As shown, when the control gate polysilicon layer and the shield gate polysilicon layer 320 are in an up-and-down distribution structure, the first dielectric material layer 311 is disposed on the inner wall of the N-type drift region 220, the second dielectric material layer 312 is disposed on the inner wall of the first dielectric material layer 311, the control gate polysilicon layer is located in the groove of the second dielectric material layer 312, the first P-type base region 521 and the second P-type base region 522 are respectively disposed on the side of the N-type drift region 220; the gate dielectric material layer 411 is located on the first dielectric material layer 3 11. The second dielectric material layer 312 and the control gate polysilicon layer, and the gate dielectric material layer 411 wraps the second shielding gate polysilicon layer 320; the first N-type doping region 511 and the second N-type doping region 512, the first N-type doping region 511 is located on the horizontal portion of the first P-type base region 521 and contacts the first side wall of the gate dielectric material layer 411, and the second N-type doping region 512 is located on the horizontal portion of the second P-type base region 522 and contacts the second side wall of the gate dielectric material layer 411.

[0029] In the embodiment of the present application, the control gate polysilicon layer and the shield gate polysilicon layer 320 may be distributed in a left-middle-right structure in addition to being distributed in an up-down manner.

[0030] like Figure 2 As shown, the gate dielectric material layer 411 can be located on the left and right sides of the first dielectric material layer 311, the second dielectric material layer 312 and the shielding gate polysilicon layer 320, and the control gate polysilicon layer is located on both sides of the shielding gate polysilicon layer 320, thereby making the control gate polysilicon layer and the shielding gate polysilicon layer 320 present a left-middle-right distribution structure.

[0031] The present application does not impose any restrictions on the distribution of the shielding gate polysilicon layer 320 and the control gate polysilicon layer. For the sake of convenience, the following mainly uses the upper and lower distribution structure between the control gate polysilicon layer and the shielding gate polysilicon layer 320 as an example to illustrate the solution of the present application.

[0032] In one embodiment of the present application, Figure 1 As shown, the second dielectric material layer 312 may be in a concave structure, half-wrapping the shielding gate polysilicon layer 320 .

[0033] In one embodiment of the present application, Figure 4 As shown, the second dielectric material layer 312 may also be in a square structure to fully wrap the shielding gate polysilicon layer 320 .

[0034] In one embodiment of the present application, the first dielectric material layer 311 and the gate dielectric material layer 411 may be made of the same material.

[0035] In one embodiment of the present application, the first dielectric material layer 311 and the gate dielectric material layer 411 are made of silicon dioxide, and the second dielectric material layer 312 is made of hafnium dioxide.

[0036] In one embodiment of the present application, the first dielectric material layer 311 and the gate dielectric material layer 411 are silicon dioxide, and the second dielectric material layer 312 is silicon nitride.

[0037] In one embodiment of the present application, the composite dielectric material layer may further include a third dielectric material layer.

[0038] like Figure 3 As shown, the third dielectric material layer may be disposed between the second dielectric material layer 312 and the shielding gate polysilicon layer 320 , and the dielectric constant of the third dielectric material layer is greater than or equal to the dielectric constant of the first dielectric material layer 311 .

[0039] For example, in one embodiment of the present application, the first dielectric material layer 311 is silicon dioxide, the second dielectric material layer 312 is silicon nitride, and the third dielectric material layer is hafnium dioxide. That is, the dielectric constant of the third dielectric material layer is greater than the dielectric constant of the first dielectric material layer 311 and the dielectric constant of the second dielectric material layer 312, and the dielectric constant of the first dielectric material layer 311 is less than the dielectric constant of the second dielectric material layer 312.

[0040] For another example, in one embodiment of the present application, the first dielectric material layer 311 is silicon dioxide, the second dielectric material layer 312 is hafnium dioxide, and the third dielectric material layer is silicon dioxide. That is, the dielectric constant of the third dielectric material layer is equal to the dielectric constant of the first dielectric material layer 311, and the dielectric constant of the first dielectric material layer 311 is less than the dielectric constant of the second dielectric material layer 312.

[0041] It should be noted that the above is only an example of the structure of the composite dielectric material layer, and it does not limit the scope of protection of the present application. In other embodiments of the present application, the composite dielectric material layer can also be implemented by other structures, as long as it includes at least a first dielectric material layer and a second dielectric material layer. For example, the composite dielectric material layer can also include more than three dielectric material layers, and at least two dielectric material layers with different dielectric constants. In the embodiments of the present application, all materials with different dielectric constants can be used to prepare the composite dielectric material layer.

[0042] In one embodiment of the present application, the shielding gate polysilicon layer 320 can be a stepped structure, and the width of the shielding gate polysilicon layer 320 gradually increases from the drain layer 110 to the source layer 120; accordingly, the thickness of the second dielectric material layer 312 gradually decreases from the drain layer 110 to the source layer 120 to further optimize the electric field of the N-type drift layer.

[0043] For example, Figure 4 As shown, the shielding gate polysilicon layer 320 is a stepped structure including a step, and the width of the shielding gate polysilicon layer 320 close to the drain layer 110 is smaller than the width close to the source layer 120 .

[0044] In one embodiment of the present application, the first dielectric material layer 311 and the second dielectric material layer 312 are in a stepped structure, that is, the thickness of the first dielectric material layer 311 varies with the thickness of the second dielectric material layer 312, so that the thickness difference between the first dielectric material layer 311 and the second dielectric material layer 312 at different depths is the same.

[0045] In some embodiments, the thickness of the second dielectric material layer 312 is less than the thickness of the first dielectric material layer 311 .

[0046] In some embodiments, the thickness of the third dielectric material layer is greater than the thickness of the second dielectric material layer 312 .

[0047] The performance of the novel shielded gate MOSFET structure provided in the embodiment of the present application is compared with the comparative structure provided in the embodiment of the present application as follows: A structure in which a single silicon dioxide (SiO2) is used as the shielding gate oxide layer of the shielding gate polysilicon layer 320 is taken as comparison structure 1, a structure in which a single hafnium dioxide (HfO2) is used as the shielding gate oxide layer of the shielding gate polysilicon layer 320 is taken as comparison structure 2, and a structure in which the composite dielectric material layer provided in an embodiment of the present application (the first dielectric material layer 311 is silicon dioxide, and the second dielectric material layer 312 is hafnium dioxide, i.e., a composite dielectric material layer of SiO2+HfO2) is used as the shielding gate oxide layer of the shielding gate polysilicon layer 320 is taken as an improved structure (i.e., the novel shielding gate MOSFET structure provided in an embodiment of the present application), and the simulation results of these three structures are shown in Tables 1, 2, 3 and 4 below.

[0048] Among them, Table 1 shows the on-resistance Ron, breakdown voltage BV and threshold voltage Vth corresponding to the comparative structure 1 under the silicon dioxide shielding gate oxide layer with different thicknesses; Table 2 shows the on-resistance Ron, breakdown voltage BV and threshold voltage Vth corresponding to the comparative structure 2 under the hafnium oxide shielding gate oxide layer with different thicknesses; Table 3 shows the on-resistance Ron, breakdown voltage BV and threshold voltage Vth corresponding to the improved structure under the silicon dioxide shielding gate oxide layer with different thicknesses and the total thickness of the shielding gate oxide layer is 0.45um; the data of the structure in Table 4 are derived from the advantage parameter FOM values ​​(i.e., BV) in Tables 1, 2 and 3. 2 / Ron) are the optimal device structures respectively.

[0049] Table 1:

[0050] Table 2:

[0051] Table 3:

[0052] Table 4:

[0053] From Table 4 above, it can be seen that the BV of the new shielded gate MOSFET structure with SiO2+HfO2 as the shielded gate oxide layer is increased by 24V compared with the BV of the shielded gate MOSFET structure with SiO2 as the shielded gate oxide layer, and the BV of the shielded gate MOSFET structure with HfO2 as the shielded gate oxide layer is increased by 34V; from the FOM value, the FOM value of the new shielded gate MOSFET structure with SiO2+HfO2 as the shielded gate oxide layer is 286.6, which is 125 (77.6%) higher than the FOM value of the shielded gate MOSFET structure with SiO2 as the shielded gate oxide layer, and 162 (131.7%) higher than the FOM value of the shielded gate MOSFET structure with HfO2 as the shielded gate oxide layer; the Ron and Vth of the three have no significant changes. The new shielded gate MOSFET structure with the composite dielectric material layer as the shielded gate oxide layer of the shielded gate MOSFET can significantly improve the BV characteristics of the shielded gate MOSFET and achieve a better FOM value.

[0054] Figure 5 The following is a comparison chart of the simulation results of the output characteristic curves of the above three structures, wherein the horizontal axis is the source-drain voltage Vds, and the vertical axis is the source-drain current Ids. Figure 6 The following is a comparison chart of the breakdown voltage simulation results of the above three structures. The horizontal axis is the source-drain voltage Vds, and the vertical axis is the source-drain current Ids. Figure 5 and Figure 6 As shown, compared with the shielded gate MOSFET containing only a single dielectric material layer, the new shielded gate MOSFET containing a composite dielectric material layer provided in the embodiment of the present application has no significant changes in on-resistance (Ron) and threshold voltage (Vth), but the breakdown voltage (BV) is significantly improved.

[0055] like Figure 7 As shown, the second aspect of the embodiment of the present application further provides a method for preparing a novel shielded gate MOSFET structure, and the preparation method includes steps S100 to S800.

[0056] Step S100 : forming an N-type drift layer by epitaxial growth on the front side of the N-type substrate 210 .

[0057] like Figure 8 As shown, an N-type drift layer 221 having a thickness greater than that of the N-type substrate 210 may be formed by epitaxy on the front side of the N-type substrate 210 .

[0058] In one embodiment of the present application, the thickness of the N-type substrate 210 is 2-6 um, and the concentration of the N-type doping ions is 1e21-1.5e21 cm -3 The thickness of the N-type drift layer is 7-15um, and the concentration of N-type doping ions is 1e15~2e17cm -3 .

[0059] Step S200 , forming a first deep trench in the central region of the N-type drift layer 221 by etching, and forming an N-type drift region 220 with a concave structure.

[0060] like Fig. 9 As shown, the depth of the first deep trench may be greater than half of the depth of the N-type drift layer.

[0061] In one embodiment of the present application, the first deep groove has a depth of 4.5-7.5 um and a width of 0.7-1.2 um.

[0062] In step S300, a first dielectric material layer 311 and a second dielectric material layer 312 are sequentially formed along the inner wall of the N-type drift region 220, and then a composite dielectric material layer is formed, and a shielding gate polysilicon layer 320 is formed in the groove of the composite dielectric material layer; wherein the composite dielectric material layer is used to isolate the shielding gate polysilicon layer 320 from the bottom and two side walls of the groove of the N-type drift region 220, the dielectric constant of the first dielectric material layer 311 is smaller than the dielectric constant of the second dielectric material layer 312, and the first dielectric material layer 311 is in contact with the N-type drift region 220.

[0063] Step S400 , forming a concave gate dielectric material layer 411 in the first deep trench, and filling the polysilicon layer material to obtain a control gate polysilicon layer; the gate dielectric material layer 411 wraps the control gate polysilicon layer.

[0064] like Fig.10 , Fig.11 , Fig.12 , Fig.13 , Fig.14 and Fig.15 As shown, when the control gate polysilicon layer and the shield gate polysilicon layer 320 are in an up-down distribution structure, step S300 and step S400 can first form the first dielectric material layer 311 and the second dielectric material layer 312 in sequence through the inner wall of the N-type drift region 220 through a thermal oxidation process and a deposition process, and then form a composite dielectric material layer to obtain Fig.11 The structure of the composite dielectric material layer 312 can be 0.1-0.3 um thick. Then, a shielding gate polysilicon layer 320 is formed in the groove of the composite dielectric material layer to obtain Fig.12 Then, the first deep groove is etched back by an etching process, the etching depth is about 1.5um, and the thickness of the formed shield gate polysilicon layer 320 can be 0.5~5um, and the following is obtained: Fig.13 structure.

[0065] Next, a concave gate dielectric material layer 411 is formed in the first deep trench, and a polysilicon layer material is filled to obtain a control gate polysilicon layer, thereby obtaining Fig.14 For example, the first deep trench is filled with SiO2 and then etched back to form an oxide layer with a sidewall thickness of 0.2-0.4um, and then a gate oxide layer with a bottom thickness of about 0.5-1um is formed through a gate oxide process, thereby obtaining Fig.14 The gate dielectric material layer 411 in.

[0066] Finally, an N-type polysilicon material is deposited in the gate dielectric material layer 411 to form a control gate polysilicon layer, and a Fig.15 The structure of the control gate polysilicon layer can be 0.5~5um thick and the doping concentration can be 1e18~1e21cm -3 .

[0067] It should be noted that in the embodiment of the present application, the control gate polysilicon layer and the shield gate polysilicon layer 320 may be arranged in a left-middle-right distribution structure in addition to an up-down distribution structure. Figure 2As shown, the gate dielectric material layer 411 can be located on the left and right sides of the first dielectric material layer 311, the second dielectric material layer 312 and the shielding gate polysilicon layer 320, and the control gate polysilicon layer is located on both sides of the shielding gate polysilicon layer 320, thereby making the control gate polysilicon layer and the shielding gate polysilicon layer 320 present a left-middle-right distribution structure.

[0068] The present application does not limit the distribution of the shielding gate polysilicon layer 320 and the control gate polysilicon layer.

[0069] In step S500 , P-type doping ions are implanted into the side of the N-type drift region 220 to form a first P-type base region 521 and a second P-type base region 522 . The first P-type base region 521 and the second P-type base region 522 are respectively disposed on both sides of the N-type drift region 220 .

[0070] In the present application embodiment, Fig.16 As shown, the width of the first P-type base region 521 and the second P-type base region 522 can be equal to the width of the two side portions of the concave N-type drift region 220, and the depth of the first P-type base region 521 and the second P-type base region 522 can be equal to the depth of the control gate polysilicon layer.

[0071] In step S600, N-type doping ions are injected into partial areas of the first P-type base region 521 and the second P-type base region 522 to form a first N-type doping region 511 and a second N-type doping region 512, and the first P-type base region 521 and the second P-type base region 522 are made into an L-shaped structure, the first N-type doping region 511 is located on the horizontal portion of the first P-type base region 521 and is in contact with the gate dielectric material layer 411, and the second N-type doping region 512 is located on the horizontal portion of the second P-type base region 522 and is in contact with the gate dielectric material layer 411.

[0072] like Fig.16 As shown, in one embodiment of the present application, the first N-type doping region 511 and the second N-type doping region 512 are located on both sides of the gate dielectric material layer 411, and the width of the first N-type doping region 511 and the second N-type doping region 512 is greater than half of the width of the first P-type base region 521 and the second P-type base region 522.

[0073] In step S700 , a source layer 120 is formed which contacts the first N-type doping region 511 , the second N-type doping region 512 , the first P-type base region 521 , and the second P-type base region 522 , and contacts the shielding gate polysilicon layer 320 .

[0074] Step S800 , forming a drain layer 110 on the back side of the N-type substrate 210 .

[0075] A third aspect of the embodiments of the present application further provides a chip, comprising a novel shielded gate MOSFET structure as described in any of the above embodiments.

[0076] The beneficial effects of the embodiments of the present application are as follows: by arranging a composite dielectric material layer and a shielding gate polysilicon layer in the groove of the N-type drift region, the shielding gate polysilicon layer is isolated from the bottom and two side walls of the groove of the N-type drift region by the composite dielectric material layer, and the composite dielectric material layer includes a first dielectric material layer and a second dielectric material layer, the first dielectric material layer is in contact with the N-type drift region, by arranging a first dielectric material layer with a lower dielectric constant on the side close to the N-type drift region, and arranging a second dielectric material layer with a higher dielectric constant on the side close to the shielding gate polysilicon layer, by utilizing the high dielectric constant characteristics of the second dielectric material layer, the same auxiliary depletion effect can be achieved with a thicker shielding gate oxide layer, thereby enhancing the breakdown voltage at the bottom of the shielding gate, and at the same time, due to the proximity of the auxiliary depletion effect, the impact on the on-resistance of the device is low. The novel shielding gate MOSFET structure proposed in the present application is realized to optimize the breakdown voltage of the device without changing the trench width and platform width of the device, and will not increase the design cost of the shielding gate device.

[0077] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned doping regions and devices is used as an example for illustration. In actual applications, the above-mentioned functions can be assigned to different doping regions and devices as needed, that is, the internal structure of the device is divided into different doping regions to complete all or part of the functions described above. The doping regions and devices in the embodiments can be integrated into one unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0078] In addition, the specific names of the doping regions and devices are only for the convenience of distinguishing each other and are not used to limit the scope of protection of the present application.

[0079] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0080] In addition, each doping region in each embodiment of the present application may be integrated into one unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0081] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A novel shielded gate MOSFET structure, characterized in that: include: N-type substrate; An N-type drift region, wherein the N-type drift region is a concave structure; A composite dielectric material layer and a shielding gate polysilicon layer, wherein the composite dielectric material layer is used to isolate the shielding gate polysilicon layer from the bottom and two side walls of the N-type drift region groove; wherein the composite dielectric material layer comprises a first dielectric material layer and a second dielectric material layer, the dielectric constant of the first dielectric material layer is smaller than the dielectric constant of the second dielectric material layer, and the first dielectric material layer is in contact with the N-type drift region; A gate dielectric material layer and a control gate polysilicon layer, wherein the gate dielectric material layer is disposed in the groove of the N-type drift region, and the gate dielectric material layer wraps the control gate polysilicon layer; A first P-type base region and a second P-type base region, wherein the first P-type base region and the second P-type base region are in an L-shaped structure and are respectively arranged at two sides of the N-type drift region; a first N-type doping region and a second N-type doping region, wherein the first N-type doping region is located on a horizontal portion of the first P-type base region of the L-shaped structure and contacts the gate dielectric material layer, and the second N-type doping region is located on a horizontal portion of the second P-type base region of the L-shaped structure and contacts the gate dielectric material layer; a source layer, contacting the first N-type doping region, the second N-type doping region, the first P-type base region and the second P-type base region, and contacting the shield gate polysilicon layer; A drain layer is disposed on the back side of the N-type substrate.

2. The novel shielded gate MOSFET structure as claimed in claim 1, characterized in that: The gate dielectric material layer is located on the first dielectric material layer, the second dielectric material layer and the shielding gate polysilicon layer. The bottom of the gate dielectric material layer and the first dielectric material layer form a closed cavity. The shielding gate polysilicon layer and the second dielectric material layer are located in the closed cavity.

3. The novel shielded gate MOSFET structure as claimed in claim 2, characterized in that: The first dielectric material layer is made of the same material as the gate dielectric material layer.

4. The novel shielded gate MOSFET structure as claimed in claim 1, characterized in that: The first dielectric material layer and the gate dielectric material layer are silicon dioxide; the second dielectric material layer is hafnium dioxide.

5. The novel shielded gate MOSFET structure according to any one of claims 1 to 4, characterized in that: The composite dielectric material layer further comprises: A third dielectric material layer is disposed between the second dielectric material layer and the shielding gate polysilicon layer, and a dielectric constant of the third dielectric material layer is greater than or equal to a dielectric constant of the first dielectric material layer.

6. The novel shielded gate MOSFET structure according to any one of claims 1 to 4, characterized in that: The shielding gate polysilicon layer is a stepped structure, and the width of the shielding gate polysilicon layer gradually increases from the drain layer to the source layer.

7. The novel shielded gate MOSFET structure as claimed in claim 6, characterized in that: The thickness of the second dielectric material layer gradually decreases from the drain layer to the source layer.

8. The novel shielded gate MOSFET structure according to any one of claims 1 to 4, characterized in that: The first dielectric material layer and the second dielectric material layer are in a stepped structure.

9. A method for preparing a novel shielded gate MOSFET structure, characterized in that: The preparation method comprises: Epitaxially forming an N-type drift layer on the front side of the N-type substrate; Forming a first deep trench in the central region of the N-type drift layer by etching, and forming an N-type drift region with a concave structure; A composite dielectric material layer is formed after a first dielectric material layer and a second dielectric material layer are sequentially formed along the inner wall of the N-type drift region, and a shielding gate polysilicon layer is formed in the groove of the composite dielectric material layer; wherein the composite dielectric material layer is used to isolate the shielding gate polysilicon layer from the bottom and two side walls of the groove of the N-type drift region, the dielectric constant of the first dielectric material layer is smaller than the dielectric constant of the second dielectric material layer, and the first dielectric material layer is in contact with the N-type drift region; A concave gate dielectric material layer is formed in the first deep groove, and is filled with a polysilicon layer material to obtain a control gate polysilicon layer; the gate dielectric material layer wraps the control gate polysilicon layer; Implanting P-type doping ions into the side of the N-type drift region to form a first P-type base region and a second P-type base region, wherein the first P-type base region and the second P-type base region are respectively arranged on both sides of the N-type drift region; Implanting N-type doping ions into partial regions of the first P-type base region and the second P-type base region to form a first N-type doping region and a second N-type doping region, and making the first P-type base region and the second P-type base region present an L-shaped structure, wherein the first N-type doping region is located on a horizontal portion of the first P-type base region of the L-shaped structure and contacts the gate dielectric material layer, and the second N-type doping region is located on a horizontal portion of the second P-type base region of the L-shaped structure and contacts the gate dielectric material layer; forming a source layer in contact with the first N-type doping region, the second N-type doping region, the first P-type base region and the second P-type base region, and in contact with the shield gate polysilicon layer; A drain layer is formed on the back side of the N-type substrate.

10. A chip, characterized in that: It comprises a novel shielded gate MOSFET structure as claimed in any one of claims 1 to 8.

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