Programmable gate design for multiple gates

Abstract

The invention provides a multi-gate transistor and a manufacturing method thereof. The transistor comprises a common substrate, a source electrode, a drain electrode, a body, a first grid electrode and a second grid electrode. The first gate electrode and the second gate electrode are collinearly arranged along a horizontal plane of the common substrate and separated by a dielectric wall. The dielectric wall provides electrical isolation between the first gate electrode and the second gate electrode.

Description

Field of the Invention

[0001] Various aspects of the present disclosure relate to dual-gate transistors. More specifically, various aspects of the present disclosure relate to dual-gate transistors with programmable gate designs. Background Art

[0002] It has been found that the efficiency of a transistor varies with the level of current passing through the transistor at low voltages. This is because at low voltages, the drain-to-source resistance (R ds There is a trade-off between reducing the gate voltage (V gs ) reduces R ds , but it brings the problem of increasing gate drive capacitance loss. MOSFET devices with large gate area allow higher V gs , devices with smaller gate area offer lower gate drive capacitance but cannot tolerate higher V gs Therefore, a MOSFET device with a smaller gate area may be more efficient at light loads because of the efficiency loss of the gate drive capacitor at low loads and high frequencies, which is reflected in the R ds dominates at higher loads, while at higher loads it may be more efficient to have a gs of a larger gate, because R ds The losses may dominate at normal or higher current loads.

[0003] Currently, the solution to this problem is to position two different sized switch devices on the same substrate, with one switch device being larger than the other. Under high load conditions, the larger switch or two switches can be used, while under low load conditions, the smaller switch can be used. Figure 1 Schematic diagram of a dual-gate n-channel MOSFET of the prior art is shown. As shown in the figure, the dual-gate n-channel MOSFET here has a common substrate and includes a common drain D and a source S controlled by two gates G1 and G2. The diode D1 is formed by a PN junction between the drain D and the body region in the common substrate. This is the so-called anti-parallel diode. In the implementation of the prior art, the width of the second switch W2 is a setting factor of the width of the first switch W1; therefore W2=nW1. The output terminal of the gate control can be coupled to the first gate G1. The gate control can be, for example, a gate driver, and controls the operation of the first gate by providing a pulse width modulation signal to the terminal of the first gate. When the switch is closed, the second gate G2 can be connected to the output terminal of the gate control and the first gate G1 through the switch SW. When the switch is open, the second gate G2 is electrically isolated from the first gate.

[0004] Different applications for dual-gate devices may have different gate voltage and / or load requirements. In prior art implementations of dual-gate devices, the width of the gate is set early in the manufacturing stage, which means that the width of the first gate and the second gate cannot be changed without redesigning the entire circuit. This means that for each application with different voltage or load requirements, the entire dual-gate device must be redesigned to accommodate the application. In addition to redesigning the layout of the device itself, each manufacturing stage of the device must be changed to accommodate the new layout of the device. This means that the cost of adapting to new applications is very high. In addition, based on prior art, since the layout of the gate area must be specifically designed based on the application, prototyping of device areas with different ratios of gate 1 to gate 2 is very expensive.

[0005] It is against this background that various aspects of the present invention are presented. Summary of the invention

[0006] The present invention provides a multi-gate transistor, comprising: a common substrate, a source, a drain, a body, a first gate and a second gate, wherein the first gate and the second gate are arranged in a colinear manner along the horizontal plane of the common substrate and are separated by a dielectric wall, and wherein the dielectric wall provides electrical isolation between the first gate electrode and the second gate electrode.

[0007] It also includes a gate control, wherein the first gate electrode is connected to the output terminal of the gate control, the second gate electrode is connected to the output terminal through a switch, and when the switch is disconnected, the first gate electrode and the second gate electrode are electrically isolated from each other.

[0008] The first gate electrode and the second gate electrode are collinearly arranged into two or more lines along a horizontal plane of the common substrate.

[0009] It also includes a first gate metal and a second gate metal, wherein the ratio of the first gate electrode to the second gate electrode in the area of ​​the common substrate depends on the number of lines of the first gate electrode material electrically contacting the first gate metal.

[0010] The ratio of the first gate to the second gate in the region of the common substrate further depends on the number of lines of the second gate electrode material electrically contacting the second gate metal.

[0011] The first gate electrode includes a first gate polysilicon layer disposed in a gate trench, and the second gate electrode includes a second gate polysilicon layer arranged in the gate trench.

[0012] Also included is a shielding electrode in the gate trench, wherein the shielding electrode extends below both the first gate electrode and the second gate electrode in the gate trench, wherein the shielding circuit is electrically isolated from the first gate electrode and the second gate electrode.

[0013] Wherein, the first gate electrode comprises a first gate polysilicon layer disposed on an insulating layer on the horizontal plane of the common substrate, and wherein the second gate electrode comprises a second gate polysilicon layer arranged above the insulating layer.

[0014] The present invention also discloses a method for manufacturing a multi-gate transistor, comprising: preparing a gate trench on a substrate; depositing an insulating layer in the gate trench; selectively etching the insulating layer to form a dielectric wall in a portion of the gate trench; forming a gate electrode insulating layer in the gate trench, depositing a conductive layer on the gate electrode insulating layer; and etching a portion of the conductive layer to form a first gate electrode and a second gate electrode, wherein the dielectric wall separates the first gate from the second gate.

[0015] The method further includes depositing a shielding electrode insulating layer at the bottom of the groove and forming a shielding electrode on the shielding electrode insulating layer, wherein the insulating layer is formed on the shielding electrode and the shielding electrode extends under the first gate and the second gate.

[0016] Wherein, it also includes a) forming at least one additional gate trench in the substrate, wherein b) includes depositing an insulating layer on the surface of the at least one additional gate trench, and wherein c) includes selectively etching the at least one additional gate trench to form a dielectric wall in a portion of the at least one additional gate trench.

[0017] The method further includes depositing a top insulating layer on the first gate electrode and the second gate electrode, wherein the top insulating layer includes a via to expose a portion of the first gate electrode, and forming a first gate metal on the top insulating layer.

[0018] The ratio of the first gate electrode to the second gate electrode in the region of the common substrate depends on the number of lines of the first gate electrode material that are in electrical contact with the first gate metal.

[0019] Wherein, it also includes forming a second gate metal on the top insulating layer, and wherein the ratio of the first gate electrode to the second gate electrode in the area of ​​the common substrate further depends on the number of lines of the second gate electrode material electrically contacting the second gate metal.

[0020] The present invention further discloses a multi-gate transistor, comprising: a lightly doped epitaxial layer of a first conductivity type, covering a heavily doped common substrate of the first conductivity type; a first trench gate, arranged in a first trench portion extending into the epitaxial layer, and a second trench gate, arranged in a second trench portion extending into the epitaxial layer, wherein the first trench gate is electrically isolated from the second trench gate; a source layer of the first conductivity type, arranged on the top surface of the epitaxial layer surrounding the first trench gate and the second trench gate, and electrically connected to the source layer region separated by the first trench portion and the second trench portion; and a common drain, arranged on the bottom of the common substrate.

[0021] It also includes a body layer with a second conductivity type, which is arranged in the epitaxial layer below the source layer.

[0022] Wherein, the first trench portion and the second trench portion are collinearly aligned along a horizontal plane of the common substrate and are separated by a dielectric wall, wherein the dielectric wall provides electrical isolation between the first gate and the second gate.

[0023] The first trench gate and the second trench gate are collinearly arranged into two or more lines along the horizontal plane of the common substrate.

[0024] The first trench gate includes a first gate polysilicon layer arranged in the first channel portion, and the second trench gate includes a second gate polysilicon disposed in the second trench portion, wherein the dielectric wall separates the first gate polysilicon layer from the second gate polysilicon layer.

[0025] It also includes a shielding electrode extending below the first trench gate and the second trench gate in the gate trench, wherein the shielding electrode is electrically isolated from the first trench gate and the second trench gate. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Other features and advantages of the present invention will become apparent upon reading the following detailed description and upon reference to the following drawings, in which:

[0027] Figure 1 A schematic diagram showing a prior art dual-gate n-channel MOSFET.

[0028] Figure 2 A top view showing a trench layout for a programmable gate design of a dual-gate transistor according to one aspect of the present invention.

[0029] Figure 3 A top view of a gate oxide with a trench layout for a programmable gate design of a dual-gate transistor is shown in accordance with one aspect of the present invention.

[0030] Figure 4 1 shows a top view of a gate metal layout with 100% device area including gate one for a programmable gate design for a dual-gate transistor in accordance with one aspect of the present invention.

[0031] Figure 5 A top view showing a gate metal layout of a programmable gate design for a dual-gate transistor having 75% of the device area including gate one and 25% of the device area including gate two according to one aspect of the present invention.

[0032] Figure 6 A top view of a gate metal layout for a programmable gate design for a dual-gate transistor is shown with 62.5% of the device area including gate one and 37.5% of the device area including gate two according to one aspect of the present invention.

[0033] Figure 7 Represents a top view of a gate metal layout of a programmable gate design of a dual-gate transistor according to one aspect of the present invention, the gate metal layout having a 55% device area including a gate and a 55% device area including a gate two.

[0034] Figures 8A-8N A method for fabricating a dual-gate shielded gate transistor (SGT) with a programmable gate design according to one aspect of the present invention is shown.

[0035] Fig. 9 A cross-sectional view of a dual-gate SGT is shown at a step in the fabrication process after gate electrode material has been deposited in the trenches in accordance with one aspect of the present invention.

[0036] Fig.10 A cross-sectional view of a dual-gate SGT after source region doping according to one aspect of the present invention is shown.

[0037] Fig.11A A top view of a planar gate layout for a programmable gate design of a dual-gate transistor is shown in accordance with one aspect of the present invention.

[0038] Fig. 11B A side view showing a programmable gate design for a dual-gate planar gate transistor according to one aspect of the present invention. DETAILED DESCRIPTION

[0039] Although for the purpose of illustration, the following detailed description contains many specific details, it will be appreciated by those skilled in the art that many changes and modifications to the following details are within the scope of the present invention. Therefore, the exemplary embodiments of the present invention described below are proposed without losing the generality of the claimed invention and without imposing limitations thereon.

[0040] In the following detailed description, reference is made to the accompanying drawings, which form a part of this document, and in which specific embodiments in which the present invention may be practiced are shown by way of illustration. In this regard, directional terms, such as "top", "bottom", "front", "rear", "leading edge", "trailing edge", etc., are used with reference to the direction of the described figures. Because the components of embodiments of the present invention can be positioned in a plurality of different directions, the directional terms are used for illustrative purposes and are not restrictive. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. Therefore, the following detailed description should not be considered restrictive, and the scope of the present invention is defined by the appended claims.

[0041] The disclosure herein relates to semiconductor materials, such as silicon, doped with ions of a first conductivity type or a second conductivity type. The ions of the first conductivity type may be the opposite ions of the second conductivity type. For example, but not limited to, in some embodiments, the ions of the first conductivity type may be n-type, which contribute negative charge carriers, such as electrons, when doped into silicon. In such embodiments, the ions of the first conductivity type may include phosphorus, antimony, bismuth, lithium, and arsenic. In such embodiments, the ions of the second conductivity may be p-type, which generate holes for charge carriers when doped into silicon, and in this way are referred to as opposite to the n-type. P-type ions include boron, aluminum, gallium, and indium. Although the above description refers to the n-type as the first conductivity type and the p-type as the second conductivity type, the present disclosure is not limited thereto, and the p-type may be the first conductivity type, and the n-type may be the second conductivity type. In addition, according to various aspects of the present disclosure, semiconductor materials other than silicon, such as germanium, silicon carbide, and gallium arsenide, etc., may be used in MOSFET devices.

[0042] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof and in which are shown by way of illustration specific embodiments in which the invention may be practiced. For convenience, the use of + or - after specifying a conductivity or net impurity carrier type (p or n) generally refers to the relative concentration of net impurity carriers of the specified type in the semiconductor material. In general, n+ materials have a higher concentration of n-type net dopants (e.g., electrons) than n materials, and n materials have a higher carrier concentration than n- materials. Similarly, p+ materials have a higher concentration of p-type net dopants (e.g., holes) than p materials, and p materials have a higher concentration than p- materials. It should be noted that it is the net concentration of carriers that is relevant, not necessarily the dopant concentration. For example, a material can be heavily doped with an n-type dopant, but still have a relatively low net carrier concentration if the material is also heavily counter-doped with a p-type dopant. As used herein, about 10 16 / cm 3 Dopant concentrations greater than about 10 18 / cm 3 A doping concentration of 1000 Å can be considered “heavily doped”.

[0043] Figure 2 A top view of a trench layout for a programmable gate design for a dual-gate shielded gate transistor according to one aspect of the present disclosure is shown. As shown, the device 200 includes a common substrate 201 having a gate trench 202 for a first gate and a trench designated as a split gate trench 203. A portion 204 of the split gate trench 203 may be widened to support the formation of a via through the gate electrode insulating layer. The trench may also include a first gate trench gate contact region 206, which is enlarged to form a via through the gate insulating layer and the termination structure. The first gate trench may also include a longitudinal connection region 207, which connects the first gate trench 202 and the first gate contact region 206 extending in the substrate in a width direction. At the production stage shown, the source region has not yet been formed in the common substrate, but the source region 205 can be seen between the gate trenches 202.

[0044] Figure 3A top view of a thick insulating layer with a trench layout for a programmable gate design of a dual-gate transistor according to one aspect of the present disclosure is shown. As shown, a dielectric wall 301 is formed in a split gate trench 203. On the other hand, the first gate trench 202 remains intact, ensuring that the width of gate one is always greater than the width of gate two. A first gate metal insulating layer 302 is also shown. This layout allows the creation of gate electrodes in the split gate trenches that are collinearly arranged along the horizontal plane of a common substrate. A longitudinal connection region 207 connects a portion of the gate electrode 304 in the split gate trenches to make it part of the first gate electrode. The dielectric wall 301 separates the first gate electrode from the second gate electrode, and the dielectric wall insulates the first gate electrode from the second gate electrode. One advantage of this design is that the dielectric wall can be formed in the same step as the formation of the interpoly oxide of the shielded gate MOSFET, which means that no additional steps are required.

[0045] An advantage of this design is that the ratio of the device area occupied by gate one to gate two can be easily customized by changing the layout of the gate metal. The deposition of the gate metal is one of the last steps in the production of the device, so it is easier to prototype devices with different ratios without completely redesigning the device area. The ratio can be adjusted by changing the patterning of the gate metal layer, which can be achieved by changing a single mask. Typically, the ratio depends on the number of lines of the first gate electrode material that are in electrical contact with the first gate metal. The ratio can also depend on the number of lines of the second gate electrode material that are in electrical contact with the second gate metal.

[0046] Figure 4 A top view of a gate metal layout with 100% device area is shown, the gate metal layout including gate one of a programmable gate design for a dual-gate transistor according to one aspect of the present disclosure. In this embodiment, the first gate metal 401 includes fingers extending over the dielectric wall 301 and over the via region of each split gate trench. The source contact metal 404 contacts the source region of the substrate composition and shorts the body region to the source region through the source region insulating layer through the electroplated source via 406. The via 403 formed through the gate insulating layer conductively couples the gate metal to the gate electrode in the split gate trench. The via 405 in the first gate contact region conductively couples the first gate metal to the gate trench. Therefore, in this embodiment, the first gate is connected to the electrode material, such as polysilicon, on either side of the dielectric wall 301 in the split gate trench 203, which means that the entire gate width of the device area is occupied by the first gate. The via through the insulating layer can be formed by masking and etching the insulating layer. Although the second gate metal 402 is disposed on the gate metal dielectric layer, there is no via through the gate electrode insulating layer to contact the second gate metal, so no device region is formed by the second gate.

[0047] Figure 5 A top view of a gate metal layout of a programmable gate design for a dual-gate transistor according to one aspect of the present invention is shown, the gate metal layout having 75% of the device area including gate one and 25% of the device area including gate two. In this embodiment, the first gate metal includes three fingers 503 that span the dielectric wall 301 and contact the gate electrode in the split gate trench through the via 403. The second gate metal 502 includes two fingers 504 that extend over the gate via region of the split gate trench 203. The second gate metal 502 is conductively coupled to the gate electrode in the split gate trench through the via 505. As shown, the dielectric wall 506 separates the second gate electrode conductively coupled to the second gate metal from the first gate electrode conductively coupled to the first gate metal. The first gate includes a first gate trench 202 filled with the first gate electrode. The substrate region alternates between the first gate trench 202 and the split gate trench 203. Therefore, 75% of the gate area of ​​the device is part of the first gate, and 25% of the gate area of ​​the device is part of the second gate. From Figure 4 and Figure 5 It can be seen that the ratio of device area occupied by gate one to gate two is controlled by the configuration of the fingers in the first gate metal 501 and the second gate metal 502. The layout of the substrate region including the gate electrodes and vias remains the same between embodiments.

[0048] Figure 6 1 shows a top view of a gate metal layout for a programmable gate design for a dual-gate transistor according to one aspect of the present disclosure, the gate metal layout having 62.5% of the device area including gate one and 37.5% of the device area including gate two. In this embodiment, the first gate metal 601 includes two fingers, each of which is conductively coupled to a gate electrode in a respective separation gate trench 203, the first metal is also conductively contacted with the first gate electrode in the first gate trench, and a portion of the separation gate trench 203 on the side of the dielectric wall opposite to the via is also conductively coupled to the first gate trench. The second gate metal 602 includes three fingers, each of which is conductively coupled to a gate electrode in a respective separation gate trench 203. Therefore, 62% of the gate electrode area of ​​the device is conductively coupled to the first gate metal, and 37% of the electrode area of ​​the device is conductively coupled to the second gate.

[0049] In the split gate trench with the gate electrode conductively coupled to the second gate metal, it can be seen that a portion of the split gate trench is filled with a gate electrode conductively coupled to the first gate (i.e., the first gate electrode) 604 and a second portion of the split gate trench gate 603, wherein the gate electrode is conductively coupled to the second gate metal (i.e., the second gate electrode). Thus, the first gate electrode 604 and the second gate electrode 603 are collinearly arranged along a horizontal plane in the split gate trench formed in the common substrate separated here by a dielectric wall 605.

[0050] Figure 7 A top view of a gate metal layout for a programmable gate design for a dual-gate transistor having 50% of the device area including gate one and 50% of the device area including gate two is shown in accordance with one aspect of the present invention. In the illustrated embodiment, a first gate metal 701 is conductively coupled to a gate electrode in a split-gate trench 203 on a first side 703 of a dielectric wall 301, and a second gate metal 702 is conductively coupled to a gate electrode in the split gate on a second side 704 of the dielectric wall 301. As shown, the first gate metal is also conductively coupled to the gate electrode material in the first gate trench 202. Thus, the ratio of the first gate electrode to the second gate electrode is 50%.

[0051] Although Figures 4 to 7 The illustrated embodiment shows six first gate trenches alternating with five split gate trenches, but aspects of the present disclosure are not limited thereto. There can be any number of first gate trenches and any number of split gate trenches. Furthermore, there is no requirement that the first gate trenches alternate with the split gate trenches. The ratio of first gate trenches to split gate trenches can be arbitrary, for example, there can be one first gate trench for every two split gate trenches, every three split gate trenches, every four split gate trenches, etc. Alternatively, there can be one split gate trench for every two first gate trenches, every three gate trenches, every four gate trenches, etc.

[0052] Figures 8A-8M A method of manufacturing a dual-gate shielded gate transistor (SGT) having a programmable dual-gate design according to one aspect of the present disclosure is shown. Fig. 8A As shown, a substrate 801 heavily doped with a first conductivity type may be provided. For example, the substrate may be N-type doped. An epitaxial layer / drift region 802 may be grown on the surface of the substrate 801. The epitaxial layer / drift region 802 may be lightly doped with ions of the first conductivity type. A body region 803 may then be formed in the upper portion of the epitaxial layer. The body region may be formed by implanting ions of a second conductivity type into a selected portion of the epitaxial layer 802, wherein the second conductivity type is opposite to the first conductivity type. Alternatively, the body region 803 may be formed by implantation after forming the gate and just before the source implantation.

[0053] A trench 804 may be formed in the substrate composition, through the body region 803 and into the drift region 802. The trench may be formed by any suitable trench formation method, such as, but not limited to, reactive ion etching (RIE) or anisotropic wet etching. The trench 804 may be formed to a depth of about 1 micron or greater. The trench pitch may be less than 1 micron, and in one embodiment, the trench pitch may be, for example, but not limited to, 0.6 microns. Figure 8C As shown, the interior of the trench and the exposed surface of the substrate may be lined with a capping insulating layer 805, which will eventually become the lower portion of the shielding electrode insulating layer at the bottom of the trench 804. The capping insulating layer 805, as well as the subsequent shielding electrode insulating layer, may be made of, for example, but not limited to, silicon dioxide. The capping insulating layer 805 may be formed by any suitable method, such as, but not limited to, chemical vapor deposition (CVD) or thermal oxidation.

[0054] The shield electrode material 806 may be deposited overlying the top surface of the cap insulating layer 805. The shield electrode may be composed of any conductive material, such as but not limited to polysilicon. The shield electrode material 806 may be deposited by any suitable method, such as but not limited to chemical vapor deposition. The shield electrode material may then be etched away from the surface of the device, such as Fig. 8E The etchant is selected so that it selectively etches the surface of the substrate composition, thereby leaving the shield electrode 807 at the bottom of the trench.

[0055] Then, if Figure 8F As shown, an inter-poly insulator layer 808, such as an oxide layer, may be deposited on the surface of the substrate composition. The top of the inter-poly insulator is then removed from the surface of the substrate composition exposing the top of the body region 803. The top of the inter-poly insulator may be removed by any suitable method, such as, but not limited to, chemical and mechanical polishing (CMP).

[0056] like Figure 8G As shown, an inter-poly insulator mask 809 is formed over the trenches that will become split gate trenches. The inter-poly insulator layer 808 is then etched away from the surface of the substrate composition through the openings in the mask 809, leaving the inter-poly insulator layer intact beneath the dielectric walls. The inter-poly insulator mask can be any suitable photoresist mask material. The inter-poly insulator remains in the gate trenches 810 and forms dielectric walls 811 in the split gate trenches. A capping gate insulating layer is then applied over the substrate composition, such as Figure 8H As shown, the inter-poly oxide covers the side walls of the gate trench 810. The gate insulating layer may be, for example but not limited to, a silicon dioxide layer, and may be formed by any suitable method, for example but not limited to, CVD or thermal oxidation.

[0057] The gate electrode material 812 is disposed on the surface of the gate insulating layer, such as Figure 8I As shown. It can be seen that the gate electrode material fills the gate trench, but does not fill the trench area where the dielectric wall 811 is located. In the third dimension, which is not shown, the gate electrode material fills the split gate trench on either side of the dielectric wall. The gate electrode material 812 can be any suitable conductive material, such as but not limited to polysilicon. The gate electrode material can be deposited on the gate insulating layer, for example and without limitation, by CVD.

[0058] Next, if Figure 8J As shown, a portion of the gate material 812 is etched away from the top surface of the substrate composition to form a gate electrode 813 in the first gate trench 817 and on either side of the dielectric wall of the split gate trench 818. The dielectric wall electrically insulates the gate electrode material on one side of the split gate trench from the other side of the split gate trench. Any portion of the dielectric wall 811 above the body region 803 can be stripped away, and a maskless implant can be performed to form the source region 815, as shown. Figure 8K As shown. The source and gate insulating layer 814 can then be deposited on the surface of the substrate composition, such as Figure 8L The source and gate insulating layer 814 may include, for example but not limited to, a dielectric material such as silicon dioxide, and may be formed by any suitable method such as CVD.

[0059] The source via 821 is formed through the source insulating layer 814 and into the substrate composition, reaching a depth deeper than the source region 815 and exposing at least the surface of the body region 820. Figure 8M As shown, the source via terminates at about half the depth of the body region 820. The source via 821 exposes the body region for forming a source region and body short. The source via can be formed by a mask and any suitable dry etching method (e.g., reactive ion etching). The source region 815 can be heavily doped with ions of the first conductivity type. After the source region 815 is doped into the body region, the source mask can be removed by, for example, but not limited to, chemical cleaning and / or CMP. Figure 8N As shown, a metal layer 816 is finally disposed on top of the substrate composition. The source metal contacts both the source region and shorts the body region to the source region through the plated source via. The source metal can be plated and fill the via.

[0060] Alternatively, as shown here, the sides 822 of the vias may be plated with a plating material such as aluminum, copper, tungsten, iron, or any alloy thereof. A source metal layer may then fill the remaining space 823 in the source via. The gate electrode is insulated from the source metal by a gate insulating layer. Selected portions of the metal layer are masked and etched away to form separate source metal and gate metal regions. The gate metal may be connected to the gate contact through the via, e.g., Figure 4 , Figure 5 , Figure 6 and Figure 7 As shown. A top metal insulating layer (not shown) may be deposited on top of metal layer 816. Vias through the top metal insulating layer aligned with vias in the gate electrode insulation may be formed by, for example, but not limited to, masking and chemical etching, reactive ion etching, or mechanical means. The vias allow the gate metal to contact the gate electrode 813 in the trench 817.

[0061] Fig. 9 1 shows a cross-sectional view of a dual-gate SGT at a step during fabrication after gate electrode material has been deposited in the trenches, in accordance with various aspects of the present disclosure. Figure 8J 1. The manufacturing steps shown. In the device shown, there are two split gate trenches separated by a first gate trench. It can be seen that the gate electrode is continuous in the first gate trench 901 and extends parallel to the split gate trenches, with a portion of the substrate exposed between the trenches. The split gate trench has a first gate electrode 902 and a second gate electrode 903 located on either side of a dielectric wall 906. The first and second electrodes are collinearly arranged 907 along a horizontal plane 908 of the substrate composition. The shield electrode 904 is continuous in both the split gate trench and the first gate trench.

[0062] Fig.10 A cross-sectional view of a dual-gate SGT after source region doping according to one aspect of the present disclosure is shown. In order to show the surface of the substrate composition, the gate metal, source metal and source insulating layer are not shown here. In this view, the via 1001 passing through the gate electrode insulating layer 1006 can be clearly seen. In some embodiments, the gate electrode and the trench can be widened in the via position to better form a contact between the gate electrode and the gate metal through the via. The source region 1002 extends parallel to the first gate trench and the split gate trench in the body region 1003. The source via 1010 is formed in the substrate composition, passing through the source region 1002 and contacting at least the body region 1003, thereby allowing the source region and the body region to be conductively coupled to the source metal and form a short source body of an anti-parallel diode. In addition, the drift region 1004 and the substrate region 1005 can be seen.

[0063] Fig.11AA top view of a planar gate layout for a programmable gate design of a dual-gate transistor according to one aspect of the present disclosure is shown. The top view of the layout of a planar gate device is very similar to the layout of a trench gate or SGT device. In this embodiment, the gate electrode is located on the surface of the substrate composition, and the gate insulating layer separates the gate electrode from the surface of the substrate composition. The gate electrodes are arranged in a line on the substrate composition, alternating between the first gate electrode 1101 and the split gate electrodes 1102, 1103. The connecting portion of the first gate electrode 1105 extends perpendicular to the first gate electrode line 1101 connecting them.

[0064] In addition, the connecting portion of the first gate electrode 1105 connects the shorter portion of the split gate electrode 1102 on one side of the dielectric wall 1104, making it a part of the first gate electrode. The longer portion of the split gate electrode 1103 on the other side of the dielectric wall 1104 can have an extended connection area 1111 to allow easier connection to the gate metal through a via in the insulating layer (not shown in the figure). In this embodiment, the dielectric wall 1104 is formed by a gate insulating layer stacked on the surface of the substrate. The dielectric wall insulates the shorter portion 1103 of the split gate electrode from the longer portion 1102 of the split gate electrode.

[0065] In this view, source regions 1106 are visible. Source regions 1106 are formed near the sides of gates 1101, 1102, 1103 in body regions 1107, with a portion of body regions 1107 exposed, allowing a short circuit to be formed between the source and body regions with source metal (not shown).

[0066] Fig. 11B A side cross-sectional view of a programmable gate design of a dual-gate planar gate transistor according to one aspect of the present disclosure is shown. As shown, a first gate electrode 1101 is disposed on the top surface of a substrate composition above a gate electrode insulating layer 1110. In addition, a split gate electrode (not shown) is disposed on the surface of the substrate composition and above the electrode insulating layer. The gate electrode insulating layer 1110 may surround the first gate electrode 1101 and the split gate electrode (not shown) and electrically isolate them from the substrate composition. A portion of the drift region 1108 may be located below the gate insulating layer 1110 in the substrate composition. The body region 1107 is formed in the upper portion of the drift region 1108, and the source region 1106 is formed in the upper portion of the body region 1106. The drift region 1108 may be formed on a substrate layer 1109.

[0067] As shown, a dielectric wall 1104 is formed on the top surface of the substrate composition. The dielectric wall may be formed together with the gate insulating layer, and additional insulating material may be deposited on the gate insulating layer to form the dielectric wall.

[0068] Although the embodiments shown throughout the present disclosure depict substrates having a fixed ratio of first gate trenches to split gate trenches (or lines in the case of a planar gate layout), aspects of the present disclosure are not limited thereto, and there may be any number of first gate lines to split gate lines, such as, and without limitation, there may be one first gate trench for every two split gate trenches, every three split gate trenches, every four split gate trenches, and the like. It should also be understood that a greater number of split gate trenches to first gate trenches may allow for greater customizability, but there may be some loss in gate width due to the loss of space in the split gate trenches due to the dielectric walls. The first gate trenches limit the overall ratio of first gate trenches to second gate trenches, so in the embodiments discussed, the first trenches may constitute more substrate area. Therefore, the first gate may be able to accommodate higher loads than the second gate, while the second gate may have less capacitive losses and be more efficient at low loads.

[0069] Fig.11A and Figure 3 The layout shown advantageously allows the ratio of the first gate to the second gate to be selected by changing the metal layout. This is particularly useful because it allows a single substrate layout to be used for different applications that may have different load requirements. In existing devices, new gate layouts will be required to accommodate devices with different load requirements. In order to meet the requirements, the gate needs to be redesigned, which means that for each application with different requirements, a completely new device must be designed and built. Various aspects of the present disclosure provide a substrate area layout that is universal and can be easily customized for different applications with different load requirements without completely redesigning. Here, the last few steps in production, namely the gate metal mask and the gate metal deposition, can be changed to meet the requirements of a specific application. This saves time in redesigning the gate layout and also saves money in developing new production equipment and samples. Although various implementations related to MOSFET devices with multiple gates are discussed herein, those skilled in the art will recognize that this implementation can be applied to other types of transistors, such as insulated gate bipolar transistors (IGBTs) and junction field effect transistors (JFETs).

[0070] While the above is a complete description of the preferred embodiments of the present invention, various alternatives, modifications and equivalents may be used. Therefore, the scope of the present invention should not be determined by reference to the above description, but should be determined by reference to the full scope of the appended claims and their equivalents. Any feature described herein, whether preferred or not, may be combined with any other feature described herein, whether preferred or not. In the following claims, the indefinite article "a" or "an" refers to the quantity of one or more items following the clause, unless otherwise expressly stated. The appended claims should not be interpreted as including means plus function limitations unless such limitation is expressly stated in a given claim using the phrase "meant to be".

Claims

1. A multi-gate transistor, comprising: A common substrate, a source, a drain, a body, a first gate and a second gate, wherein the first gate and the second gate are arranged in a collinear manner along a horizontal plane of the common substrate and are separated by a dielectric wall, and wherein the dielectric wall provides electrical isolation between the first gate electrode and the second gate electrode.

2. The transistor of claim 1, further comprising a gate control, wherein the first gate electrode is connected to an output terminal of the gate control, the second gate electrode is connected to the output terminal via a switch, and when the switch is turned off, the first gate electrode and the second gate electrode are electrically isolated from each other. 3 . The transistor of claim 1 , wherein the first gate electrode and the second gate electrode are collinearly arranged in two or more lines along a horizontal plane of the common substrate.

4. The transistor of claim 3 further comprising a first gate metal and a second gate metal, wherein a ratio of the first gate electrode to the second gate electrode in the region of the common substrate depends on the number of lines of the first gate electrode material that are in electrical contact with the first gate metal.

5. The transistor of claim 4, wherein the ratio of the first gate to the second gate in the region of the common substrate is further dependent upon the number of lines of second gate electrode material in electrical contact with the second gate metal. 6 . The transistor of claim 1 , wherein the first gate electrode comprises a first gate polysilicon layer disposed in a gate trench, and the second gate electrode comprises a second gate polysilicon disposed in the gate trench.

7. The transistor of claim 6, further comprising a shield electrode in the gate trench, wherein the shield electrode extends below both the first gate electrode and the second gate electrode in the gate trench, wherein: The shielding circuit is electrically isolated from the first gate electrode and the second gate electrode.

8. The transistor of claim 1, wherein the first gate electrode comprises a first gate polysilicon layer disposed over an insulating layer on the horizontal plane of the common substrate, and wherein the second gate electrode comprises a second gate polysilicon layer disposed over the insulating layer.

9. A method of manufacturing a multi-gate transistor, comprising: a) preparing a gate trench on a substrate; b) depositing an insulating layer in the gate trench; c) selectively etching the insulating layer to form a dielectric wall in a portion of the gate trench; d) forming a gate electrode insulating layer in the gate trench, and depositing a conductive layer on the gate electrode insulating layer; and e) etching a portion of the conductive layer to form a first gate electrode and a second gate electrode, wherein the dielectric wall separates the first gate electrode from the second gate electrode.

10. The method of claim 9, further comprising depositing a shielding electrode insulating layer at the bottom of the trench and forming a shielding electrode on the shielding electrode insulating layer, wherein: The insulating layer is formed over a shielding electrode, and the shielding electrode extends under the first gate and the second gate.

11. The method of claim 9, further comprising a) forming at least one additional gate trench in the substrate, wherein b) comprises depositing an insulating layer on a surface of the at least one additional gate trench, wherein c) comprises selectively etching the at least one additional gate trench to form a dielectric wall in a portion of the at least one additional gate trench.

12. The method of claim 11, further comprising depositing a top insulating layer on the first gate electrode and the second gate electrode, wherein the top insulating layer comprises a via exposing a portion of the first gate electrode, and forming a first gate metal on the top insulating layer.

13. The method of claim 12, wherein: The ratio of the first gate electrode to the second gate electrode in the region of the common substrate depends on the number of lines of the first gate electrode material that are in electrical contact with the first gate metal.

14. The method of claim 13 further includes forming a second gate metal on the top insulating layer, and wherein the ratio of the first gate electrode to the second gate electrode in the region of the common substrate further depends on the number of lines of second gate electrode material that are in electrical contact with the second gate metal.

15. A multi-gate transistor comprising: a lightly doped epitaxial layer of a first conductivity type covering a heavily doped common substrate of the first conductivity type; a first trench gate disposed in a first trench portion extending into the epitaxial layer, and a second trench gate disposed in a second trench portion extending into the epitaxial layer, wherein the first trench gate is electrically isolated from the second trench gate; A source layer of the first conductivity type is disposed on the top surface of the epitaxial layer surrounding the first trench gate and the second trench gate, and the source layer regions separated by the first trench portion and the second trench portion are electrically connected; as well as A common drain is arranged on the bottom of the common substrate.

16. The transistor of claim 15, further comprising a body layer having a second conductivity type disposed in the epitaxial layer below the source layer.

17. The transistor of claim 15, wherein the first trench portion and the second trench portion are collinearly aligned along a horizontal plane of the common substrate and are separated by a dielectric wall, wherein the dielectric wall provides electrical isolation between the first gate and the second gate. 18 . The transistor of claim 17 , wherein the first trench gate and the second trench gate are collinearly arranged in two or more lines along the horizontal plane of the common substrate.

19. The transistor of claim 18, wherein the first trench gate comprises a first gate polysilicon layer disposed in the first channel portion, and the second trench gate comprises a second gate polysilicon disposed within the second trench portion, wherein the dielectric wall separates the first gate polysilicon layer from the second gate polysilicon layer.

20. The transistor of claim 19, further comprising a shield electrode extending below the first trench gate and the second trench gate in the gate trench, wherein the shield electrode is electrically isolated from the first trench gate and the second trench gate.

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