Back contact solar cell and manufacturing method thereof

Abstract

The invention relates to a back contact solar cell and a manufacturing method thereof. The manufacturing method comprises the following steps: providing a substrate, and forming an intrinsic semiconductor layer on the substrate; a first blocking pattern is formed on the side, away from the substrate, of the intrinsic semiconductor layer through printing, and the first blocking pattern is provided with a first opening pattern used for defining the forming position of a first emitting electrode; performing first polarity doping on the intrinsic semiconductor layer based on the first opening pattern to form a first emitter; removing the first blocking pattern; printing and forming a second blocking pattern on one side, away from the substrate, of the intrinsic semiconductor layer, wherein the second blocking pattern is provided with a second opening pattern used for defining a second emitting electrode forming position; performing second polarity doping on the intrinsic semiconductor layer based on the second opening pattern to form a second emitter; the second barrier pattern is patterned to at least expose the second emitter. The manufacturing method is used for simplifying the battery preparation process and reducing the process difficulty.

Description

Technical Field

[0001] The present disclosure relates to the technical field of solar cells, and in particular to a back-contact solar cell and a method for manufacturing the same. Background Art

[0002] IBC (Interdigitated Back Contact) solar cells have no grid lines on the front, and the back has positive and negative metal grid lines arranged in a finger-like cross pattern. As a platform-type photovoltaic cell technology, IBC cells can be superimposed with various high-efficiency cell technologies to further improve the photoelectric conversion efficiency. For example, IBC technology is combined with HJT (Heterojunction Technology) cells to make HBC (Hybrid Back Contact) cells. Or, for example, IBC technology is combined with TOPCON (tunneling oxide passivation contact) cells to make TBC (tunneling oxide back contact) cells. However, the preparation cost of HBC cells and TBC cells is high, and the preparation process is complicated, which limits their large-scale industrialization process. Summary of the invention

[0003] Based on this, the embodiments of the present disclosure provide a back-contact solar cell and a method for manufacturing the same, which can simplify the cell preparation process and reduce the process difficulty, thereby improving the preparation efficiency and reducing the preparation cost, thereby facilitating the large-scale industrialization process of the cell.

[0004] In order to achieve the above objectives, in a first aspect, an embodiment of the present disclosure provides a method for manufacturing a back-contact solar cell, comprising the following steps:

[0005] A substrate is provided, and an intrinsic semiconductor layer is formed on the substrate.

[0006] A first barrier pattern is formed by printing on a side of the intrinsic semiconductor layer away from the substrate. The first barrier pattern has a first opening pattern for defining a first emitter formation position.

[0007] The intrinsic semiconductor layer is doped with a first polarity based on the first opening pattern to form a first emitter.

[0008] The first barrier pattern is removed.

[0009] A second blocking pattern is formed by printing on a side of the intrinsic semiconductor layer away from the substrate. The second blocking pattern has a second opening pattern for defining a second emitter formation position.

[0010] The intrinsic semiconductor layer is doped with a second polarity based on the second opening pattern to form a second emitter.

[0011] The second blocking pattern is patterned to expose at least the second emitter.

[0012] In some embodiments of the present disclosure, the second barrier pattern is formed by printing on the side of the intrinsic semiconductor layer away from the substrate, including: printing to form a second barrier pattern with equal thickness covering the first emitter and the isolation region. The isolation region is a region where the first barrier pattern and the second barrier pattern overlap. Accordingly, the second barrier pattern is patterned, including: removing the second barrier pattern.

[0013] Or, in some other embodiments of the present disclosure, the second barrier pattern is formed by printing on the side of the intrinsic semiconductor layer away from the substrate, including: printing to form a first sub-barrier pattern covering the first emitter and a second sub-barrier pattern covering the isolation region, wherein the thickness of the second sub-barrier pattern is greater than the thickness of the first sub-barrier pattern, and the difference in thickness between the second sub-barrier pattern and the first sub-barrier pattern is greater than or equal to a target threshold. The isolation region is an area where the first barrier pattern and the second barrier pattern overlap repeatedly. Accordingly, the second barrier pattern is patterned, including: removing the first sub-barrier pattern and a portion of the thickness of the second sub-barrier pattern, so that the second sub-barrier pattern covering the isolation region constitutes a barrier layer.

[0014] In some embodiments of the present disclosure, patterning the second barrier pattern includes: performing a wet etching process on the second barrier pattern.

[0015] In some embodiments of the present disclosure, the first barrier pattern and the second barrier pattern are formed by performing a screen printing process on a patternable diffusion barrier paste.

[0016] In some embodiments of the present disclosure, the diffusion barrier slurry includes a thermally curable slurry or a photocurable slurry, and the diffusion barrier slurry forms a corresponding barrier pattern after being cured once.

[0017] Correspondingly, the manufacturing method of the back-contact solar cell provided by the embodiment of the present disclosure also includes: in the process of performing first polarity doping on the intrinsic semiconductor layer based on the first opening pattern, secondary curing of the first barrier pattern; in the process of performing second polarity doping on the intrinsic semiconductor layer based on the second opening pattern, secondary curing of the second barrier pattern.

[0018] Optionally, the process temperature during the secondary curing of the second barrier pattern is greater than 500° C.

[0019] In some embodiments of the present disclosure, the diffusion barrier slurry comprises: an organosilicon reactant, an oxide filler and an additive. The organosilicon reactant comprises: one or more of allyl-modified methyl silicone oil, vinyl silicone oil or hydrogen-containing silicone oil. The oxide filler comprises: one or more of silicon dioxide, modified silicone resin or aluminum oxide. The additive comprises: a coupling agent, a catalyst or an inhibitor.

[0020] Optionally, the mass proportion of the organic silicon reactant in the diffusion barrier slurry ranges from 30% to 50%.

[0021] Optionally, the mass proportion of the oxide filler in the diffusion barrier slurry ranges from 10% to 50%.

[0022] Optionally, the mass proportion of the additive in the diffusion barrier slurry ranges from 0.1% to 2%.

[0023] In some embodiments of the present disclosure, the diffusion barrier slurry further comprises: a solvent for dissolving the organosilicon reactant, the oxide filler and the additive; wherein the solvent comprises: one or more of toluene, xylene, ethylene glycol or glycerol.

[0024] Optionally, the mass proportion of the solvent in the diffusion barrier slurry ranges from 0% to 30%.

[0025] In some embodiments of the present disclosure, the substrate has a first surface and a second surface opposite to each other. The first emitter and the second emitter are formed based on the intrinsic semiconductor layer on the first surface of the substrate.

[0026] Accordingly, the method for manufacturing a back-contact solar cell provided in the embodiment of the present disclosure further includes the following steps:

[0027] The second surface is subjected to a velvet treatment to form a velvet structure.

[0028] A passivation layer and an anti-reflection layer are stacked and formed on the side of the velvet structure away from the substrate and the sides of the first emitter, the isolation region and the second emitter away from the substrate.

[0029] A first electrode connected to the first emitter is formed on a side of the first emitter away from the substrate, and a second electrode connected to the second emitter is formed on a side of the second emitter away from the substrate.

[0030] In a second aspect, the embodiments of the present disclosure further provide a back-contact solar cell, which can be prepared by the manufacturing method of the back-contact solar cell described in some of the above embodiments. The back-contact solar cell comprises: a substrate, and a first emitter, a second emitter, and an isolation region located on the same side of the substrate; wherein the first emitter and the second emitter are different doped regions formed by the same intrinsic semiconductor layer based on corresponding opening patterns in different blocking patterns; and the isolation region is located between the first emitter and the second emitter, and is a non-doped region of the same intrinsic semiconductor layer.

[0031] In some embodiments of the present disclosure, the back contact solar cell further comprises: a barrier layer, a first electrode, and a second electrode. The barrier layer covers the isolation region and is formed based on a portion of the barrier pattern. The first electrode is located on a side of the first emitter away from the substrate and is connected to the first emitter. The second electrode is located on a side of the second emitter away from the substrate and is connected to the second emitter.

[0032] Optionally, a height of the barrier layer is greater than a height of the first electrode and / or the second electrode.

[0033] The embodiments of the present disclosure may or at least have the following advantages:

[0034] In the embodiment of the present disclosure, after forming an intrinsic semiconductor layer on a substrate, a corresponding blocking pattern can be formed by two printing processes and the intrinsic semiconductor layer can be doped with different polarities based on the opening pattern in the blocking pattern, so as to prepare a first emitter, an isolation region, and a second emitter on the same side of the substrate. In this way, the process provided by the embodiment of the present disclosure is simple and easy to implement, which not only reduces the dependence on the use of laser patterning technology, has a more efficient patterning process, and avoids the use of expensive equipment, but also can effectively control the film thickness of the blocking pattern through the printing process to solve the problem of high process precision of the mask in the high-temperature process, and has a production capacity advantage. In addition, the embodiment of the present disclosure can also avoid opening the film on the substrate and forming etching grooves due to wet etching, so as to avoid the problem of substrate fragmentation caused by the depth of the etching grooves, which can effectively reduce the fragmentation rate and effectively improve the problem of rework difficulties.

[0035] In summary, the embodiments of the present disclosure can simplify the battery manufacturing process and reduce the difficulty of the process, thereby improving the manufacturing efficiency and reducing the manufacturing cost, thereby facilitating the large-scale industrialization process of the battery.

[0036] The details of one or more embodiments of the present disclosure are set forth in the following drawings and description. Other features, objects, and advantages of the present disclosure will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0038] Figure 1 A schematic flow chart of a method for manufacturing a back-contact solar cell provided in some embodiments;

[0039] Figure 2A schematic cross-sectional view of a structure obtained after forming an intrinsic semiconductor layer provided in some embodiments;

[0040] Figure 3 is a schematic cross-sectional view of a structure obtained after forming a first barrier pattern provided in some embodiments;

[0041] Figure 4 is a schematic cross-sectional view of a structure obtained after forming a first emitter provided in some embodiments;

[0042] Figure 5 is a schematic cross-sectional view of a structure obtained after removing the first barrier pattern provided in some embodiments;

[0043] Figure 6 is a schematic cross-sectional view of a structure obtained after forming a second barrier pattern provided in some embodiments;

[0044] Figure 7 is a schematic cross-sectional view of a structure obtained after forming a second emitter provided in some embodiments;

[0045] Figure 8 is a schematic cross-sectional view of a structure obtained after removing the second blocking pattern provided in some embodiments;

[0046] Fig. 9 A schematic cross-sectional view of a structure obtained after forming a suede structure, a passivation layer and an anti-reflection layer provided in some embodiments;

[0047] Fig.10 is a schematic cross-sectional view of a structure obtained after forming a first electrode and a second electrode provided in some embodiments; and, Fig.10 It is also a schematic cross-sectional structure diagram of a back-contact solar cell provided in some embodiments;

[0048] Fig.11 is a cross-sectional schematic diagram of another structure obtained after forming a second barrier pattern provided in some embodiments;

[0049] Fig.12 A schematic cross-sectional view of a structure obtained after forming a barrier layer provided in some embodiments;

[0050] Fig.13 A schematic diagram of the cross-sectional structure of another back-contact solar cell provided in some embodiments.

[0051] Description of reference numerals:

[0052] 1-substrate, 11-tunneling oxide layer, 2-intrinsic semiconductor layer, 21-first doping layer, 31-first barrier pattern, K1-first opening pattern, 32-second barrier pattern, 321-first sub-barrier pattern, 322-second sub-barrier pattern, K2-second opening pattern, 41-first emitter, 411-first diffusion layer, 42-second emitter, 421-second diffusion layer, 5-isolation region, 6-barrier layer, 71-texture structure, 72-passivation layer, 73-anti-reflection layer, 81-first electrode, 82-second electrode. DETAILED DESCRIPTION

[0053] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present disclosure are shown in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0054] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0055] It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish an element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below can be represented as a second element, component, region, layer or part.

[0056] It should be understood that when an element is considered to be "connected" to another element, it can be directly connected to the other element, or connected to the other element through an intermediate element. In addition, the "connection" in the following embodiments should be understood as "electrical connection", "communication connection", etc. if there is transmission of electrical signals or data between the connected objects.

[0057] It should be understood that the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0058] IBC cells superimposed with other high-efficiency cell technologies can further improve the photoelectric conversion efficiency, but it is also easy to cause problems such as high preparation costs and complex preparation processes. Taking the TBC cell after combining IBC technology with TOPCON cells as an example, the manufacturing method of TBC cells often requires multiple patterning with lasers, and uses a wet etching process to remove polysilicon of different doping types in specific areas. However, due to the complexity of the back contact (BC) pattern and the large film opening area, there are high requirements for the quality of the mask layer (such as density, film thickness, uniformity, etc.), laser patterning accuracy, patterning speed and laser damage control, which are prone to problems such as narrow process window, low fault tolerance, low production capacity and increased equipment cost. In addition, silicon wafers after wet etching often form grooves of a certain depth on their surface, which increases the probability of fragmentation and the difficulty of rework, further increasing the preparation cost of the battery and limiting the improvement of yield.

[0059] Based on this, the embodiments of the present disclosure provide a back contact (BC) solar cell and a method for manufacturing the same, which can simplify the cell preparation process and reduce the process difficulty, thereby improving the preparation efficiency and reducing the preparation cost, thereby facilitating the large-scale industrialization of the cell.

[0060] See also Figure 1 The embodiment of the present disclosure provides a method for manufacturing a back-contact solar cell, comprising the following steps S100 to S700.

[0061] Step S100 , providing a substrate, and forming an intrinsic semiconductor layer on the substrate.

[0062] For example, see Figure 2 The substrate 1 has a first surface and a second surface opposite to each other. The intrinsic semiconductor layer 2 is formed on the substrate 1 by first polishing the first surface and the second surface of the substrate 1, and then sequentially stacking the tunneling oxide layer 11 and the intrinsic semiconductor layer 2 on the first surface and the second surface of the substrate 1. Here, the deposition thickness of the tunneling oxide layer 11 and the intrinsic semiconductor layer 2 can be set to match the requirements.

[0063] Optionally, the tunneling oxide layer 11 includes but is not limited to a silicon oxide (SiO 2 ) layer.

[0064] Optionally, the intrinsic semiconductor layer 2 includes but is not limited to a polycrystalline silicon (i-poly) layer.

[0065] In some examples, a stacked structure of tunneling oxide layer 11 / intrinsic semiconductor layer 2 / tunneling oxide layer 11 / intrinsic semiconductor layer 2 may be prepared on the first surface and the second surface of the substrate 1 .

[0066] In step S200, a first barrier pattern is formed by printing on a side of the intrinsic semiconductor layer facing away from the substrate. The first barrier pattern has a first opening pattern for defining a position for forming a first emitter.

[0067] For example, see Figure 3 , the first barrier pattern 31 is formed on a side of the intrinsic semiconductor layer 2 away from the first surface of the substrate 1 .

[0068] Alternatively, the first barrier pattern 31 may be formed by screen printing a patternable diffusion barrier paste. The first opening pattern K1 of the first barrier pattern 31 has the same or substantially the same shape, profile and size as the first emitter.

[0069] Step S300 , performing first polarity doping on the intrinsic semiconductor layer based on the first opening pattern to form a first emitter.

[0070] For example, see Figure 4 Since the first barrier pattern 31 is formed on the side of the intrinsic semiconductor layer 2 away from the first surface of the substrate 1, when the intrinsic semiconductor layer 2 is doped with the first polarity based on the first opening pattern K1 to form the first emitter 41, the intrinsic semiconductor layer 2 located on the second surface side of the substrate 1 is also doped with the first polarity to form the first doping layer 21.

[0071] Optionally, see Figure 4 At the same time or after the intrinsic semiconductor layer 2 is doped with the first polarity based on the first opening pattern K1 to form the first emitter 41 , a portion of the substrate 1 corresponding to the adjacent first emitter 41 may also be doped and diffused to form a first diffusion layer 411 .

[0072] Step S400, removing the first blocking pattern.

[0073] For example, please combine Figure 4 and Figure 5 It is understood that the first barrier pattern 31 may be removed by cleaning.

[0074] Optionally, the first doping layer 21 and the tunneling oxide layer 11 located on one side of the second surface of the substrate 1 may be cleaned and removed simultaneously with the first barrier pattern 31 .

[0075] Step S500: Printing a second barrier pattern on a side of the intrinsic semiconductor layer away from the substrate. The second barrier pattern has a second opening pattern for defining a second emitter formation position.

[0076] For example, see Figure 6 The second barrier pattern 32 is formed on the side of the intrinsic semiconductor layer 2 away from the first surface of the substrate 1 ; that is, the second barrier pattern 32 and the first barrier pattern 31 are formed on the same side of the substrate 1 in a time-sharing manner.

[0077] Alternatively, the second barrier pattern 32 may be formed by screen printing a patternable diffusion barrier paste. The second opening pattern K2 of the second barrier pattern 32 has the same or substantially the same shape, profile and size as the second emitter.

[0078] Step S600 , performing second polarity doping on the intrinsic semiconductor layer based on the second opening pattern to form a second emitter.

[0079] For example, the second polarity doping and the first polarity doping have different doping types. For example, when one of the second polarity doping and the first polarity doping is P-type doping, the other is N-type doping.

[0080] Optionally, see Figure 7 At the same time or after the second polarity doping is performed on the intrinsic semiconductor layer 2 based on the second opening pattern K2 to form the second emitter 42 , a portion of the substrate 1 corresponding to the adjacent second emitter 42 may also be doped and diffused to form a second diffusion layer 421 .

[0081] Optionally, the second opening pattern K2 of the second barrier pattern 32 is spaced apart from the first opening pattern K1 of the first barrier pattern 31 in the previous step S200 in a direction parallel to the substrate 1. Accordingly, after forming the second emitter 42, the intrinsic semiconductor layer 2 located within the aforementioned space between the first emitter 41 and the second emitter 42 constitutes an isolation region 5.

[0082] Step S700: patterning the second blocking pattern to at least expose the second emitter.

[0083] For example, please combine Figure 7 and Figure 8 It is understood that patterning the second barrier pattern 32 includes performing a wet etching process on the second barrier pattern 32 .

[0084] Here, optionally, the second barrier pattern 32 may be removed by cleaning through a wet etching process.

[0085] Or, optionally, the second barrier pattern 32 may be partially retained, for example, the second barrier pattern 32 covering the isolation region 5 may be retained to form a barrier layer.

[0086] In the embodiment of the present disclosure, after the intrinsic semiconductor layer 2 is formed on the substrate 1, two printing processes can be used to form the corresponding blocking patterns (31 and 32) and the intrinsic semiconductor layer 2 can be doped with different polarities based on the opening patterns (K1 and K2) in the blocking patterns (31 and 32), so as to prepare the first emitter 41, the isolation region 5 and the second emitter 42 on the same side of the substrate 1. In this way, the process provided by the embodiment of the present disclosure is simple and easy to implement, which can not only reduce the dependence on the use of laser patterning process, but also have a more efficient patterning process, while avoiding the use of expensive equipment, and can also effectively control the film thickness of the blocking pattern through the printing process to solve the problem of high process accuracy of the mask in the high temperature process, and has a production capacity advantage. In addition, the embodiment of the present disclosure can also avoid opening the film on the substrate and forming the etching groove due to wet etching, so as to avoid the problem of substrate fragmentation caused by the depth of the etching groove, which can effectively reduce the fragmentation rate and effectively improve the problem of rework difficulty.

[0087] In summary, the embodiments of the present disclosure can simplify the battery manufacturing process and reduce the difficulty of the process, thereby improving the manufacturing efficiency and reducing the manufacturing cost, thereby facilitating the large-scale industrialization process of the battery.

[0088] It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0089] In some embodiments of the present disclosure, the first emitter 41 and the second emitter 42 are formed based on the intrinsic semiconductor layer 2 on the first surface of the substrate 1. Figure 8~Figure 10 The method for manufacturing a back-contact solar cell provided in the embodiment of the present disclosure further includes the following steps S800 to 1000.

[0090] Step S800, see Figure 8 , the second surface of the substrate 1 is subjected to a velvet treatment to form a velvet structure 71 .

[0091] Optionally, the patterning of the second barrier pattern 32 in step S700 may be performed in the same process and step as the texturing treatment of the second surface of the substrate 1 .

[0092] Step S900, see Fig. 9 A passivation layer 72 and an anti-reflection layer 73 are stacked on the side of the suede structure 71 away from the substrate 1 and the sides of the first emitter 41 , the isolation region 5 and the second emitter 43 away from the substrate 1 .

[0093] Optionally, the passivation layer 72 includes a dielectric layer such as an oxide (eg, silicon oxide) layer or a nitride (eg, silicon nitride) layer.

[0094] Optionally, the anti-reflection layer 73 includes but is not limited to a silicon oxynitride layer.

[0095] Step S1000, see Fig.10 A first electrode 81 connected to the first emitter 41 is formed on a side of the first emitter 41 away from the substrate 1 , and a second electrode 82 connected to the second emitter 42 is formed on a side of the second emitter 42 away from the substrate 1 .

[0096] Optionally, the first electrode 81 and the second electrode 82 are formed of a conductive material, such as a metal material.

[0097] Optionally, the first electrode 81 and the second electrode 82 match the doping polarity of the corresponding emitter and can be used as a positively charged gate line and a negatively charged gate line respectively.

[0098] It is worth mentioning that in some embodiments of the present disclosure, the isolation region 5 is a region where the first barrier pattern 31 and the second barrier pattern 32 overlap each other. The formation process and patterning process of the second barrier pattern 32 can be implemented in different ways.

[0099] For some possible implementations, see Figure 6 In step S500 , a second barrier pattern 32 is formed by printing on a side of the intrinsic semiconductor layer 2 away from the substrate 1 , including: forming the second barrier pattern 32 with equal thickness by printing to cover the first emitter 41 and the isolation region 5 .

[0100] Accordingly, see Figure 8 In step S700 , the second barrier pattern 32 is patterned, including: removing the second barrier pattern 32 .

[0101] For other possible implementations, see Fig.11 In step S500, a second barrier pattern 32 is formed by printing on a side of the intrinsic semiconductor layer 2 facing away from the substrate 1, including: printing to form a first sub-barrier pattern 321 covering the first emitter 41 and a second sub-barrier pattern 322 covering the isolation region 5, wherein the thickness of the second sub-barrier pattern 322 is greater than the thickness of the first sub-barrier pattern 321, and the difference in thickness between the second sub-barrier pattern 322 and the first sub-barrier pattern 321 is greater than or equal to a target threshold.

[0102] Here, the target threshold is, for example, the height of the first electrode 81 and / or the second electrode 82 .

[0103] Illustratively, the height of the first electrode 81 is the same as the height of the second electrode 82 .

[0104] By way of example, the height of the first electrode 81 is different from the height of the second electrode 82 , and the target threshold is, for example, the maximum height of the first electrode 81 and the second electrode 82 .

[0105] Accordingly, please combine Fig.11 and Fig.12 It is understood that the patterning of the second barrier pattern 32 in step S700 includes: removing the first sub-barrier pattern 321 and a portion of the thickness of the second sub-barrier pattern 322 , so that the remaining second sub-barrier pattern 322 covering the isolation region 5 forms the barrier layer 6 .

[0106] See also Fig.13 After forming the barrier layer 6, the aforementioned steps S800 to S1000 can be adaptively performed to form a suede structure 71, a passivation layer 72, an anti-reflection layer 73, a first electrode 81, and a second electrode 82, etc., so as to prepare a back contact solar cell. The passivation layer 72 and the anti-reflection layer 73 are also sequentially stacked and cover the barrier layer 6.

[0107] For example, the thickness of the second barrier pattern 32 ranges from 0.1 μm to 50 μm.

[0108] In some examples, the second barrier pattern 32 includes a first sub-barrier pattern 321 and a second sub-barrier pattern 322 ; wherein the first sub-barrier pattern 321 has a thickness ranging from 0.1 μm to 5 μm, and the second sub-barrier pattern 322 has a thickness ranging from 0.1 μm to 50 μm.

[0109] In the embodiment of the present disclosure, a barrier layer 6 is formed based on the retained second barrier pattern 32, and the height of the barrier layer 6 is ensured to be greater than the height of the first electrode 81 and / or the second electrode 82. The barrier layer 6 can be used as an isolation structure between adjacent cells when multiple cells are stacked in a back-contact solar cell to replace isolation paper, thereby reducing the production cost of the back-contact solar cell.

[0110] It should be supplemented that, in the above-mentioned embodiment of the present disclosure, the first barrier pattern 31 and the second barrier pattern 32 are formed by performing a screen printing process on a patternable diffusion barrier paste.

[0111] For example, the diffusion barrier paste includes a thermal curing paste or a photocuring paste. The diffusion barrier paste can form a corresponding barrier pattern after being cured once.

[0112] In some examples, the diffusion barrier slurry is a thermal curing slurry, and the process temperature of the diffusion barrier slurry during the primary curing thereof can be rapidly cured within a temperature range of 50° C. to 250° C., for example.

[0113] Optionally, the process temperature of the diffusion barrier slurry during its primary curing ranges from 150° C. to 250° C.

[0114] On this basis, the manufacturing method of the back-contact solar cell provided in the embodiment of the present disclosure also includes: in the process of performing first polarity doping on the intrinsic semiconductor layer 2 based on the first opening pattern K1, secondary curing of the first barrier pattern 31; in the process of performing second polarity doping on the intrinsic semiconductor layer 2 based on the second opening pattern K2, secondary curing of the second barrier pattern 32.

[0115] Optionally, the process temperature when performing secondary curing on the first barrier pattern 31 and the second barrier pattern 32 is greater than 500° C., for example, may be the same as the process temperature when performing the first polarity doping and / or the second polarity doping.

[0116] For example, the thickness of the first barrier pattern 31 ranges from 0.1 μm to 5 μm.

[0117] For example, the thickness of the second barrier pattern 32 ranges from 0.1 μm to 50 μm.

[0118] In some examples, the second barrier pattern 32 includes a first sub-barrier pattern 321 and a second sub-barrier pattern 322 ; wherein the first sub-barrier pattern 321 has a thickness ranging from 0.1 μm to 5 μm, and the second sub-barrier pattern 322 has a thickness ranging from 0.1 μm to 50 μm.

[0119] The diffusion barrier slurry provided by the embodiment of the present disclosure has the characteristics of high temperature resistance, acid resistance (such as hydrofluoric acid HF) and secondary curing. The embodiment of the present disclosure can avoid the use of highly polluting slurry and easily realize the preparation of the corresponding barrier pattern through the screen printing process, which has a production capacity advantage.

[0120] In some embodiments of the present disclosure, the diffusion barrier slurry comprises: an organosilicon reactant, an oxide filler and an additive. Among them, the organosilicon reactant includes: one or more of allyl-modified methyl silicone oil, vinyl silicone oil or hydrogen-containing silicone oil. The oxide filler includes: one or more of silicon dioxide, modified silicone resin or aluminum oxide; or, the oxide filler can also be other high-temperature resistant oxide materials. Additives include: coupling agents, catalysts or inhibitors. Coupling agents include but are not limited to silane coupling agents. Catalysts include but are not limited to platinum catalysts. Inhibitors include but are not limited to MVCT inhibitors.

[0121] Optionally, the mass proportion of the organic silicon reactant in the diffusion barrier slurry ranges from 30% to 50%.

[0122] Optionally, the mass proportion of the oxide filler in the diffusion barrier slurry ranges from 10% to 50%.

[0123] Optionally, the mass proportion of the additive in the diffusion barrier slurry ranges from 0.1% to 2%.

[0124] In some embodiments of the present disclosure, the diffusion barrier slurry further comprises: a solvent for dissolving the organosilicon reactant, the oxide filler and the additive; wherein the solvent comprises: one or more of toluene, xylene, ethylene glycol or glycerol.

[0125] Optionally, the mass percentage of the solvent in the diffusion barrier slurry ranges from 0% to 30%. When the mass percentage of the solvent in the diffusion barrier slurry is 0%, it means that the diffusion barrier slurry can be prepared without solvent; for example, the diffusion barrier slurry can be prepared without solvent to produce an environmentally friendly slurry with low volatile organic compound (VOC).

[0126] The diffusion barrier slurry provided in the embodiment of the present disclosure can be cured once and then be cured again by using the high temperature in the polar doping process (for example, by breaking the Si-C bonds at high temperature and then rearranging them for secondary cross-linking), thereby forming a barrier pattern with silicon oxide as the main body (for example, the first barrier pattern 31 and the second barrier pattern 32 mentioned above). In this way, the first barrier pattern 31 and the second barrier pattern 32 are easy to react with hydrofluoric acid, so that wet etching is convenient for cleaning, removal or patterning. In addition, considering that there is still a main material in the diffusion barrier slurry that has not been effectively converted into silicon oxide, the system material based on the organic silicon reactant can be cleaned by alkali washing.

[0127] The following embodiments of the present disclosure exemplarily provide two different formulations and preparation processes of diffusion barrier slurries, and the relevant contents can be referred to in Table 1 and Table 2 respectively.

[0128] Table 1, Diffusion Barrier Slurry Formula 1:

[0129]

[0130] According to the above-mentioned diffusion barrier slurry formula 1, at room temperature (e.g. 25°C), use a stirrer to mix the organosilicon reactants, wherein the molar ratio of vinyl to hydrogen is 1:1, and add the oxide filler in batches, stir thoroughly for 2h-3h, and keep the stirring speed between 3000rpm-5000rpm. Then cool the mixed solution to room temperature or lower temperature, add the additive to the mixed solution, stir for about 30min, and perform degassing treatment to obtain a milky white ink (i.e., a diffusion barrier slurry for screen printing).

[0131] Table 2, formula 2 of diffusion barrier slurry:

[0132]

[0133] According to the above-mentioned formula 1 of the diffusion barrier slurry, at room temperature (e.g. 25°C), use a stirrer to mix the organosilicon reactants, wherein the molar ratio of vinyl to hydrogen is 1:1.2, and add the oxide filler in batches, fully stir for 2h-3h, and keep the stirring speed between 3000rpm-5000rpm. Then cool the mixed solution to room temperature or lower temperature, add the additive to the mixed solution, stir for about 30min, and perform degassing treatment to obtain a light yellow ink (i.e., a diffusion barrier slurry for screen printing).

[0134] Some embodiments of the present disclosure also provide a back-contact solar cell, which can be prepared by the manufacturing method of the back-contact solar cell described in some of the above embodiments. The technical advantages of the aforementioned manufacturing method are also possessed by the back-contact solar cell, which will not be described in detail here. In addition, the relevant features of each component of the back-contact solar cell can also be found in the relevant records in some of the above embodiments.

[0135] See also Fig.10 and Fig.13 The back-contact solar cell includes: a substrate 1 and a first emitter 41, a second emitter 42 and an isolation region 5 located on the same side of the substrate 1; wherein the first emitter 41 and the second emitter 42 are different doped regions formed by the same intrinsic semiconductor layer based on corresponding opening patterns in different blocking patterns; the isolation region 5 is located between the first emitter 41 and the second emitter 42 and is a non-doped region of the same intrinsic semiconductor layer.

[0136] For example, please refer to Fig.10 and Fig.13 The first emitter 41 , the second emitter 42 and the isolation region 5 are located on the same side of the first surface of the substrate 1 . The back contact solar cell further includes: a velvet structure 71 located on the second surface of the substrate 1 .

[0137] For example, please refer to Fig.10 and Fig.13 The back contact solar cell further includes: a passivation layer 72 and an anti-reflection layer 73 stacked and arranged on the side of the suede structure 71 away from the substrate 1 and the side of the first emitter 41, the isolation region 5 and the second emitter 43 away from the substrate 1.

[0138] Optionally, see Fig.10 and Fig.13 The back contact solar cell further includes: a first electrode 81 and a second electrode 82. The first electrode 81 is located on a side of the first emitter 41 away from the substrate 1 and connected to the first emitter 41. The second electrode 82 is located on a side of the second emitter 42 away from the substrate 1 and connected to the second emitter 42.

[0139] Optionally, the first electrode 81 and the second electrode 82 match the doping polarity of the corresponding emitter and can be used as a positively charged gate line and a negatively charged gate line respectively.

[0140] Optionally, see Fig.13 The back contact solar cell further includes a barrier layer 6. The barrier layer 6 covers the isolation region 5 and is formed based on a portion of the barrier pattern (for example, the second barrier pattern 32 in some of the aforementioned embodiments). The material for forming the barrier layer 6 can refer to the diffusion barrier slurry in some of the aforementioned embodiments.

[0141] Optionally, the height of the barrier layer 6 is greater than the height of the first electrode 81 and / or the second electrode 82 .

[0142] In some examples, the height of the first electrode 81 is the same as the height of the second electrode 82 .

[0143] In some other examples, the height of the first electrode 81 is different from the height of the second electrode 82 , and the height of the barrier layer 6 is greater than the maximum height of the first electrode 81 and the second electrode 82 .

[0144] In the embodiment of the present disclosure, the height of the barrier layer 6 is set to be greater than the height of the first electrode 81 and / or the second electrode 82. The barrier layer 6 can also be used as an isolation structure between adjacent battery cells when multiple battery cells are stacked in a back-contact solar cell to replace isolation paper, thereby reducing the production cost of the back-contact solar cell.

[0145] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0146] The above-described embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure shall be subject to the attached claims.

Claims

1. A method for manufacturing a back contact solar cell, characterized in that: include: Providing a substrate, and forming an intrinsic semiconductor layer on the substrate; Printing a first barrier pattern on a side of the intrinsic semiconductor layer away from the substrate; The first barrier pattern has a first opening pattern for defining a first emitter formation position; Based on the first opening pattern, the intrinsic semiconductor layer is doped with a first polarity to form a first emitter; removing the first blocking pattern; Printing a second blocking pattern on a side of the intrinsic semiconductor layer away from the substrate; The second barrier pattern has a second opening pattern for defining a second emitter formation position; Performing second polarity doping on the intrinsic semiconductor layer based on the second opening pattern to form a second emitter; The second blocking pattern is patterned to expose at least the second emitter.

2. The method for manufacturing a back contact solar cell according to claim 1, characterized in that: The step of printing and forming a second barrier pattern on a side of the intrinsic semiconductor layer away from the substrate comprises: printing and forming the second barrier pattern with equal thickness covering the first emitter and the isolation region; the step of patterning the second barrier pattern comprises: removing the second barrier pattern; Or, the step of printing and forming the second barrier pattern on the side of the intrinsic semiconductor layer away from the substrate comprises: printing and forming a first sub-barrier pattern covering the first emitter and a second sub-barrier pattern covering the isolation region, wherein the thickness of the second sub-barrier pattern is greater than the thickness of the first sub-barrier pattern, and the difference in thickness between the second sub-barrier pattern and the first sub-barrier pattern is greater than or equal to a target threshold; the step of patterning the second barrier pattern comprises: removing the first sub-barrier pattern and a portion of the thickness of the second sub-barrier pattern, so that the second sub-barrier pattern remaining to cover the isolation region constitutes a barrier layer; The isolation area is an area repeatedly covered by the first barrier pattern and the second barrier pattern.

3. The method for manufacturing a back contact solar cell according to claim 2, characterized in that: The patterning of the second barrier pattern includes: performing a wet etching process on the second barrier pattern.

4. The method for manufacturing a back contact solar cell according to claim 1, characterized in that: The first barrier pattern and the second barrier pattern are formed by performing a screen printing process on a patternable diffusion barrier paste.

5. The method for manufacturing a back contact solar cell according to claim 4, characterized in that: The diffusion barrier slurry includes a thermal curing slurry or a photocuring slurry; The diffusion barrier slurry forms a corresponding barrier pattern after primary curing; The manufacturing method also includes: in the process of performing first polarity doping on the intrinsic semiconductor layer based on the first opening pattern, performing secondary curing on the first barrier pattern; in the process of performing second polarity doping on the intrinsic semiconductor layer based on the second opening pattern, performing secondary curing on the second barrier pattern; wherein the process temperature during the secondary curing is greater than 500°C.

6. The method for manufacturing a back contact solar cell according to claim 4, characterized in that: The diffusion barrier slurry comprises: an organosilicon reactant, an oxide filler and an additive; Wherein, the organic silicon reactant includes: one or more of allyl-modified methyl silicone oil, vinyl silicone oil or hydrogen-containing silicone oil; The oxide filler includes: one or more of silicon dioxide, modified silicone resin or aluminum oxide; The additives include: coupling agents, catalysts or inhibitors; Wherein, the mass proportion of the organic silicon reactant in the diffusion barrier slurry ranges from 30% to 50%; The mass proportion of the oxide filler in the diffusion barrier slurry ranges from 10% to 50%; The mass percentage of the additive in the diffusion barrier slurry ranges from 0.1% to 2%.

7. The method for manufacturing a back contact solar cell according to claim 6, characterized in that: The diffusion barrier slurry further comprises: a solvent for dissolving the organosilicon reactant, oxide filler and additive; Wherein, the solvent includes: one or more of toluene, xylene, ethylene glycol or glycerol; The mass percentage of the solvent in the diffusion barrier slurry ranges from 0% to 30%.

8. The method for manufacturing a back-contact solar cell according to any one of claims 1 to 7, characterized in that: The substrate has a first surface and a second surface opposite to each other; the first emitter and the second emitter are formed based on the intrinsic semiconductor layer on the first surface; The manufacturing method further comprises: Performing a velvet treatment on the second surface to form a velvet structure; A passivation layer and an anti-reflection layer are stacked on the side of the suede structure away from the substrate and the sides of the first emitter, the isolation region and the second emitter away from the substrate; A first electrode connected to the first emitter is formed on a side of the first emitter away from the substrate, and a second electrode connected to the second emitter is formed on a side of the second emitter away from the substrate.

9. A back contact solar cell, characterized in that: include: A substrate and a first emitter, a second emitter and an isolation region located on the same side of the substrate; wherein the first emitter and the second emitter are different doped regions formed by the same intrinsic semiconductor layer based on corresponding opening patterns in different blocking patterns; the isolation region is located between the first emitter and the second emitter and is a non-doped region of the same intrinsic semiconductor layer.

10. The back contact solar cell according to claim 9, characterized in that: Also includes: a barrier layer, covering the isolation region and formed based on a portion of the barrier pattern; A first electrode, located on a side of the first emitter away from the substrate and connected to the first emitter; a second electrode, located on a side of the second emitter away from the substrate and connected to the second emitter; Wherein, the height of the blocking layer is greater than the height of the first electrode and / or the second electrode.

Images