Printed circuit board via structure with reduced insertion loss distortion

Abstract

A printed circuit board (PCB) includes: a plurality of stacked layers, each layer having a main plane defining a main plane of the PCB; a plurality of signal pads disposed on a signal pad layer of the PCB, the signal pad layer being parallel to a main plane of the PCB; and a plurality of signal vias, each of the plurality of signal vias having a longitudinal axis perpendicular to the main plane of the PCB, each signal via extending along the longitudinal axis through the plurality of layers, each respective signal via being electrically coupled to a respective signal pad of the plurality of signal pads, wherein at least one of the plurality of signal vias includes an added capacitive structure that forms a correction filter together with an inductance of the via to reduce insertion loss deviations of at least one broadband signal in the via.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This disclosure claims the benefit of co-pending, commonly assigned U.S. Provisional Patent Application No. 63 / 357,036, filed on June 30, 2022, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a printed circuit board (PCB) having a via configured to reduce distortion. More specifically, the present disclosure relates to a PCB having a via having a built-in capacitive structure to form an "in-via" correction filter with other components of the PCB to reduce distortion that causes insertion loss deviation and signal loss in the via. Background Art

[0004] The background description provided herein is for the purpose of generally presenting the context of the present disclosure. The work of the inventors, to the extent described in the background section, and insofar as it may not qualify as prior art at the time of filing, is neither explicitly nor implicitly admitted to be prior art to the subject matter of the present disclosure.

[0005] A printed circuit board (PCB) typically has multiple stacked layers, each with electrical traces or lines. Signal vias may be provided to conduct signals from one layer of the PCB to another layer of the PCB. The more layers a via passes through, i.e., the longer the via, the greater the likelihood of signal insertion deviation loss, which leads to signal integrity issues. Insertion loss deviation may worsen when the length of the signal via is comparable to the wavelength of the signal sent through the signal via. For example, a broadband signal may be sent through the signal via. If the insertion loss deviates non-monotonically over this frequency range, non-monotonic distortion may be introduced into the broadband signal. This may be of particular concern in the case of high-speed serial signals with data rates of approximately 200 Gbps or more. Summary of the invention

[0006] According to an implementation of the subject matter of the present disclosure, a printed circuit board includes a plurality of stacked layers, each layer having a corresponding main plane defining a main plane of the printed circuit board; a plurality of signal pads, which are arranged on a signal pad layer of the printed circuit board, the signal pad layer being parallel to the main plane of the printed circuit board; and a plurality of signal vias, each of the plurality of signal vias having a longitudinal axis perpendicular to the main plane of the printed circuit board, each signal via extending through the plurality of stacked layers along the longitudinal axis, each corresponding signal via being electrically coupled to a corresponding signal pad of the plurality of signal pads, wherein at least one of the plurality of signal vias includes an added capacitive structure, the added capacitive structure together with the inductance of the at least one signal via forms a correction filter to reduce the insertion loss deviation of at least one broadband signal in the at least one signal via.

[0007] In a first implementation of such a printed circuit board, for each corresponding signal via of at least one signal via, the added capacitive structure may include at least one additional pad, each additional pad extending from the corresponding signal via parallel to the main plane of the printed circuit board without being conductively coupled to any other part of the printed circuit board.

[0008] According to a first aspect of the first implementation, each respective additional pad may be formed in a respective conductive layer of a plurality of stacked layers of the printed circuit board.

[0009] According to a second aspect of the first implementation, the capacitance of each respective additional pad may be at least partially determined by at least one of: (a) a pad size of the respective additional pad and (b) a pad shape of the respective additional pad.

[0010] According to a third aspect of the first implementation, each corresponding additional pad may be disposed at a corresponding position along the signal via to cause signal reflection, resulting in constructive signal interference, which increases the signal amplitude of a selected portion of at least one broadband signal to reduce the insertion loss deviation of at least one broadband signal.

[0011] In a first example of the third aspect, the amplitude of the constructive signal interference of the at least one broadband signal may be adjusted by modifying the respective positions of the respective additional pads based on the wavelength range of the at least one broadband signal.

[0012] According to a fourth aspect of the first implementation, each corresponding additional pad of at least one signal via may be separated from at least one stacked layer of the printed circuit board by a via anti-pad.

[0013] In a second implementation of such a printed circuit board, the plurality of signal pads may include a plurality of differential signal pad pairs, wherein each differential signal pad pair of the plurality of differential signal pad pairs includes a positive signal pad and a negative signal pad.

[0014] According to the first aspect of the second implementation method, the multiple signal vias may include multiple signal via pairs, each signal via pair including a positive signal via and a negative signal via, wherein each via in the positive signal via and the negative signal via may include a corresponding additional solder pad, and each additional solder pad of each via in the positive signal via and the negative signal via is separated from at least one stacked layer of the printed circuit board by a plurality of via anti-solder pads.

[0015] In a first instance of the first aspect, a positive signal pad of at least one of a plurality of differential signal pad pairs may be electrically coupled to a positive signal via of at least one of a plurality of signal via pairs, and a negative signal pad of at least one of a plurality of differential signal pad pairs may be electrically coupled to a negative signal via of at least one of a plurality of signal via pairs.

[0016] In a third implementation of such a printed circuit board, the signal pad layer may be a surface layer of the printed circuit board.

[0017] In a fourth implementation of such a printed circuit board, a respective one of the plurality of signal pads may be disposed on a respective inner layer parallel to a main plane of the printed circuit board.

[0018] According to an implementation of the subject matter of the present disclosure, a method for manufacturing a printed circuit board includes stacking multiple printed circuit board layers, each printed circuit board layer having a corresponding main plane parallel to the main plane of the printed circuit board; forming multiple signal pads arranged on a signal pad layer of the printed circuit board, the signal pad layer being parallel to the main plane of the printed circuit board; electrically coupling multiple signal vias to each signal pad of the multiple signal pads, each signal via in the multiple signal vias having a longitudinal axis perpendicular to the main plane of the printed circuit board, each signal via extending through the multiple printed circuit board layers along the longitudinal axis, each corresponding signal via being electrically coupled to a corresponding signal pad of the multiple signal pads; and providing an added capacitive structure in at least one signal via in the multiple signal vias, the added capacitive structure together with the inductance of the at least one signal via forming a correction filter to reduce the insertion loss deviation of at least one broadband signal in the at least one signal via.

[0019] In a first implementation of the method, forming the added capacitive structure may include forming at least one additional pad, each additional pad extending from a corresponding signal via parallel to a main plane of the printed circuit board without being conductively coupled to any other portion of the printed circuit board.

[0020] The first aspect of the first implementation may further include forming each respective additional pad in a respective conductive layer of a plurality of printed circuit board layers of the printed circuit board.

[0021] A second aspect of the first implementation may further include determining a capacitance of each corresponding additional pad based on at least one of: (a) a pad size of the corresponding additional pad, (b) a pad shape of the corresponding additional pad, and (c) a pad position of the corresponding additional pad.

[0022] A second aspect of the first implementation may also include positioning each corresponding additional pad at a corresponding position along the signal via to cause signal reflection, resulting in constructive signal interference, which increases the signal amplitude of a selected portion of at least one broadband signal to reduce the insertion loss deviation of at least one broadband signal.

[0023] The first example of the second aspect may also include adjusting constructive signal interference of the at least one broadband signal by modifying respective positions of respective additional pads based on a wavelength range of the at least one broadband signal.

[0024] In a first variation of the first example, modifying the corresponding position of the corresponding additional pad to adjust the constructive signal interference caused by signal reflection may include: determining whether an insertion loss deviation target has been achieved by including the corresponding additional pad in the corresponding printed circuit board layer, and when the insertion loss deviation target has not been achieved, moving the corresponding additional pad to the corresponding adjacent printed circuit board layer of the signal via; and repeating the determination and movement until the insertion loss deviation target has been achieved.

[0025] In a second implementation of the method, forming the plurality of signal pads may include forming a plurality of differential signal pad pairs, wherein each differential signal pad pair of the plurality of differential signal pad pairs includes a positive signal pad and a negative signal pad.

[0026] According to the first aspect of the second implementation method, electrically coupling multiple signal vias may include electrically coupling multiple signal via pairs, each signal via pair including a positive signal via and a negative signal via, wherein each via in the positive signal via and the negative signal via includes a corresponding capacitive structure to form a corresponding correction filter, the corresponding capacitive structure includes at least one additional pad, and each of the additional pads of the capacitive structure of each via in the positive signal via and the negative signal via is separated from at least one printed circuit board layer of the printed circuit board by a plurality of via anti-pads.

[0027] A first instance of the first aspect may also include electrically coupling a positive signal pad of at least one differential signal pad pair among a plurality of differential signal pad pairs to a positive signal via of at least one signal via pair among a plurality of signal via pairs; and electrically coupling a negative signal pad of at least one differential signal pad pair among a plurality of differential signal pad pairs to a negative signal via of at least one signal via pair among a plurality of signal via pairs.

[0028] In a third implementation of the method, forming a plurality of signal pads on a signal pad layer of the printed circuit board may include forming a plurality of signal pads on a surface layer of the printed circuit board, the surface layer being parallel to a main plane of the printed circuit board.

[0029] In a fourth implementation of the method, forming a plurality of signal pads on a signal pad layer of the printed circuit board may include forming at least one signal pad of the plurality of signal pads on an inner layer parallel to a main plane of the printed circuit board.

[0030] According to an implementation of the subject matter of the present disclosure, a method for reducing insertion loss deviation of at least one broadband signal in a printed circuit board, the printed circuit board comprising a plurality of layers, each layer having a corresponding main plane parallel to the main plane of the printed circuit board, a plurality of signal pads, each signal pad being on a signal pad layer of the printed circuit board, the signal pad layer being parallel to the main plane; and a plurality of signal vias, the plurality of signal vias being electrically coupled to each of the plurality of signal pads, wherein each corresponding signal via has a longitudinal axis perpendicular to the main plane, wherein each signal via extends through the plurality of layers along the longitudinal axis, comprising: forming at least one signal via in the plurality of signal vias having a capacitive structure, the capacitive structure comprising at least one additional pad, the additional pad not being electrically coupled to other metal elements of the printed circuit board, each additional pad extending from the corresponding signal via parallel to the main plane; and positioning at least one additional pad along the longitudinal axis of the corresponding signal via based on the wavelength range of at least one broadband signal for which insertion loss deviation is to be reduced.

[0031] In a first implementation of such a method, positioning at least one additional pad along a longitudinal axis of a corresponding signal via based on a wavelength range may include positioning each corresponding additional pad at a corresponding position along the signal via to cause signal reflection, resulting in constructive signal interference, which increases the signal amplitude of a selected portion of at least one broadband signal to reduce an insertion loss deviation of the at least one broadband signal.

[0032] The first aspect of the first implementation may further include adjusting constructive signal interference of the at least one broadband signal by modifying respective positions of respective additional pads based on a wavelength range of the at least one broadband signal.

[0033] In a first instance of the first aspect, adjusting constructive signal interference of at least one broadband signal by modifying the corresponding position of a corresponding additional pad may include: determining whether an insertion loss deviation target has been achieved by including a corresponding additional pad in a corresponding printed circuit board layer, and when the insertion loss deviation target has not been achieved, moving the corresponding additional pad to a corresponding adjacent printed circuit board layer of the signal via, and repeating the determination and movement until the insertion loss deviation target has been achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Further features of the present disclosure, its nature and various advantages will become apparent from the following detailed description considered in conjunction with the accompanying drawings, in which like reference numerals refer to like parts throughout, and in which:

[0035] Figure 1 is a cross-sectional view of a printed circuit board incorporating an implementation of the presently disclosed subject matter;

[0036] Figure 2 is a perspective view of a signal via in a printed circuit board with portions of the printed circuit board removed for clarity, wherein the via includes a capacitive structure to form a correction filter according to an implementation of the presently disclosed subject matter;

[0037] Figure 3 is a flow chart of a method for forming a printed circuit board according to some implementations of the disclosed subject matter;

[0038] Figure 4 is a flow chart of a method for forming a via having a capacitive structure to form a correction filter according to some implementations of the disclosed subject matter; and

[0039] Figure 5 Flowchart of a method for tuning a correction filter formed by a capacitive structure in a via of a printed circuit board according to some implementations of the disclosed subject matter. DETAILED DESCRIPTION

[0040] As the length of the signal via approaches the order of magnitude of the wavelength of the signal sent through the signal via, the likelihood of insertion loss deviation of the signal in the signal via of the PCB increases. For a signal of a given wavelength, this phenomenon can occur as the via length increases, or for a constant via length, as the wavelength decreases (i.e., as the frequency increases), in both cases, for the signal passing through the signal via, poor signal integrity will result.

[0041] Additionally, for signals whose wavelength is comparable (i.e., of the same order of magnitude) to the length of the signal via (e.g., for a signal via greater than 1 mm in length, transmitting a broadband signal with a data rate equal to or greater than 200 Gbps), the likelihood of insertion loss deviation is greater than for lower data rate signals.

[0042] Printed circuit boards and methods of forming printed circuit boards can be implemented according to the subject matter of the present disclosure for broadband signals. In some implementations, signals of a certain wavelength range are transmitted through a signal via, where insertion loss deviation of the signal occurs.

[0043] Insertion loss, which can be defined as the energy loss during a signal's transmission through a transmission material in the direction of the signal path, as a function of frequency, can be caused by any of the following factors: (a) reflection insertion loss, (b) dielectric insertion loss, (c) conductive material insertion loss, (d) radiation insertion loss, and (e) surface roughness insertion loss. Insertion loss can be measured for a range of frequencies of the signal transmitted through the transmission material. For a corresponding signal frequency, insertion loss deviation can be defined as the difference between the expected insertion loss and the observed insertion loss. At high serial signal frequencies (e.g., 100 Gbps or higher), insertion loss deviation can create distortion (e.g., signal phase distortion), which causes unexpected results or errors in signal recovery after the signal passes through the signal via.

[0044] According to the implementation of the subject matter of the present disclosure, a correction filter can be formed in a signal via of a PCB, and at least one additional pad is added along the length of the signal via. Each additional pad can be formed in a metal layer of the PCB, but is not electrically connected to the rest of the metal layer or any other circuit element on the PCB. Each additional pad forms a capacitive relationship with another metal structure or multiple structures in the PCB, and the resulting capacitance interacts with the inductance (e.g., barrel inductance) inherent in the signal via, together with the delay associated with the distance between the capacitive structures embedded in the via, to create a correction filter. Assuming that broadband signals of various wavelengths (and therefore broadband signals of various frequencies) are sent through the signal via, the filter characteristics are adjusted by modifying the size and / or shape and / or position of the pad, and the filter is tuned to a specific frequency band within the signal, and the capacitance of the pad can be changed. The characteristics of the via, including the via length, the position of the pad along the via length, the presence of a stub and the anti-pad diameter, and additional mechanical aspects of the via, determine the insertion loss deviation as a function of frequency, and the cutoff fs of the frequency domain performance of the via.

[0045] In some implementations, each additional pad can cause a signal to reflect. In particular, if there are two or more additional pads, there can be repeated reflections of the signal between two adjacent additional pads within a specific frequency band. The signal transmission delay caused by these reflections can cause constructive interference in the signal, thereby increasing the signal amplitude and reducing the insertion loss deviation of the signal in the specific frequency band.

[0046] In addition, the signal via may include a signal via stub between an end of the signal via in the PCB and a signal via pad closest to the end. The signal via stub may be the remainder of the signal via formed by enlarging the signal via. The signal via stub may limit the signal via bandwidth and may also increase the insertion loss deviation of the signal sent through the signal via. The correction filter created by adding at least one capacitive structure may reduce the insertion loss deviation caused by the signal via stub.

[0047] The PCB has a main plane defined by the largest surface of the PCB, and each corresponding signal via has a longitudinal axis perpendicular to the main plane. As described above, an integrated correction filter can be formed in the signal via by creating a capacitive structure, such as by adding additional pads at various metal layers of the PCB through which the signal via passes, otherwise no signal pad is needed. Each additional pad added is not electrically coupled to the metal layer or any electronic component of the PCB that forms it. Each such pad can form a capacitive relationship with any other metal structure in the PCB, including but not limited to (a) a corresponding capacitive pad of a capacitive structure of an adjacent signal via, (b) a signal trace or conductive layer of an adjacent PCB layer, (c) a circuit board ground layer, and (d) an adjacent signal via. In some implementations, the capacitive relationship can include capacitance from an edge effect, which is formed by (a) a corresponding additional pad within a corresponding PCB layer and (b) a conductive element (e.g., trace, signal via, additional pad) on a corresponding adjacent dielectric PCB layer. The capacitance can be adjusted by changing the pad size and / or pad shape and / or pad position.

[0048] According to some implementations of the subject matter of the present disclosure, the corresponding positions along the corresponding signal vias of the additional pads of the corresponding capacitive structures that are added to form the correction filter are determined based on the length of the corresponding signal vias, the final signal transmission delay of the signal transmitted through the signal vias having the corresponding positions of the additional pads, and the wavelength range of the signal transmitted on the corresponding signal vias.

[0049] In some implementations, the position of each additional pad can be iteratively adjusted (eg, by iterative simulation, calculation, and / or measurement) to determine a position of the additional pad that minimizes insertion loss deviation of a signal passing through the signal via.

[0050] The number of additional pads of the capacitive structure of the correction filter set along the corresponding signal via can be determined based on the signal transmission delay corresponding to the length of the corresponding signal via and the wavelength of the signal (e.g., broadband signal) sent through the signal via. For example, the number of additional pads added to form the capacitive structure of the correction filter can be determined based on the ratio of the length of the corresponding signal via to the wavelength range of the broadband signal sent through the signal via. Then, the number of additional pads so determined can be set at a uniform distance along the corresponding signal via at least at the beginning, so as to delay the signal transmission between any two adjacent additional pads set along the corresponding signal via. As described above, the signal transmission delay can cause constructive signal interference, which is caused by the signal reflection between any two adjacent additional pads along the corresponding signal via. Constructive interference can reduce the insertion loss deviation of the signal sent along the corresponding signal via, and the constructive signal interference can be adjusted or tuned by changing one or more of the position, size and shape of the corresponding additional pads set along the corresponding signal via.

[0051] As described above, the capacitance formed by the corresponding additional pads added to form the capacitive structure of the correction filter can be adjusted by changing the size, shape or position of the corresponding additional pads. However, in some implementations, due to layout footprint limitations, such as the presence of other components in the PCB layer surrounding the corresponding additional pads, or due to manufacturing limitations of positioning two components close together on the same PCB layer, the size of the corresponding additional pads may not be increased. In such implementations, the pad shape can be changed to change the capacitance of the additional pads without exceeding the layout footprint constraints of the additional pads or the manufacturing limitations of the PCB layer.

[0052] For example, a correction filter can be formed in a signal via by adding a capacitive structure, the capacitive structure comprising at least one additional pad in the shape of a circular pad, having a corresponding pad size including a corresponding pad diameter, and having a layout footprint constraint. The layout footprint constraint of each additional pad can be imposed by one or more other components arranged in a corresponding conductive layer of the PCB, and the corresponding additional pad is arranged in the corresponding conductive layer of the PCB. If the capacitance of the corresponding capacitive element needs to be increased, but due to the presence of another component or any other manufacturing restrictions, the pad size of the corresponding additional pad may not be uniformly enlarged in all radial directions starting from the longitudinal axis of the signal via, the pad shape can be modified by extending or enlarging the corresponding additional pad in the corresponding conductive layer of the corresponding additional pad in a direction away from another component. This enables the pad size of the corresponding additional pad to be increased while remaining within the layout footprint constraints and manufacturing restrictions of the PCB layer.

[0053] The capacitive interaction between the capacitive elements formed by the additional pads and the barrel inductance of the corresponding signal vias can act as a correction filter to reduce the insertion loss deviation of the signal within a certain frequency range. For example, in PCB design, the correction filter can be tuned by changing the corresponding position, size and shape of the capacitive elements.

[0054] In some implementations, the signal vias are arranged as different signal via pairs, each signal via pair including a positive signal via and a negative signal via. Typically, in such cases, the positive signal via and the negative signal via are parallel to each other. Insertion loss deviations can be observed in the differential signal insertion loss behavior of a structure including both the positive signal via and the negative signal via and any additional reference vias near the signal vias. The delay associated with the length of the two signal vias is the main factor in the insertion loss behavior. In some different implementations, for each different signal via pair, a corresponding capacitive structure can be added to each of the positive signal via and the negative signal via to form a corresponding correction filter.

[0055] According to further implementations of the subject matter of the present disclosure, ground vias may be arranged in a printed circuit board and coupled to one or more printed circuit board ground layers to match the impedance of an integrated correction filter formed by adding a capacitive structure to the signal via and to minimize noise generated on the signal via due to interference (e.g., crosstalk interference) from other signal vias or any adjacent components (e.g., signal traces or pads in adjacent signal vias) disposed within the printed circuit board layer.

[0056] In some implementations, there may be anti-pads or non-conductive pockets in the stacked PCB layers to electrically isolate each respective signal via and its corresponding capacitive structure, which is added to form the correction filter, from each of the stacked layers of the PCB through which the signal via passes.

[0057] In an implementation where the length of each signal via is within an order of magnitude of the signal wavelength (e.g., a via length of approximately 1 mm for a signal with a data rate of 200 Gbps), the signal vias may not require any added capacitive structures to form a correction filter. Instead, the impedance of each signal via (e.g., differential impedance, common mode impedance, or single-ended impedance) can be optimized by arranging the signal vias closer to or farther away from the ground via, changing the pitch between each corresponding signal via and each other corresponding adjacent signal via. As the pitch between two signal vias increases, the corresponding impedance also increases. In some implementations, the size of the anti-pads in all layers of the PCB can be adjusted based on any changes in the pitch between two signal vias.

[0058] In an implementation where the length of each signal via is greater than the order of magnitude of the signal wavelength (e.g., when the signal data rate is 200 Gbps, the via length is greater than 1 mm), the number of additional pads that are disposed along the longitudinal axis of the signal via to form a correction filter can be determined based on the length of the signal via. The positions of the additional pads can initially be evenly distributed along the signal via. The final position of each additional pad can be determined in an iterative manner to determine the optimal position to achieve the insertion loss deviation target. In each iteration, if the insertion loss deviation target has not been achieved, a layer of the PCB changes the position of one of the additional pads to determine whether the change approaches or achieves the insertion loss deviation target of the correction filter formed by adding a capacitive structure.

[0059] refer to Figure 1-Figure 5 , you can better understand the subject matter of the present disclosure.

[0060] Figure 1 1 is a cross-sectional view of a printed circuit board 100 according to an implementation of the subject matter of the present disclosure. The printed circuit board (PCB) 100 includes a signal pad 102 and a ground pad 104. The signal pad 102 and the ground pad 104 are configured to be electrically coupled to a pin of an integrated circuit device or a pin of an additional circuit board. According to an implementation of the subject matter of the present disclosure, the printed circuit board 100 also includes a signal via 106, a ground via 108, an anti-pad 110, one or more board ground layers 112, one or more board power layers (not shown), a signal via pad 113, and a signal trace 114, all of which are positioned in various layers of the PCB 100.

[0061] In some implementations, the signal pads 102 are grouped into different signal pad pairs, each signal pad pair including a positive signal pad and a negative signal pad. In such implementations, the signal vias 106 are arranged as parallel differential via pairs, each pair including a positive signal via electrically coupled to the positive signal pad and a negative signal via electrically coupled to the negative signal pad. Within the printed circuit board layer through which the signal vias 106 pass, insertion loss deviations may occur in the positive signal vias and the negative signal vias depending on the length of each of the positive signal vias and the negative signal vias and the wavelength of the signal sent along the signal vias 106.

[0062] Each of the signal vias 106 can be electrically coupled to a corresponding signal trace 114 by means of a signal via pad 113. The signal trace 114 carries the signal sent from the signal pad 102 to the corresponding pin of the device. Additionally, the printed circuit board 100 can also include one or more board ground planes 112. In some implementations, the ground via 108 can be electrically coupled to a ground of the circuit board (e.g., one or more ground planes 112). In some implementations, the PCB 100 can include a power via (not shown) that is electrically coupled to one or more board power planes (not shown).

[0063] In addition, in some implementations, anti-pads 110, which are non-conductive pockets in one or more layers of the printed circuit board 100, can be disposed around one or more signal vias 106 and corresponding capacitive structures 116, which are added to form corresponding additional pads 118 of the correction filter. The anti-pads 110 isolate the additional pads 118 from the corresponding layers of the PCB forming each corresponding additional pad. In some implementations, the signal pads 102 can be electrically coupled to the signal vias 106, and the ground pads 104 can be electrically coupled to the ground vias 108. In some implementations, each signal via 106 defines a corresponding longitudinal axis perpendicular to the main plane of the PCB 100, and each signal via 106 extends through the layers of the PCB 100 along the corresponding longitudinal axis.

[0064] Each corresponding signal via 106 may have a capacitive structure 116, which includes at least one additional pad 118 to form a correction filter to reduce the insertion loss deviation of the signal sent through the corresponding signal via 106. The capacitive structure 116 added for the correction filter is realized by forming an additional pad 118 positioned along the longitudinal axis of the signal via 106, and the capacitive structure 116 may extend perpendicular to the main plane formed by the largest surface layer of the PCB 100. Each of the additional pads 118 may be formed by one of the metal layers of the PCB 100. In some implementations, the additional pads are not electrically connected to any other components or conductive elements within the structure of the PCB 100. In some implementations, the additional pads 118 may also be used to enhance the structural integrity of the PCB 100, while in other implementations, the additional structural integrity provided by the additional pads 118 is not required.

[0065] Each of the additional pads 118 can form a capacitive relationship with any other metal structure in the PCB 100, including any corresponding additional pads 118 of the same capacitive structure 116, or any conductive layer, structure, or trace in the PCB (e.g., signal trace 114, signal via pad 113, signal via 106, and corresponding additional pads of adjacent signal vias).

[0066] The capacitive interaction of each capacitive element formed by the additional pads 118 positioned along the signal via 106, together with the barrel inductance of the signal via 106, forms a correction filter to reduce insertion loss deviations of a transmit signal of a particular frequency or range of frequencies transmitted through the signal via 106. In some implementations, the capacitance of the respective capacitive element formed by each additional pad 118 of the capacitive structures 116 that are added to form the correction filter can be tuned by modifying the size or shape of the additional pads 118 and the spacing of the additional pads 118 relative to other metal elements.

[0067] In some implementations, it may be necessary to increase the pad size of the corresponding additional pad 118 to increase the capacitance of the corresponding formed capacitive element. As described above, in some implementations, the pad size of the corresponding additional pad 118 having a specific pad shape (e.g., a circular pad) may not be increased due to layout footprint constraints or manufacturing mechanical limitations. In such implementations, the shape of the pad may be changed, such as by changing the shape of the pad to a square, rectangle, other multi-sided polygon, ellipse, teardrop, or any other suitable geometric shape, so as to adjust and further increase the area of ​​the additional pad 118 without exceeding the layout footprint constraints of the additional pad 118.

[0068] The position of the additional pads 118 disposed along the corresponding signal vias 106 may be determined based on the wavelength range of at least one signal transmitted through the corresponding signal vias 106. In some implementations, the position of the additional pads 118 may be selected so that a signal reflection between any two adjacent additional pads 118 disposed along the signal vias 106 results in a transmission delay that causes constructive signal interference. When optimized, the constructive signal interference may cause an increased signal amplitude to help reduce the insertion loss deviation of the signal transmitted along the signal vias 106.

[0069] Despite Figure 1As shown, the signal pads 102 from which the signal vias 106 extend are disposed on a surface layer of the PCB 100, but in some implementations, one or more of the signal vias 106 may be "buried vias" extending completely inside the PCB 100. In the case of any completely internal signal vias 106, the corresponding signal pads 102 may be disposed on an inner layer of the PCB 100, and if there is more than one buried signal via 106, the corresponding signal pads 102 may not be disposed on the same inner layer of the PCB 100. That is, in some implementations, the signal pads 102 may be disposed on different inner layers among the multiple layers.

[0070] Figure 2 1 is a perspective view of signal vias (e.g., signal vias 106) in a printed circuit board, wherein the signal vias include capacitive structures (e.g., capacitive structures 116) according to implementations of the disclosed subject matter for forming a corresponding correction filter in each signal via 106. Each of the capacitive structures 116 added to form the correction filter includes at least one additional pad 202, each additional pad 202 having a pad size, a pad shape, and a pad position along the signal via 106. Each additional pad 202 disposed along the corresponding signal via 106 can form a capacitive relationship with any other metal structure in the PCB 100, including but not limited to (a) a corresponding capacitive pad in the same or adjacent signal via, (b) a signal trace 114 or a conductive layer of an adjacent PCB layer, (c) a board ground layer, and (d) an adjacent signal via. By modifying at least one of (a) the pad size of the corresponding additional pad 202, (b) the pad shape of the corresponding additional pad 202, and (c) the position of the corresponding additional pad 202, the capacitance of each corresponding capacitive element partially formed by each corresponding additional pad 202 can be changed.

[0071] like Figure 2 As shown, by modifying the pad shape of the additional pad 202, the additional pad 202 can be extended to include an additional geometric feature to increase the area of ​​the additional pad 202, thereby increasing the capacitance. The added area of ​​the corresponding additional pad 202 increases the capacitance of the corresponding capacitive element formed between the corresponding additional pad 202 and any conductive layer, structure or trace in the PCB near the corresponding capacitive element (e.g., signal trace 114, signal via pad 113, signal via 106, the corresponding additional pad of the adjacent capacitive structure 116, and the dielectric layer of the PCB). Modifying the pad shape of the corresponding additional pad 202 can help avoid other components surrounding the corresponding additional pad 202 in the stacked layer in which the additional pad 202 is provided.

[0072] According to an implementation of the subject matter of the present disclosure, a method 300 for manufacturing a printed circuit board is as follows: Figure 3 As shown. The method 300 begins at 302, where a plurality of printed circuit board layers are stacked, each printed circuit board layer having a corresponding main plane parallel to the main plane of the printed circuit board. In some implementations, the conductive electronic components are formed on the layers that are subsequently stacked in a suitable alignment, while in other implementations, the conductive electronic components are formed on the individual layers in a suitable alignment during the stacking construction of the printed circuit board. At 304, a plurality of signal pads are formed, the plurality of signal pads being disposed on the printed circuit board layer, the printed circuit board layer being parallel to the main plane of the printed circuit board. At 306, a plurality of signal vias are electrically coupled to each of the plurality of signal pads, each corresponding signal via in the plurality of signal vias having a longitudinal axis perpendicular to the main plane of the printed circuit board, each signal via extending through the plurality of layers along the longitudinal axis, each corresponding signal via being electrically coupled to a corresponding signal pad of the plurality of signal pads, wherein at least one of the plurality of signal vias includes an added capacitive structure, the added capacitive structure together with the inductance of the at least one signal via forms a correction filter to reduce the insertion loss deviation of at least one signal in the at least one signal via.

[0073] A method 400 for manufacturing a printed circuit board according to an implementation of the disclosed subject matter is as follows: Figure 4 The method 400 begins at 402, where a capacitive structure is formed in at least one of a plurality of signal vias to form a correction filter, the capacitive structure comprising a plurality of additional pads, each of which extends from a corresponding signal via parallel to the main plane. At 404, the plurality of additional pads are positioned along a longitudinal axis of the corresponding signal via based on a wavelength range of at least one signal for which insertion loss deviation is to be reduced.

[0074] One implementation of a method 500 for tuning a broadband signal filter in a printed circuit board by positioning additional pads based on signal wavelength according to an implementation of the disclosed subject matter is as follows: Figure 5 As shown. The method 500, which is repeated for each signal via (or for each differential signal via pair in a differential signal implementation), begins at 502, where it is determined whether the length of a current via of a plurality of signal vias is greater than 1 mm. If so, then at 504, based on the length of the signal via, the number of additional pads required to form a correction filter in the signal via is determined. At 506, a location along the signal via is determined at which each additional pad of the capacitive structure is to be disposed; initially, the additional pads are evenly spaced along the signal via.

[0075] At 508, an optimized pad size is determined for each additional pad of a capacitive structure that forms part of a correction filter in the signal via. At 510, it is determined whether the insertion loss deviation target has been achieved. If so, the method 500 ends. If the insertion loss deviation target has not been achieved at 510, the process continues at 512, where the position of one of the additional pads is changed by one layer of the PCB. At 512, changing the position of the additional pads by one layer is iterative because the process returns to 510 to determine whether the insertion loss deviation target has been achieved.

[0076] If it is determined at 502 that the length of the current via of the plurality of signal vias is not greater than 1 mm, then at 514, unused additional pads are removed, and at 516, the impedance of each signal via is matched to the impedance of each other signal via by arranging the signal vias near the ground vias, changing the pitch between the signal vias, and changing the size of the anti-pad corresponding to each signal via. At 518, it is determined whether the insertion loss deviation target has been achieved for signal vias less than or equal to 1 mm in length. If at 518, the insertion loss deviation target has been achieved, the method 500 ends. If it is determined at 518 that the insertion loss deviation target has not been achieved, the process proceeds to 504.

[0077] It can be seen that a PCB is provided having vias with built-in correction filters to reduce distortion caused by insertion loss deviations.

[0078] As used herein and in the following claims, the construction "one of A and B" shall mean "A or B."

[0079] It should be noted that the foregoing is merely illustrative of the principles of the present invention and that the present invention may be practiced by embodiments other than those described, which are intended to be illustrative rather than limiting, and that the present invention is limited only by the claims that follow.

Claims

1. A printed circuit board, comprising: a plurality of stacked layers, each layer having a respective major plane defining a major plane of the printed circuit board; A plurality of signal pads are arranged on a signal pad layer of the printed circuit board, wherein the signal pad layer is parallel to the main plane of the printed circuit board; as well as A plurality of signal vias, each of the plurality of signal vias having a longitudinal axis perpendicular to the main plane of the printed circuit board, each signal via extending through the plurality of stacked layers along the longitudinal axis, each corresponding signal via being electrically coupled to a corresponding signal pad of the plurality of signal pads, wherein at least one of the plurality of signal vias includes an added capacitive structure, the added capacitive structure together with the inductance of the at least one signal via forms a correction filter to reduce an insertion loss deviation of at least one broadband signal in the at least one signal via.

2. The printed circuit board of claim 1 , wherein for each corresponding signal via of the at least one signal via, the added capacitive structure comprises at least one additional pad, each additional pad extending from the corresponding signal via parallel to the main plane of the printed circuit board without being conductively coupled to any other portion of the printed circuit board. 3 . The printed circuit board of claim 2 , wherein each respective additional pad is formed in a respective conductive layer of the plurality of stacked layers of the printed circuit board.

4. A printed circuit board according to claim 2, wherein the capacitance of each corresponding additional pad is at least partially determined by at least one of the following: (a) a pad size of the corresponding additional pad and (b) a pad shape of the corresponding additional pad.

5. The printed circuit board of claim 2, wherein each corresponding additional pad is disposed at a corresponding position along the signal via to cause signal reflection, resulting in constructive signal interference, the constructive signal interference increasing the signal amplitude of a selected portion of the at least one broadband signal to reduce the insertion loss deviation of the at least one broadband signal.

6. The printed circuit board of claim 5, wherein the amplitude of the constructive signal interference of the at least one broadband signal can be adjusted by modifying the respective positions of the respective additional pads based on the wavelength range of the at least one broadband signal.

7. The printed circuit board of claim 2, wherein each respective additional pad of at least one signal via is separated from at least one stacked layer of the printed circuit board by a via anti-pad.

8. The printed circuit board of claim 1 , wherein the plurality of signal pads comprises a plurality of differential signal pad pairs, wherein each of the plurality of differential signal pad pairs comprises: Positive signal pad; as well as Negative signal pad.

9. The printed circuit board of claim 8, wherein the plurality of signal vias comprises a plurality of signal via pairs, each signal via pair comprising a positive signal via and a negative signal via, wherein each of the positive signal vias and the negative signal vias comprises a corresponding additional pad, and each of the additional pads of each of the positive signal vias and the negative signal vias is separated from at least one stacked layer of the printed circuit board by a plurality of via anti-pads.

10. The printed circuit board according to claim 9, wherein: The positive signal pad of at least one of the plurality of differential signal pad pairs is electrically coupled to the positive signal via of at least one of the plurality of signal via pairs; and The negative signal pad of at least one of the plurality of differential signal pad pairs is electrically coupled to the negative signal via of at least one of the plurality of signal via pairs.

11. The printed circuit board according to claim 1, wherein the signal pad layer is a surface layer of the printed circuit board.

12. The printed circuit board of claim 1, wherein corresponding signal pads of the plurality of signal pads are disposed on corresponding inner layers parallel to the main plane of the printed circuit board.

13. A method for manufacturing a printed circuit board, the method comprising: stacking a plurality of printed circuit board layers, each printed circuit board layer having a respective main plane parallel to a main plane of the printed circuit board; forming a plurality of signal pads disposed on a signal pad layer of the printed circuit board, the signal pad layer being parallel to the main plane of the printed circuit board; electrically coupling a plurality of signal vias to each of the plurality of signal pads, each respective signal via of the plurality of signal vias having a longitudinal axis perpendicular to the principal plane of the printed circuit board, each signal via extending through the plurality of printed circuit board layers along the longitudinal axis, each respective signal via being electrically coupled to a respective signal pad of the plurality of signal pads; as well as An added capacitive structure is provided in at least one signal via of the plurality of signal vias, the added capacitive structure together with the inductance of the at least one signal via forming a correction filter to reduce insertion loss deviation of at least one broadband signal in the at least one signal via.

14. The method for manufacturing a printed circuit board according to claim 13, wherein forming the added capacitive structure includes forming at least one additional pad, each additional pad extending from the corresponding signal via parallel to the main plane of the printed circuit board without being conductively coupled to any other part of the printed circuit board.

15. The method for manufacturing a printed circuit board according to claim 14, further comprising forming each respective additional pad in a respective conductive layer of the plurality of printed circuit board layers of the printed circuit board.

16. The method for manufacturing a printed circuit board according to claim 14 further includes determining the capacitance of each corresponding additional pad based on at least one of the following: (a) a pad size of the corresponding additional pad, (b) a pad shape of the corresponding additional pad, and (c) a pad position of the corresponding additional pad.

17. The method for manufacturing a printed circuit board according to claim 14 further includes positioning each corresponding additional pad at a corresponding position along the signal via so that signal reflection causes constructive signal interference, and the constructive signal interference increases the signal amplitude of a selected portion of the at least one broadband signal to reduce the insertion loss deviation of the at least one broadband signal.

18. The method for manufacturing a printed circuit board according to claim 17, further comprising adjusting the constructive signal interference of the at least one broadband signal by modifying respective positions of respective additional pads based on a wavelength range of the at least one broadband signal.

19. The method for manufacturing a printed circuit board according to claim 18, wherein modifying the respective positions of the respective additional pads to adjust the constructive signal interference caused by the signal reflection comprises: determining whether an insertion loss deviation target has been achieved by including the corresponding additional pad in a corresponding printed circuit board layer, and moving the corresponding additional pad to a corresponding adjacent printed circuit board layer of the signal via when the insertion loss deviation target has not been achieved; as well as The determining and the moving are repeated until the insertion loss deviation target has been achieved.

20. The method for manufacturing a printed circuit board according to claim 13, wherein forming a plurality of signal pads comprises forming a plurality of differential signal pad pairs, wherein each differential signal pad pair of the plurality of differential signal pad pairs comprises: Positive signal pad; as well as Negative signal pad.

21. A method for manufacturing a printed circuit board according to claim 20, wherein electrically coupling a plurality of signal vias includes electrically coupling a plurality of signal via pairs, each signal via pair including a positive signal via and a negative signal via, wherein each of the positive signal vias and the negative signal vias includes a corresponding capacitive structure to form a corresponding correction filter, the corresponding capacitive structure includes at least one additional pad, each of the additional pads of the capacitive structure of each of the positive signal vias and the negative signal vias is separated from at least one printed circuit board layer of the printed circuit board by a plurality of via anti-pads.

22. The method for manufacturing a printed circuit board according to claim 21, further comprising: electrically coupling the positive signal pad of at least one differential signal pad pair of the plurality of differential signal pad pairs to the positive signal via of at least one signal via pair of the plurality of signal via pairs; as well as The negative signal pad of at least one of the plurality of differential signal pad pairs is electrically coupled to the negative signal via of at least one of the plurality of signal via pairs.

23. The method for manufacturing a printed circuit board according to claim 13, wherein forming a plurality of signal pads disposed on a signal pad layer of the printed circuit board comprises forming a plurality of signal pads disposed on a surface layer of the printed circuit board, the surface layer being parallel to the main plane of the printed circuit board.

24. The method for manufacturing a printed circuit board according to claim 13, wherein forming a plurality of signal pads on a signal pad layer of the printed circuit board comprises forming at least one of the plurality of signal pads on an inner layer parallel to the main plane of the printed circuit board.

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