Semiconductor device and preparation method thereof, and storage system

Abstract

The embodiment of the invention provides a semiconductor device and a preparation method thereof, and a storage system, and the semiconductor device comprises a first semiconductor structure which comprises a first well region; and the second semiconductor structure is bonded with the first semiconductor structure, the second semiconductor structure comprises a second well region, and the second well region of the second semiconductor structure is provided with a fin field effect transistor. Through the mode, the performance of the transistor can be improved on the basis of reducing the chip area.

Description

Semiconductor device, manufacturing method thereof, and storage system Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device, a preparation method thereof, and a storage system. Background Art

[0002] As the feature size of memory chips approaches the process limit, planar processes and manufacturing technologies become challenging and costly, causing the storage density of 2D or planar NAND flash memory to approach its upper limit. To overcome the limitations of 2D or planar NAND flash memory, the industry has developed memory chips with three-dimensional structures (3D NAND), which increase storage density by arranging memory cells three-dimensionally on a substrate.

[0003] In current three-dimensional memories, the integration density of transistors is still low, which means that the memory chip still has the problem of large area, and the existing preparation process is relatively complicated and costly.

[0004] Summary of the Invention

[0005] The embodiments of the present application provide a semiconductor device, a method for manufacturing the same, and a storage system, which can improve the performance of transistors while reducing the chip area.

[0006] The present application provides a semiconductor device, which includes: a first semiconductor structure, the first semiconductor structure including a first well region; a second semiconductor structure, the second semiconductor structure is bonded to the first semiconductor structure, the second semiconductor structure including a second well region, wherein the second well region of the second semiconductor structure is provided with a fin field-effect transistor.

[0007] In an optional embodiment, the first semiconductor structure includes a first insulating layer; the second semiconductor structure includes: a second insulating layer, one side of the second insulating layer is bonded to the first insulating layer; an active layer, the active layer is arranged on the side of the second insulating layer away from the first semiconductor structure, and the active layer of the second well region includes at least one fin; a gate oxide layer, the gate oxide layer is arranged on the fin; and a gate layer, the gate layer is arranged on the gate oxide layer.

[0008] In an optional embodiment, the thickness of the fin along the Z direction is 30 nm-65 nm, wherein the Z direction is a direction perpendicular to the extension plane of the second insulating layer.

[0009] In an optional embodiment, the fin includes a top surface and side surfaces, the top surface is parallel to an extension plane of the second insulating layer, the side surfaces are connected to the top surface, and the gate oxide layer covers the top surface and the side surfaces.

[0010] In an optional embodiment, the second insulating layer includes at least one step portion protruding from a side facing away from the first semiconductor structure, and the at least one fin is correspondingly disposed on the at least one step portion.

[0011] In an optional embodiment, the width of the contact surface between the step portion and the fin along the X direction is equal to the width of the contact surface between the fin and the step portion along the X direction, and the X direction is the arrangement direction of at least one fin.

[0012] In an optional embodiment, the width of the contact surface between the step portion and the fin along the X direction is smaller than the width of the contact surface between the fin and the step portion along the X direction. The fin further includes a top surface, a side surface, and a bottom surface. The bottom surface is a non-contact surface of the fin that overhangs the contact surface of the step portion. The gate oxide layer covers the top surface, the side surface, and the bottom surface. The X direction is the arrangement direction of at least one fin.

[0013] In an optional embodiment, the second well region includes a first sub-well region and a second sub-well region, and the thickness of the gate oxide layer of the first sub-well region is greater than the thickness of the gate oxide layer of the second sub-well region.

[0014] In an optional embodiment, the second semiconductor structure further includes a first isolation structure, and the first isolation structure is used to isolate the gate layers corresponding to two adjacent fins.

[0015] In an optional embodiment, the second semiconductor structure further includes a second isolation structure, and the second isolation structure is used to isolate gate layers corresponding to different well regions.

[0016] In an optional embodiment, a planar transistor is disposed on the first semiconductor structure in the first well region.

[0017] In an optional embodiment, the thickness of the gate oxide layer of the planar transistor is greater than the thickness of the gate oxide layer of the fin field effect transistor.

[0018] In an optional embodiment, the semiconductor device further includes a memory array structure, and the memory array structure is bonded to the second semiconductor structure.

[0019] The present application also provides a method for preparing a semiconductor device, which includes: providing a first semiconductor structure and a second semiconductor structure, the first semiconductor structure including a first well region, and the second semiconductor structure including a second well region; bonding the first semiconductor structure and the second semiconductor structure; and forming a fin field-effect transistor in the second well region of the second semiconductor structure.

[0020] In an optional embodiment, the first semiconductor structure includes a first insulating layer, and the second semiconductor structure includes an active layer; bonding the first semiconductor structure and the second semiconductor structure includes: forming a second insulating layer on the active layer; bonding the second insulating layer and the first insulating layer to bond the first semiconductor structure and the second semiconductor structure.

[0021] In an optional embodiment, a fin field effect transistor is formed in the second well region of the second semiconductor structure, including: forming at least one groove on the active layer, with the second insulating layer exposed at the bottom of the groove, and the groove isolating the active layer into at least one fin; forming a gate oxide layer on the at least one fin; and forming a gate layer on the gate oxide layer.

[0022] In an optional embodiment, before forming at least one groove on the active layer, the method further includes: performing a thinning process on the active layer.

[0023] In an optional embodiment, before forming a gate oxide layer on at least one fin, the method further includes: forming a liner on at least one fin; and removing the liner.

[0024] In an optional embodiment, the fin includes a top surface and a side surface, the top surface is parallel to the extension plane of the second insulating layer, and the side surface is connected to the top surface; forming a gate oxide layer on at least one fin includes: forming a gate oxide layer on the top surface and side surface of at least one fin.

[0025] In an optional embodiment, at least one groove is formed on the active layer, including: forming at least one groove on the active layer, the groove isolating the active layer into at least one fin, exposing the second insulating layer at the bottom of the groove and causing the second insulating layer to form at least one step portion protruding from one side away from the first semiconductor structure and corresponding to the at least one fin.

[0026] In an optional embodiment, a width of a contact surface between the step portion and the fin along the X direction is smaller than a width of a contact surface between the fin and the step portion along the X direction, the fin further includes a top surface, a side surface, and a bottom surface, the bottom surface is a non-contact surface of the fin overhanging the contact surface of the step portion, and the X direction is an arrangement direction of the at least one fin; forming a gate oxide layer on the at least one fin includes: forming a gate oxide layer on the top surface, the side surface, and the bottom surface of the at least one fin.

[0027] In an optional embodiment, forming a gate layer on the gate oxide layer includes: forming a gate layer on the gate oxide layer and the exposed second insulating layer; thinning the gate layer to expose the top surface of the gate oxide layer, and the top surface of the gate oxide layer is parallel to the extension plane of the second insulating layer.

[0028] In an optional embodiment, after forming the gate layer on the gate oxide layer, the method further includes: forming a first isolation structure on the second insulating layer to isolate the gate layers corresponding to two adjacent fins.

[0029] In an optional embodiment, after forming the gate layer on the gate oxide layer, the method further includes: forming a second isolation structure on the gate oxide layer to isolate the gate layers corresponding to different well regions.

[0030] In an optional embodiment, the method further includes: providing a memory array structure; and bonding the memory array structure to the second semiconductor structure.

[0031] The present application also provides a storage system, which includes a semiconductor device and a controller. The controller is coupled to the semiconductor device to control the semiconductor device to store data. The semiconductor device is the semiconductor device as described above, or the semiconductor device is a semiconductor device prepared using the preparation method as described above.

[0032] The semiconductor device provided in this application includes: a first semiconductor structure, the first semiconductor structure including a first well region; and a second semiconductor structure, the second semiconductor structure bonded to the first semiconductor structure and including a second well region, wherein the second well region of the second semiconductor structure is provided with a fin field-effect transistor. By adopting the above-described method, the first well region and the second well region are respectively provided on two semiconductor structures (such as a wafer), and the second well region of the second semiconductor structure is provided with a fin field-effect transistor. The embodiments of this application can improve transistor performance by using fin field-effect transistors while reducing chip area. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0034] FIG1 is a schematic structural diagram of a semiconductor device according to a first embodiment of the present invention;

[0035] FIG2 is a schematic structural diagram of a second embodiment of a semiconductor device provided by the present application;

[0036] FIG3 is a schematic structural diagram of a first embodiment of a second semiconductor structure 20;

[0037] FIG4 is a partial schematic diagram of the fin portion in FIG3 ;

[0038] FIG5 is a schematic structural diagram of a second semiconductor structure 20 according to a second embodiment;

[0039] FIG6 is a schematic structural diagram of a third embodiment of the second semiconductor structure 20;

[0040] FIG7 is a partial schematic diagram of the fin portion in FIG6 ;

[0041] FIG8 is a schematic structural diagram of a fourth embodiment of the second semiconductor structure 20;

[0042] FIG9 is a schematic structural diagram of a fifth embodiment of the second semiconductor structure 20;

[0043] FIG10 is a schematic flow chart of an embodiment of a method for manufacturing a semiconductor device provided by the present application;

[0044] FIG11 is a schematic structural diagram of an embodiment of step 102 in FIG10 ;

[0045] FIG12 is a schematic flow chart of a first embodiment of step 103 in FIG10 ;

[0046] FIG13 is a schematic structural diagram of an embodiment of step 1031 in FIG12;

[0047] FIG14 is a schematic structural diagram of an embodiment of step 1032 in FIG12;

[0048] FIG15 is a schematic flow chart of a second embodiment of step 103 in FIG10 ;

[0049] FIG16 is a schematic structural diagram of an embodiment of step 103a in FIG15;

[0050] FIG17 is a schematic structural diagram of an embodiment of step 103b in FIG15;

[0051] FIG18 is a schematic structural diagram of an embodiment of a storage system provided in the present application. DETAILED DESCRIPTION

[0052] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0053] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the said features. In the description of the present application, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0054] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0055] The use of "suitable for" or "configured to" in this application is intended to be open and inclusive language, and does not exclude devices that are adapted or configured to perform additional tasks or steps. In addition, the use of "based on" is intended to be open and inclusive, as a process, step, calculation, or other action that is "based on" one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0056] In this application, the word "exemplary" is used to mean "serving as an example, illustration, or illustration." Any embodiment described in this application as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. The following description is given to enable any person skilled in the art to implement and use the present application. In the following description, details are listed for the purpose of explanation. It should be understood that one of ordinary skill in the art can recognize that the present application can be implemented without using these specific details. In other instances, well-known structures and processes are not elaborated in detail to avoid obscuring the description of the present application with unnecessary details. Therefore, the present application is not intended to be limited to the embodiments shown, but is consistent with the widest scope consistent with the principles and features disclosed in this application.

[0057] Referring to Figure 1, Figure 1 is a structural schematic diagram of the first embodiment of the semiconductor device provided in the present application. The semiconductor device 100 includes a first semiconductor structure 10 and a second semiconductor structure 20. The first semiconductor structure 10 and the second semiconductor structure 20 are bonded. The first semiconductor structure 10 includes a first well region, the second semiconductor structure 20 includes a second well region, and the second well region of the second semiconductor structure 20 is provided with a fin field-effect transistor.

[0058] Alternatively, the first semiconductor structure 10 and the second semiconductor structure 20 may be wafers. A wafer is a silicon wafer used to manufacture silicon semiconductor circuits. The starting material is silicon. High-purity polycrystalline silicon is dissolved, doped with silicon crystal seeds, and then slowly pulled out to form cylindrical single crystal silicon. Silicon ingots are ground, polished, and sliced ​​to form silicon wafers, also known as wafers.

[0059] In one embodiment, the first well region is a high voltage (High Voltage, HV) well region, and the second well region is a low voltage well region. Further, the low voltage well region may further include a first sub-well region and a second sub-well region. The first sub-well region is, for example, an LV (Low Voltage) well region, and the second sub-well region is, for example, an LLV (Low Low Voltage) well region. Optionally, in one embodiment, the first well region (high voltage well region HV) can be understood as a semiconductor device formed in this region having a turn-on voltage or threshold voltage greater than 5V, and the second well region (low voltage well region LV and ultra-low voltage well region LLV) can be understood as a semiconductor device formed in this region having a turn-on voltage or threshold voltage less than or equal to 5V; wherein, the ultra-low voltage well region LLV can be understood as a semiconductor device formed in this region having a turn-on voltage or threshold voltage less than or equal to 1.6V.

[0060] Furthermore, a planar transistor is disposed in the first well region of the first semiconductor structure 10 , and a fin field effect transistor is disposed in the second well region of the second semiconductor structure 20 .

[0061] Fin field-effect transistors (FinFETs) are a new type of complementary metal oxide semiconductor (CMOS) transistor. In traditional transistor structures, the gate that controls current flow can only turn the circuit on and off on one side of the gate, resulting in a planar architecture. In the Fin-FET architecture, the gate is a forked 3D structure, similar to a fish fin, that can turn the circuit on and off on both sides. This design significantly improves circuit control and reduces leakage, while also significantly shortening the transistor's gate length. The main difference between Fin-FETs and planar MOSFETs is that their channel consists of a tall, thin fin raised above an insulating substrate, with the source and drain electrodes at either end, and the gate attached to the sidewalls and top to assist in current control. This fin-shaped structure increases the area surrounding the gate, strengthening the gate's control over the channel. This effectively mitigates the short channel effect seen in planar devices, significantly improving circuit control and reducing leakage, while also significantly shortening the transistor's gate length. Precisely because of this characteristic, Fin-FETs do not require a highly doped channel, effectively reducing impurity ion scattering and improving channel carrier mobility.

[0062] Fin-FET devices offer significant advantages over traditional planar transistors. First, the Fin-FET channel is typically lightly doped or even undoped, which avoids the scattering effect of discrete dopant atoms. This significantly improves carrier mobility compared to heavily doped planar devices. Furthermore, compared to traditional planar CMOS, Fin-FET devices offer a significant advantage in suppressing subthreshold current and gate leakage. The Fin-FET's body-fin structure, such as its dual-gate or half-ring gate, increases the gate's control area over the channel, significantly enhancing gate control capability. This effectively suppresses the short-channel effect and reduces subthreshold leakage. This suppression of the short-channel effect and enhanced gate control capability allow Fin-FET devices to use thicker gate oxides than traditional devices, which in turn reduces gate leakage. Clearly, Fin-FETs are superior to PDSOI. Furthermore, because Fin-FETs operate on a similar process to CMOS technology, they are technically easier to implement and are widely used in the manufacture of small ICs.

[0063] Referring to Figure 2, Figure 2 is a structural schematic diagram of a second embodiment of a semiconductor device provided in the present application. The semiconductor device 100 includes a first semiconductor structure 10, a second semiconductor structure 20 and a storage array structure 30. The first semiconductor structure 10 and the second semiconductor structure 20 are bonded, and the storage array structure 30 is connected to the second semiconductor structure 20. The first semiconductor structure 10 includes a first well region, the second semiconductor structure 20 includes a second well region, and the second well region of the second semiconductor structure 20 is provided with a fin field-effect transistor.

[0064] Optionally, the memory array structure 30 and the second semiconductor structure 20 may be connected by bonding, or the memory array structure 30 may be formed on the second semiconductor structure 20 by deposition processing.

[0065] It is worth noting that in this embodiment, the first well region is a high-voltage well region and the second well region is a low-voltage well region. Therefore, the first semiconductor structure 10, the second semiconductor structure 20 and the memory array structure 30 are stacked and bonded in sequence, that is, the second semiconductor structure 20 containing the low-voltage well region (such as the LV well region and the LLV well region) is closer to the memory array structure 30, and the first semiconductor structure 10 containing the high-voltage well region (such as the HV well region) is farther away from the memory array structure 30.

[0066] Furthermore, a planar transistor is disposed in the first well region of the first semiconductor structure 10 , and a fin field effect transistor is disposed in the second well region of the second semiconductor structure 20 .

[0067] In this embodiment, the memory array structure 30 includes a plurality of memory cells for storing data. The first semiconductor structure 10 and the second semiconductor structure 20 serve as peripheral circuits (peripheral devices) of the memory array structure 30. The peripheral devices may include page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, and other peripheral circuits. At least one of the peripheral circuits includes a semiconductor structure and a transistor disposed on the semiconductor structure. Depending on the connection architecture between the peripheral circuit and the memory array structure 30, the peripheral circuit may be a periphery near cell (PNC) architecture, a periphery under cell (PUC) architecture, or an inverted architecture, which is not limited in this embodiment of the present application.

[0068] It can be understood that the semiconductor structure to be protected by the embodiments of the present application can be the semiconductor structure shown in Figure 2 (i.e., a three-dimensional memory) or the semiconductor structure shown in Figure 1 (i.e., a part of a three-dimensional memory), and this application does not limit it.

[0069] In conjunction with the embodiments of Figures 1 and 2 above, the semiconductor device provided by the present application includes: a first semiconductor structure, the first semiconductor structure including a first well region; and a second semiconductor structure, the second semiconductor structure being bonded to the first semiconductor structure and including a second well region, wherein the second well region of the second semiconductor structure is provided with a fin field-effect transistor. By adopting the above-described method, the first well region and the second well region are respectively provided on two semiconductor structures (such as a wafer), and the second well region of the second semiconductor structure is provided with a fin field-effect transistor. The embodiment of the present application can improve transistor performance by using fin field-effect transistors while reducing chip area.

[0070] The second semiconductor structure 20 is described in detail below. In the following embodiments, the X direction, Y direction, and Z direction are defined, where the X direction is the horizontal direction in the figure, the Z direction is the vertical direction in the figure, the X direction and the Z direction form an XZ plane, the Y direction is perpendicular to the XZ plane, the X direction and the Y direction form an XY plane, and the XY plane is the horizontal plane in the figure.

[0071] As shown in Figure 3, Figure 3 is a structural schematic diagram of the first embodiment of the second semiconductor structure 20. The first semiconductor structure 10 includes a first insulating layer 11, and the second semiconductor structure 20 includes a second insulating layer 21, an active layer 22, a gate oxide layer 23 and a gate layer 24. One side of the second insulating layer 21 is bonded to the first insulating layer 11.

[0072] The active layer 22 is disposed on the side of the second insulating layer 21 away from the first semiconductor structure 10 . The active layer 22 in the second well region includes at least one fin 22 a . The gate oxide layer 23 is disposed on the fin 22 a . The gate layer 24 is disposed on the gate oxide layer 23 .

[0073] Specifically, the extension plane of the second insulating layer 21 is parallel to the XY plane; the active layer 22 is arranged on the side of the second insulating layer 21 away from the first semiconductor structure 10, and the active layer 22 includes at least one fin 22a, the at least one fin 22a extends along the Y direction, and has a certain width in the X direction and a certain thickness in the Z direction. At least one fin 22a is arranged along the X direction. When the number of fins 22a is multiple, there is a certain interval between every two fins 22a; the gate oxide layer 23 is arranged on the fin 22a, specifically including the top surface (away from the side of the second insulating layer 21 and planar to the XY plane) and the side surface (based on the opposite sides of the YZ plane) of the fin 22a; the gate layer 24 is arranged on the gate oxide layer 23. When the number of fins 22a is multiple, the gate layer 24 is arranged on the gate oxide layer 23 between every two fins 22a.

[0074] Please refer to Figure 4 specifically, which is a partial schematic diagram of the fin in Figure 3. Along the thickness direction (Z direction) of the fin 22a, due to the etching process, the width of its upper end along the X direction is smaller than the width of the lower end along the X direction; further, the fin 22a includes a top surface 22a1 and side surfaces (a first side surface 22a2 and a second side surface 22a3), wherein the first side surface 22a2 and the second side surface 22a3 are two side surfaces symmetrical based on the YZ plane, the top surface 22a1 is parallel to the extension plane of the second insulating layer 21, the side surfaces (the first side surface 22a2 and the second side surface 22a3) are connected to the top surface 22a1, and the gate oxide layer 23 covers the top surface 22a1 and the side surfaces (the first side surface 22a2 and the second side surface 22a3).

[0075] It can be understood that in this embodiment, the active layer 22 is set to at least one fin 22a, and then the gate oxide layer 23 is covered on the top and side surfaces of the fin 22a. The structure of the Fin-FET formed in this way is mainly composed of a tall and thin fin raised on an insulating substrate, with the source and drain poles at both ends respectively, and the gate is close to its side walls and top for assisting current control. This fin-shaped structure increases the surface of the gate surrounding the channel and strengthens the control of the gate over the channel, thereby effectively alleviating the short channel effect that occurs in planar devices, greatly improving circuit control and reducing leakage current, and also greatly shortening the gate length of the transistor. Precisely because of this feature, the Fin-FET does not require a highly doped channel, and therefore can effectively reduce the impurity ion scattering effect and improve the channel carrier mobility.

[0076] As shown in Figure 5, Figure 5 is a structural schematic diagram of the second embodiment of the second semiconductor structure 20, the first semiconductor structure 10 includes a first insulating layer 11, and the second semiconductor structure 20 includes a second insulating layer 21, an active layer 22, a gate oxide layer 23 and a gate layer 24, and one side of the second insulating layer 21 is bonded to the first insulating layer 11.

[0077] Among them, the second insulating layer 21 includes at least one step portion 21a protruding from the side away from the first semiconductor structure 10, the active layer 22 is arranged on the side of the second insulating layer 21 away from the first semiconductor structure 10, the active layer 22 of the second well region includes at least one fin 22a, and at least one fin 22a is respectively arranged on at least one step portion 21a; the gate oxide layer 23 is arranged on the fin 22a; and the gate layer 24 is arranged on the gate oxide layer 23.

[0078] It can be understood that in the etching process, during the etching of the active layer 22, the second insulating layer 21 will be further partially etched to form the step portion 21a. Therefore, the step portion 21a and the fin portion 22a formed by etching the active layer 22 are one-to-one corresponding. In this embodiment, the width of the contact surface between the step portion 21a and the fin portion 22a along the X direction is equal to the width of the contact surface between the fin portion 22a and the step portion 21a along the X direction.

[0079] Further refer to Figure 6, which is a structural schematic diagram of the third embodiment of the second semiconductor structure 20. The first semiconductor structure 10 includes a first insulating layer 11, and the second semiconductor structure 20 includes a second insulating layer 21, an active layer 22, a gate oxide layer 23 and a gate layer 24. One side of the second insulating layer 21 is bonded to the first insulating layer 11.

[0080] Among them, the second insulating layer 21 includes at least one step portion 21a protruding from the side away from the first semiconductor structure 10, the active layer 22 is arranged on the side of the second insulating layer 21 away from the first semiconductor structure 10, the active layer 22 of the second well region includes at least one fin 22a, and at least one fin 22a is respectively arranged on at least one step portion 21a; the gate oxide layer 23 is arranged on the fin 22a; and the gate layer 24 is arranged on the gate oxide layer 23.

[0081] In this embodiment, the width of the contact surface between the step portion 21 a and the fin portion 22 a along the X direction is smaller than the width of the contact surface between the fin portion 22 a and the step portion 21 a along the X direction.

[0082] It can be understood that in the etching process, during the etching of the active layer 22, the second insulating layer 21 will be further partially etched to form the step portion 21a; further, based on the degree of etching, the two sides of the step portion 21a along the X direction will be etched to a certain extent (side etching), so that the width of the contact surface between the step portion 21a and the fin 22a along the X direction is smaller than the width of the contact surface between the fin 22a and the step portion 21a along the X direction.

[0083] Please refer to Figure 7 for details. Figure 7 is a partial schematic diagram of the fin in Figure 6. Along the thickness direction (Z direction) of the fin 22a, due to the etching process, the width of its upper end along the X direction is smaller than the width of its lower end along the X direction; further, the fin 22a includes a top surface 22a1 and side surfaces (a first side surface 22a2 and a second side surface 22a3). Due to the side etching, the bottom surface of the fin 22a (a first bottom surface 22a4 and a second bottom surface 22a5) will be further formed. The bottom surface is a non-contact surface of the fin 22a that is suspended outside the contact surface of the step portion 21a. Among them, the first side surface 22a2 and the second side surface 22a3 are two side surfaces symmetrical based on the YZ plane, the top surface 22a1 is parallel to the extension plane of the second insulating layer 21, the first bottom surface 22a4 and the second bottom surface 22a5 are two side surfaces symmetrical based on the YZ plane, and the side surfaces (the first side surface 22a2 and the second side surface 22a3) connect the top surface 22a1 and the bottom surface. Specifically, the first side surface 22a2 connects the top surface 22a1 and the first bottom surface 22a4, and the second side surface 22a3 connects the top surface 22a1 and the second bottom surface 22a5. The gate oxide layer 23 covers the top surface 22a1, the side surfaces (the first side surface 22a2 and the second side surface 22a3) and the bottom surface (the first bottom surface 22a4 and the second bottom surface 22a5).

[0084] It can be understood that in this embodiment, the active layer 22 is set to at least one fin 22a, and then the gate oxide layer 23 is covered on the top, side and bottom surfaces of the fin 22a. The structure of the Fin-FET formed in this way is mainly composed of a tall and thin fin raised on an insulating substrate, with the source and drain poles at both ends respectively, and the gate is close to its side wall, top and part of the bottom to assist in current control. This fin-shaped structure increases the surface of the gate surrounding the channel and strengthens the control of the gate over the channel, thereby effectively alleviating the short channel effect in planar devices, greatly improving circuit control and reducing leakage current, and also greatly shortening the gate length of the transistor. Precisely because of this feature, the Fin-FET does not require a highly doped channel, so it can effectively reduce the impurity ion scattering effect and improve the channel carrier mobility.

[0085] In combination with the above embodiment, in an optional embodiment, the thickness of the fin along the Z direction is 30nm-65nm, and in a further embodiment, 40nm-55nm can be selected. It can be understood that in one embodiment, since the high-voltage well region and the low-voltage well region are produced on the same active layer, the active layer is generally selected to be around 100nm, and then during the etching process of the active layer, the entire thickness of the active layer is not etched, the overall thickness of the semiconductor device is large, the process is complex and the cost is high; while this embodiment only requires the selection of an active layer of 30nm-65nm for preparation, compared with the traditional process, the overall thickness of the semiconductor device formed is reduced, and the process is simple and the cost is controllable.

[0086] In one embodiment, the first well region of the first semiconductor structure 10 is a high-voltage well region HV, and the second well region of the second semiconductor structure 20 is a low-voltage well region (including a low-voltage well region LV and an ultra-low-voltage well region LLV). The first well region is provided with a planar transistor, and the second well region is provided with a fin field-effect transistor. The thickness of the gate oxide layer corresponding to the low-voltage well region LV is greater than the thickness of the gate oxide layer corresponding to the ultra-low-voltage well region LLV. Furthermore, the thickness of the gate oxide layer of the planar transistor in the high-voltage well region HV is greater than the thickness of the gate oxide layer of the fin field-effect transistor in the low-voltage well region LV and the ultra-low-voltage well region LLV.

[0087] As shown in Figure 8, Figure 8 is a structural schematic diagram of the fourth embodiment of the second semiconductor structure 20, the first semiconductor structure 10 includes a first insulating layer 11, the second semiconductor structure 20 includes a second insulating layer 21, an active layer 22, a gate oxide layer 23, a gate layer 24 and a first isolation structure 25a, and one side of the second insulating layer 21 is bonded to the first insulating layer 11.

[0088] Among them, the active layer 22 is arranged on the side of the second insulating layer 21 away from the first semiconductor structure 10, and the active layer 22 of the second well region includes at least one fin 22a; the gate oxide layer 23 is arranged on the fin 22a; the gate layer 24 is arranged on the gate oxide layer 23; the first isolation structure 25a is used to isolate the gate layers 24 corresponding to two adjacent fins 22a.

[0089] Optionally, the first isolation structure 25a can be set specifically according to the function of the fin field-effect transistor in the well region. For example, if some transistors share a gate, the gate layers corresponding to these transistors do not need to be isolated by the first isolation structure 25a. If the functions of two adjacent transistors are different and they cannot share the same gate, the gate layers corresponding to the two transistors need to be isolated by the first isolation structure 25a.

[0090] As shown in Figure 9, Figure 9 is a structural schematic diagram of the fifth embodiment of the second semiconductor structure 20, the first semiconductor structure 10 includes a first insulating layer 11, the second semiconductor structure 20 includes a second insulating layer 21, an active layer 22, a gate oxide layer 23, a gate layer 24 and a second isolation structure 25b, and one side of the second insulating layer 21 is bonded to the first insulating layer 11.

[0091] The active layer 22 is disposed on a side of the second insulating layer 21 facing away from the first semiconductor structure 10. The active layer 22 in the second well region includes at least one fin 22a. A gate oxide layer 23 is disposed on the fin 22a. A gate layer 24 is disposed on the gate oxide layer 23. The second isolation structure 25b is used to isolate the gate layers 24 corresponding to different well regions. For example, in one embodiment, the second isolation structure 25b is used to isolate a low-voltage well region (LV) from an ultra-low-voltage well region (LLV).

[0092] It can be understood that in the embodiments of Figures 8 and 9 above, the location and shape of the first isolation structure 25a and the second isolation structure 25b are schematic and can be arbitrarily set according to actual needs in specific application scenarios, and are not limited here.

[0093] The following is an introduction to the preparation process of the above-mentioned semiconductor device.

[0094] As shown in FIG10 , FIG10 is a schematic flow chart of an embodiment of a method for manufacturing a semiconductor device provided by the present application, the manufacturing method comprising:

[0095] Step 101: providing a first semiconductor structure and a second semiconductor structure, wherein the first semiconductor structure includes a first well region, and the second semiconductor structure includes a second well region.

[0096] As shown in FIG. 1 , optionally, the first semiconductor structure 10 and the second semiconductor structure 20 may be wafers.

[0097] In one embodiment, the first well region is a high voltage (HV) well region, and the second well region is a low voltage well region. Furthermore, the low voltage well region may further include a first sub-well region and a second sub-well region. The first sub-well region is, for example, an LV (Low Voltage) well region, and the second sub-well region is, for example, an LLV (Low Low Voltage) well region.

[0098] Step 102: Bond the first semiconductor structure and the second semiconductor structure.

[0099] Alternatively, in one embodiment, as shown in FIG11 , which is a schematic structural diagram of an embodiment of step 102 in FIG10 , the first semiconductor structure 10 includes a first insulating layer 11, and the second semiconductor structure 20 includes an active layer 22. Before the first semiconductor structure 10 and the second semiconductor structure 20 are bonded together, a second insulating layer 21 is first formed on the active layer 22, and then the first insulating layer 11 side of the first semiconductor structure 10 and the second insulating layer 21 side of the second semiconductor structure 20 are bonded together.

[0100] Optionally, the active layer is a thin film on the wafer, which is made of semiconductor material and has a thickness generally between a few hundred nanometers and a few tens of nanometers. Its function is to penetrate the electronically active material on the surface of the wafer into the surface of the wafer so that components can be manufactured thereon.

[0101] The active layer may be made of silicon (single crystal silicon, polycrystalline silicon or amorphous silicon), germanium (single crystal germanium), silicon germanium, etc., and may also be P-type doped or N-type doped.

[0102] Optionally, the first insulating layer 11 and the second insulating layer 21 may be made of materials such as silicon nitride and silicon oxide.

[0103] Step 103 : Form a fin field-effect transistor in the second well region of the second semiconductor structure.

[0104] Optionally, as shown in FIG12 , FIG12 is a flowchart of a first embodiment of step 103 in FIG10 , and step 103 may include:

[0105] Step 1031: forming at least one groove on the active layer, with the second insulating layer exposed at the bottom of the groove, and the groove isolating the active layer into at least one fin.

[0106] As shown in FIG13 , FIG13 is a structural diagram of an embodiment of step 1031 in FIG12 , at least one groove A is formed on the active layer 22 , the bottom of the groove A exposes the second insulating layer 21 , and the groove A isolates the active layer 22 into at least one fin 22 a.

[0107] Optionally, the groove A may be formed by an etching process. It is understandable that due to the etching process, the cross-section of the fin 22 a resembles a trapezoid that is narrow at the top and wide at the bottom.

[0108] Optionally, the thickness of the fin along the Z direction is 30 nm-65 nm. Therefore, in one embodiment, if the thickness of the active layer 22 is greater than this thickness, the step 1031 may further include: thinning the active layer 22 .

[0109] Step 1032: Form a gate oxide layer on a top surface and side surfaces of at least one fin.

[0110] As shown in FIG. 14 , FIG. 14 is a structural diagram of an embodiment of step 1032 in FIG. 12 , in which a gate oxide layer 23 is formed on at least one fin 22 a .

[0111] In one embodiment, as shown in Figure 4, the fin 22a includes a top surface 22a1 and side surfaces (a first side surface 22a2 and a second side surface 22a3), wherein the first side surface 22a2 and the second side surface 22a3 are two side surfaces symmetrical based on the YZ plane, the top surface 22a1 is parallel to the extension plane of the second insulating layer 21, the side surfaces (the first side surface 22a2 and the second side surface 22a3) are connected to the top surface 22a1, and the gate oxide layer 23 covers the top surface 22a1 and the side surfaces (the first side surface 22a2 and the second side surface 22a3).

[0112] Optionally, step 1032 may specifically include: forming a gate oxide layer 23 on the top surface 22a1 and side surfaces (the first side surface 22a2 and the second side surface 22a3) of the at least one fin 22a.

[0113] Step 1033: Form a gate layer on the gate oxide layer.

[0114] Optionally, as shown in FIG15 , FIG15 is a flowchart of a second embodiment of step 103 in FIG10 , and step 103 may include:

[0115] Step 103a: forming at least one groove on the active layer, the groove isolating the active layer into at least one fin, exposing the second insulating layer at the bottom of the groove and forming at least one step portion on the second insulating layer that protrudes away from the first semiconductor structure and corresponds to the at least one fin.

[0116] As shown in Figure 16, Figure 16 is a structural schematic diagram of an embodiment of step 103a in Figure 15, where at least one groove A is formed on the active layer 22, and the groove A isolates the active layer 22 into at least one fin 22a. The bottom of the groove A exposes the second insulating layer 21 and forms at least one step portion 21a in the second insulating layer 21 that protrudes on one side away from the first semiconductor structure 10 and corresponds to the at least one fin 22a.

[0117] In this embodiment, the width of the contact surface between the step portion 21 a and the fin portion 22 a along the X direction is smaller than the width of the contact surface between the fin portion 22 a and the step portion 21 a along the X direction.

[0118] It can be understood that in the etching process, during the etching of the active layer 22, the second insulating layer 21 will be further partially etched to form the step portion 21a; further, based on the degree of etching, the two sides of the step portion 21a along the X direction will be etched to a certain extent (side etching), so that the width of the contact surface between the step portion 21a and the fin 22a along the X direction is smaller than the width of the contact surface between the fin 22a and the step portion 21a along the X direction.

[0119] Step 103b: forming a gate oxide layer on the top surface, side surfaces and bottom surface of at least one fin.

[0120] As shown in FIG17 , FIG17 is a structural diagram of an embodiment of step 103b in FIG15 .

[0121] In one embodiment, as shown in FIG7 , along the thickness direction (Z direction) of the fin 22 a , due to the etching process, the width of its upper end along the X direction is smaller than the width of its lower end along the X direction; further, the fin 22 a includes a top surface 22 a 1 and side surfaces (a first side surface 22 a 2 and a second side surface 22 a 3 ). Since the side etching further forms the bottom surface of the fin 22 a (a first bottom surface 22 a 4 and a second bottom surface 22 a 5 ), the bottom surface is a non-contact surface of the fin 22 a that is suspended outside the contact surface of the step portion 21 a. Among them, the first side surface 22a2 and the second side surface 22a3 are two side surfaces symmetrical based on the YZ plane, the top surface 22a1 is parallel to the extension plane of the second insulating layer 21, the first bottom surface 22a4 and the second bottom surface 22a5 are two side surfaces symmetrical based on the YZ plane, and the side surfaces (the first side surface 22a2 and the second side surface 22a3) connect the top surface 22a1 and the bottom surface. Specifically, the first side surface 22a2 connects the top surface 22a1 and the first bottom surface 22a4, and the second side surface 22a3 connects the top surface 22a1 and the second bottom surface 22a5. The gate oxide layer 23 covers the top surface 22a1, the side surfaces (the first side surface 22a2 and the second side surface 22a3) and the bottom surface (the first bottom surface 22a4 and the second bottom surface 22a5).

[0122] Step 103c: forming a gate layer on the gate oxide layer.

[0123] Optionally, in one embodiment, step 1033 and step 103c may specifically include: forming a gate layer on the gate oxide layer and the exposed second insulating layer; thinning the gate layer to expose the top surface of the gate oxide layer, and the top surface of the gate oxide layer is parallel to the extension plane of the second insulating layer.

[0124] Optionally, in the embodiments of Figures 12 and 15 above, before forming the gate insulating layer 23, a liner layer may be formed on the fin 22a, then removed, and the gate insulating layer 23 preparation step may be performed. Optionally, the liner layer may include a dielectric material, such as silicon oxide, silicon nitride, and / or other suitable materials. It will be appreciated that the liner layer may be a catalytic layer for promoting adhesion to the continuously disposed gate oxide layer material, or a barrier layer for preventing possible contamination of the fin 22a due to the subsequent deposition of isolation material. For example, the liner layer may be silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbide nitride, titanium nitride, tantalum nitride, any suitable material, and / or combinations thereof.

[0125] Optionally, in one embodiment, a first isolation structure and a second isolation structure may be further formed. As shown in FIG8 , a first isolation structure 25 a is formed on the second insulating layer 21 to isolate the gate layers 24 corresponding to two adjacent fins 22 a. The first isolation structure 25 a penetrates the gate layer 24 along the Z direction.

[0126] Optionally, the first isolation structure 25a can be set specifically according to the function of the fin field-effect transistor in the well region. For example, if some transistors share a gate, the gate layers corresponding to these transistors do not need to be isolated by the first isolation structure 25a. If the functions of two adjacent transistors are different and they cannot share the same gate, the gate layers corresponding to the two transistors need to be isolated by the first isolation structure 25a.

[0127] As shown in FIG9 , a second isolation structure 25b is formed on the gate oxide layer 23 to isolate the gate layers 24 corresponding to different well regions. The second isolation structure 25b penetrates the gate layer 24 along the Z direction.

[0128] It can be understood that in the embodiments of Figures 8 and 9 above, the location and shape of the first isolation structure 25a and the second isolation structure 25b are schematic and can be arbitrarily set according to actual needs in specific application scenarios, and are not limited here.

[0129] Optionally, as shown in FIG. 2 , after the fin field effect transistor of the second semiconductor structure 20 is fabricated, the memory array structure 30 and the second semiconductor structure 20 may be further bonded to form a three-dimensional memory.

[0130] It can be understood that the preparation process provided in the embodiment of the present application prepares a fin field effect transistor in one of the semiconductor structures after bonding two semiconductor structures. On the one hand, the first well region and the second well region are respectively arranged on two semiconductor structures (such as wafers), and the second well region of the second semiconductor structure is provided with a fin field effect transistor. Compared with the traditional technology, the two well regions are arranged on the same wafer, or the two well regions are arranged on two wafers respectively but no fin field effect transistor is adopted, the method of the embodiment of the present application can adopt fin field effect transistors on the basis of reducing the chip area to improve the performance of the transistor; on the other hand, compared with the traditional production of fin field effect transistors, such a preparation process reduces the filling and planarization of shallow trench isolation, and also reduces the wet etching process of the isolation trench, so the cost is lower and the preparation efficiency is higher.

[0131] Referring to FIG. 18 , FIG. 18 is a schematic diagram of the structure of an embodiment of a storage system provided by the present application. The storage system 200 includes at least one semiconductor device 100 and a controller 202. Controller 202 is coupled to semiconductor device 100 to control semiconductor device 100 to store data. Storage system 200 can be integrated into various memory cards, such as personal computer memory card international association (PCMCIA or PC), compact flash (CF) card, smart media (SM) card, memory stick, multimedia card (MMC), secure digital memory card (SD), universal flash storage (UFS), and solid state drives (SSD).

[0132] The controller 202 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones.

[0133] Alternatively, the controller 202 is configured to operate in a high duty cycle environment SSD or eMMC used for data storage in mobile devices such as smartphones, tablets, laptops, and enterprise storage arrays.

[0134] Alternatively, the controller 202 is configured to manage data stored in the semiconductor device 100 and communicate with an external device (e.g., a host) according to a specific communication protocol, wherein the communication protocol includes at least one of a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a PCI-E (Peripheral Component Interconnect Express) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer system interface (SCSI) protocol, an enhanced small drive interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, and a FireWire protocol.

[0135] The controller 202 may also be configured to control operations of the semiconductor device 100, such as read, erase, and program operations. In some embodiments, the controller 202 may also be configured to manage various functions related to data stored or to be stored in the semiconductor device 100, including at least one of bad block management, garbage collection, logical-to-physical address translation, and wear leveling. In some embodiments, the controller 202 may also be configured to process error correction codes for data read from or written to the semiconductor device 100. The controller 202 may also perform any other suitable functions, such as formatting the semiconductor device 100.

[0136] Optionally, the semiconductor device 100 in this embodiment is the semiconductor device 100 described in the above embodiment, or is a semiconductor device 100 manufactured using the manufacturing method described in the above embodiment. In one embodiment, the semiconductor device 100 is a three-dimensional memory device.

[0137] The above is a detailed introduction to the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. At the same time, for those skilled in the art, based on the ideas of the present application, there may be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A semiconductor device, It is characterized in that include: a first semiconductor structure, the first semiconductor structure comprising a first well region; A second semiconductor structure is bonded to the first semiconductor structure, the second semiconductor structure comprises a second well region, wherein the second well region of the second semiconductor structure is provided with a fin field effect transistor.

2. The semiconductor device according to claim 1, It is characterized in that The first semiconductor structure includes a first insulating layer; The second semiconductor structure comprises: a second insulating layer, one side of the second insulating layer being bonded to the first insulating layer; an active layer, the active layer being disposed on a side of the second insulating layer away from the first semiconductor structure, the active layer of the second well region comprising at least one fin; A gate oxide layer, wherein the gate oxide layer is disposed on the fin; A gate layer is disposed on the gate oxide layer.

3. The semiconductor device according to claim 2, It is characterized in that The thickness of the fin along the Z direction is 30 nm-65 nm, wherein the Z direction is a direction perpendicular to an extension plane of the second insulating layer.

4. The semiconductor device according to claim 2, It is characterized in that The fin portion includes a top surface and a side surface, the top surface is parallel to an extension plane of the second insulating layer, the side surface is connected to the top surface, and the gate oxide layer covers the top surface and the side surface.

5. The semiconductor device according to claim 2, It is characterized in that The second insulating layer includes at least one step portion protruding from a side away from the first semiconductor structure, and the at least one fin portion is correspondingly disposed on the at least one step portion.

6. The semiconductor device according to claim 5, It is characterized in that The width of the contact surface between the step portion and the fin along the X direction is equal to the width of the contact surface between the fin portion and the step portion along the X direction, and the X direction is the arrangement direction of at least one of the fins.

7. The semiconductor device according to claim 5, It is characterized in that The width of the contact surface between the step portion and the fin portion along the X direction is smaller than the width of the contact surface between the fin portion and the step portion along the X direction. The fin portion further includes a top surface, a side surface and a bottom surface. The bottom surface is a non-contact surface of the fin portion suspended outside the contact surface of the step portion. The gate oxide layer covers the top surface, the side surface and the bottom surface. The X direction is the arrangement direction of at least one of the fin portions.

8. The semiconductor device according to claim 2, It is characterized in that The second well region includes a first sub-well region and a second sub-well region, and the thickness of the gate oxide layer in the first sub-well region is greater than the thickness of the gate oxide layer in the second sub-well region.

9. The semiconductor device according to claim 2, It is characterized in that The second semiconductor structure further includes a first isolation structure, and the first isolation structure is used to isolate the gate layers corresponding to two adjacent fins.

10. The semiconductor device according to claim 2, It is characterized in that The second semiconductor structure further includes a second isolation structure, and the second isolation structure is used to isolate the gate layers corresponding to different well regions.

11. The semiconductor device according to claim 1, It is characterized in that A planar transistor is disposed on the first semiconductor structure in the first well region.

12. The semiconductor device according to claim 11, It is characterized in that The thickness of the gate oxide layer of the planar transistor is greater than the thickness of the gate oxide layer of the fin field effect transistor.

13. The semiconductor device according to claim 1, It is characterized in that The semiconductor device further includes a storage array structure bonded to the second semiconductor structure.

14. A method for preparing a semiconductor device, It is characterized in that include: Providing a first semiconductor structure and a second semiconductor structure, wherein the first semiconductor structure includes a first well region, and the second semiconductor structure includes a second well region; bonding the first semiconductor structure and the second semiconductor structure; A fin field effect transistor is formed in the second well region of the second semiconductor structure.

15. The preparation method according to claim 14, It is characterized in that The first semiconductor structure includes a first insulating layer, and the second semiconductor structure includes an active layer; The step of bonding the first semiconductor structure to the second semiconductor structure comprises: forming a second insulating layer on the active layer; The second insulating layer is bonded to the first insulating layer, so that the first semiconductor structure is bonded to the second semiconductor structure.

16. The preparation method according to claim 15, It is characterized in that The forming of a fin field effect transistor in the second well region of the second semiconductor structure comprises: forming at least one groove on the active layer, wherein the second insulating layer is exposed at the bottom of the groove, and the groove isolates the active layer into at least one fin; forming a gate oxide layer on at least one of the fins; A gate layer is formed on the gate oxide layer.

17. The preparation method according to claim 16, It is characterized in that Before forming at least one groove on the active layer, the method further includes: The active layer is thinned.

18. The preparation method according to claim 16, It is characterized in that Before forming a gate oxide layer on at least one of the fins, the method further includes: forming a liner on at least one of the fins; The liner is removed.

19. The preparation method according to claim 16, It is characterized in that The fin portion includes a top surface and a side surface, the top surface is parallel to the extension plane of the second insulating layer, and the side surface is connected to the top surface; The forming of a gate oxide layer on at least one of the fins comprises: A gate oxide layer is formed on the top surface and the side surfaces of at least one of the fins.

20. The preparation method according to claim 16, It is characterized in that The forming of at least one groove on the active layer comprises: At least one groove is formed on the active layer, the groove isolates the active layer into at least one fin, the bottom of the groove exposes the second insulating layer and forms at least one step portion of the second insulating layer that protrudes away from one side of the first semiconductor structure and corresponds to at least one of the fins.

21. The preparation method according to claim 20, It is characterized in that The width of the contact surface between the step portion and the fin portion along the X direction is smaller than the width of the contact surface between the fin portion and the step portion along the X direction, the fin portion further comprises a top surface, a side surface and a bottom surface, the bottom surface is a non-contact surface of the fin portion suspended outside the contact surface of the step portion, and the X direction is an arrangement direction of at least one of the fin portions; The forming of a gate oxide layer on at least one of the fins comprises: A gate oxide layer is formed on the top surface, the side surface, and the bottom surface of at least one of the fins.

22. The preparation method according to claim 16, It is characterized in that The step of forming a gate layer on the gate oxide layer comprises: forming a gate layer on the gate oxide layer and the exposed second insulating layer; The gate layer is thinned to expose a top surface of the gate oxide layer, and the top surface of the gate oxide layer is parallel to an extension plane of the second insulating layer.

23. The preparation method according to claim 16, It is characterized in that After forming a gate layer on the gate oxide layer, the method further comprises: A first isolation structure is formed on the second insulating layer to isolate the gate layers corresponding to two adjacent fins.

24. The preparation method according to claim 16, It is characterized in that After forming a gate layer on the gate oxide layer, the method further comprises: A second isolation structure is formed on the gate oxide layer to isolate the gate layers corresponding to different well regions.

25. The preparation method according to claim 16, It is characterized in that The method further comprises: Providing a storage array structure; The memory array structure and the second semiconductor structure are bonded together.

26. A storage system, It is characterized in that The storage system includes a semiconductor device and a controller, wherein the controller is coupled to the semiconductor device to control the semiconductor device to store data, and the semiconductor device is a semiconductor device as described in any one of claims 1-13, or the semiconductor device is a semiconductor device prepared by the preparation method as described in any one of claims 14-25.

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