Scintillation pulse sampling device and method, electronic device and storage medium

Abstract

The embodiment of the invention provides pulse sampling equipment, a pulse sampling method, electronic equipment and a storage medium. A main chip configures a voltage threshold of each threshold module through each voltage unit; the system module determines the number of target threshold modules needing to be started for detection according to the estimated voltage amplitude of the scintillation pulse signal, and starts each target threshold module through a starting instruction; the flicker pulse signals are input into the target threshold modules in parallel, the flicker pulse signals and corresponding voltage threshold signals output by the voltage unit are connected to the input end of the threshold comparator, and comparison signals output by the threshold comparator are sent to the system module; the system module determines each voltage threshold of the scintillation pulse signal and corresponding detection time according to the comparison signal; and the system module recovers the waveform of the scintillation pulse signal according to the time sequence according to all the integrated detection time-voltage threshold pair information, so that the sampling requirement of the scintillation pulse signal can be adapted, and the sampling and restoring accuracy of the scintillation pulse can be improved.

Description

Technical Field

[0001] The present application relates to the field of ionizing radiation detection, and in particular to a pulse sampling device, method, electronic device and storage medium. Background Art

[0002] Scintillation detectors acquire information about the particles and their energy deposition by detecting the fluorescence produced by the interaction of high-energy particles, such as gamma and X-rays, with certain substances. They are widely used in radiation detection and imaging equipment, including high-energy physics experiments, nuclear medicine imaging, and industrial flaw detection and inspection. They offer high detection efficiency, fast response, and high measurement accuracy.

[0003] Traditionally, an analog-to-digital converter (ADC) is used to digitally sample the electrical signal generated by a scintillation detector. However, using an ADC to digitally sample electrical signals is difficult and expensive to implement.

[0004] In the field of radiation detection and imaging, in order to reduce the cost of digital sampling of electrical signals, the existing technology generally adopts a multi-voltage threshold (hereinafter referred to as MVT) sampling method. However, the number of sampling time points collected by this method is limited (usually 8) and the corresponding voltage threshold is fixed (usually the voltage threshold setting that makes the scintillation pulse within a fixed energy window have the best sampling and reconstruction effect). When facing particle detection with a wide energy dynamic range, the preset voltage threshold may be at the very bottom of the entire scintillation pulse, or exceed the entire scintillation pulse. The MVT method is stretched in this situation. For example, in a proton therapy monitoring system, faced with gamma and neutrons with energy ranges spanning several orders of magnitude, the existing MVT method has difficulty in accurately restoring the signal and obtaining key particle information.

[0005] Therefore, a scintillation pulse sampling method with a wide dynamic range is urgently needed. Summary of the Invention

[0006] In order to solve at least one of the above technical problems, embodiments of the present application provide a pulse sampling device, method, electronic device and storage medium.

[0007] In a first aspect, an embodiment of the present application provides a flicker pulse sampling device, comprising a system module and a threshold voltage module, wherein the system module comprises a main chip, and the main chip is provided with a chip select pin and a signal pin; the threshold voltage module comprises a plurality of threshold modules, each threshold module is provided with a signal input terminal, a voltage input terminal, a signal output terminal, a chip select unit, a threshold comparator and a plurality of voltage units, in each threshold module, the voltage input terminal is connected to the main chip, the output terminal of the voltage unit and the signal input terminal are respectively connected to the input terminal of the threshold comparator, the chip select unit is connected to the chip select pin of the main chip, and the output terminal of the threshold comparator is connected to the signal pin of the main chip via the signal output terminal; the main chip The voltage threshold of each threshold module is configured by each voltage unit; the system module determines the number of target threshold modules that need to be started for detection based on the estimated voltage amplitude of the flicker pulse signal, and starts each target threshold module through a start instruction; the flicker pulse signal is input into each target threshold module in parallel, and the flicker pulse signal and the corresponding voltage threshold signal output by the voltage unit are respectively connected to the input end of the threshold comparator, and the comparison signal output by the threshold comparator is sent to the system module; the system module determines each voltage threshold and the corresponding detection time of the flicker pulse signal based on the comparison signal; the system module restores the waveform of the flicker pulse signal in a time sequence based on the integrated information of all detection time-voltage threshold pairs.

[0008] According to a specific embodiment of the present application, the voltage unit includes a digital-to-analog converter.

[0009] According to a specific embodiment of the present application, the voltage unit includes a digital-to-analog converter and a voltage dividing resistor connected in series to the digital-to-analog converter.

[0010] According to a specific embodiment of the present application, the voltage divider resistors in each voltage unit in the threshold module are equivalent circuits.

[0011] According to a specific implementation of the present application, the threshold comparator is a differential comparator.

[0012] According to a specific embodiment of the present application, the chip select unit includes an AND gate circuit and an inversion circuit. The chip select unit is connected to one input end of the AND gate circuit via the inversion circuit, the signal input end is connected to the other input end of the AND gate circuit, and the output end of the AND gate circuit is connected to the signal input end of each threshold comparator.

[0013] According to a specific embodiment of the present application, the main chip configures the voltage threshold of each threshold module through serial communication, and stores the voltage threshold setting in an erasable memory. The threshold module automatically reads the voltage threshold from the erasable memory each time it is powered on.

[0014] According to a specific implementation of the present application, the threshold module and the system module are connected in a plug-in manner; the main chip and each threshold module are connected in a plug-in manner.

[0015] According to a specific embodiment of the present application, the number of the threshold modules is M, the number of voltage units in each threshold module is N, and the number of voltage thresholds of the system module is M×N, where M≥2 and N is a positive integer.

[0016] According to a specific embodiment of the present application, the voltage thresholds corresponding to adjacent threshold modules gradually increase and the spacings are equal, and the voltage thresholds corresponding to adjacent voltage units in the same threshold module gradually increase and the spacings are equal.

[0017] According to a specific embodiment of the present application, the system module is configured to identify the number of enabled threshold modules and adaptively change the size interval of the corresponding voltage threshold in each threshold module to adapt to the corresponding number of thresholds.

[0018] In the second aspect, an embodiment of the present application provides a flicker pulse sampling method, including: the main chip configures the voltage threshold of each threshold module through each voltage unit; the system module determines the number of target threshold modules that need to be started for detection based on the estimated voltage amplitude of the flicker pulse signal, and starts each target threshold module through a start instruction; the flicker pulse signal is input into each target threshold module in parallel, and the flicker pulse signal and the corresponding voltage threshold signal output by the voltage unit are respectively connected to the input end of the threshold comparator, and the comparison signal output by the threshold comparator is sent to the system module; the system module determines the voltage thresholds and corresponding detection time of the flicker pulse signal based on the comparison signal; the system module restores the waveform of the flicker pulse signal in a time series based on the integrated information of all detection time-voltage threshold pairs.

[0019] According to a specific embodiment of the present application, the system module determines the number of target threshold modules that need to be started based on the estimated voltage amplitude of the flicker pulse signal, and before the step of starting each target threshold module through a start instruction, the flicker pulse sampling method also includes: judging whether the voltage threshold of the system module covers the estimated voltage amplitude of the flicker pulse signal; if the voltage threshold of the system module covers the estimated voltage amplitude of the flicker pulse signal, executing the step of determining the number of target threshold modules that need to be started based on the estimated voltage amplitude of the flicker pulse signal; if the voltage threshold of the system module does not cover the estimated voltage amplitude of the flicker pulse signal, adjusting the estimated voltage amplitude of the flicker pulse signal so that the estimated voltage amplitude of the flicker pulse signal after adjustment is within the coverage range of the voltage threshold of the system module.

[0020] According to a specific embodiment of the present application, the step of the system module determining the number of target threshold modules that need to be started based on the estimated voltage amplitude of the flicker pulse signal includes: determining the number of target threshold modules that need to be started based on the estimated voltage amplitude of the flicker pulse signal, the detection voltage accuracy and the number of voltage units in each threshold module; and selecting a threshold module that meets the quantity requirements from all threshold modules as the target threshold module.

[0021] According to a specific embodiment of the present application, after the step of starting each target threshold module through a startup instruction, the flicker pulse sampling method also includes: configuring the voltage threshold of each target threshold module; splitting the voltage threshold of each target threshold module into voltage thresholds of corresponding voltage units.

[0022] According to a specific embodiment of the present application, the voltage threshold of each target threshold module is split into the voltage threshold of the corresponding voltage unit in the following manner: the number of the threshold modules is M, the number of the voltage units is N, M and N are both positive integers, and the number accuracy of the voltage threshold required for detection is P = M × N; the voltage threshold of the i-th target threshold module is sequentially recorded as V i×N , where 1≤i≤M; the voltage threshold value V of the i-th target threshold module i×N The voltage threshold of each voltage unit in the corresponding N voltage units is split.

[0023] According to a specific embodiment of the present application, the step of starting each target threshold module through a start instruction includes: switching the chip select pin corresponding to each target threshold module to a low level; the signal input end of each target threshold module is connected to the flickering pulse signal in parallel, and the input end of the threshold comparator is respectively connected to the flickering pulse signal and the voltage threshold signal output by each voltage unit, the chip select pin is high by default, and the chip select pin corresponding to each target threshold module is low after being inverted, and is ANDed with the flickering pulse signal, and the output clock is low, which will not trigger the corresponding target threshold module; when the corresponding target threshold module needs to be triggered, the chip select signal of the corresponding target threshold module is pulled low, and the flickering pulse signal is valid.

[0024] According to a specific embodiment of the present application, the flicker pulse signal and the corresponding voltage threshold signal output by the voltage unit are respectively connected to the input end of the threshold comparator, and the comparison signal output by the threshold comparator is sent to the system module, including: the low-level chip select signal connected to the chip select unit is inverted by the inversion circuit of the chip select unit and then input into the AND gate circuit of the chip select unit; the flicker pulse signal is input into the AND gate circuit via the signal input end; the output end of the AND gate circuit inputs the flicker pulse signal into the signal input end of each threshold comparator.

[0025] According to a specific embodiment of the present application, after the step of determining the number of target threshold modules that need to be started based on the estimated voltage amplitude of the flicker pulse signal, the detection voltage accuracy and the number of voltage units in each threshold module, the flicker pulse sampling method also includes: obtaining predefined global variables, the global variables including the total threshold number, the effective threshold number and the noise threshold number, the total threshold number being the sum of the effective threshold number and the noise threshold number; calculating the actual threshold number contained in the target threshold module based on the number of threshold modules; if the actual threshold number is greater than the effective threshold number, determining that the flicker pulse signal is a valid signal.

[0026] According to a specific embodiment of the present application, a method for restoring the waveform of the scintillation pulse signal includes a scatter plot, a broken line graph, curve smoothing, and an equal time interval interpolation method.

[0027] According to a specific embodiment of the present application, the system module restores the waveform of the flicker pulse signal in a time series based on the integrated information of all detection time-voltage threshold pairs, including: determining the waveform characteristic parameters of the flicker pulse signal based on the comparison signal, and selecting a matching target fitting model based on the waveform characteristic parameters; and using the target fitting model to fit all detection time-voltage threshold pair information to obtain the waveform of the flicker pulse signal.

[0028] According to a specific embodiment of the present application, determining the waveform characteristic parameters of the flickering pulse signal based on the comparison signal includes: determining the voltage threshold and trigger time corresponding to each of the comparison signals; summarizing the voltage thresholds of all comparison signals to determine the actual voltage range of the flickering pulse signal; integrating the voltage thresholds corresponding to each trigger time to obtain the voltage sequence corresponding to the time series; and obtaining the waveform characteristic parameters of the pulse signal based on the voltage sequence corresponding to the time series.

[0029] According to a specific embodiment of the present application, the method further includes: the system module determines any two adjacent trigger times among all trigger times corresponding to the highest voltage threshold; and determines the peak interval of the flash pulse signal based on any two adjacent trigger times.

[0030] According to a specific embodiment of the present application, the step of the system module determining each voltage threshold value and the corresponding detection time of the scintillation pulse signal according to the comparison signal includes: determining the corresponding voltage threshold value of the voltage unit connected to the threshold comparator corresponding to the comparison signal;

[0031] Obtain the signal time when the flicker pulse signal corresponding to the comparison signal crosses the corresponding voltage threshold, and obtain the noise time when the flicker pulse signal corresponding to the comparison signal first crosses the corresponding voltage threshold; associate the voltage threshold corresponding to each comparison signal with the signal time and the noise time.

[0032] According to a specific embodiment of the present application, the noise time is determined by obtaining the first time point after the signal crosses the baseline and does not return to the baseline within a preset time.

[0033] According to a specific embodiment of the present application, the signal location time and / or the noise location time are both achieved by TDC identifying different transition point moments in the comparison signal.

[0034] According to a specific embodiment of the present application, the noise exposure time is acquired through a timing logic implemented by a threshold comparator and a TDC.

[0035] According to a specific embodiment of the present application, the step of obtaining the noise control time when the flicker pulse signal corresponding to the comparison signal first crosses the corresponding voltage threshold includes: if the flicker pulse signal is a single-peak pulse signal, obtaining the trigger time of the front / back trigger point of the rising edge and the trigger time of the front / back trigger point of the falling edge as the noise control time, and setting other times to zero; if the flicker pulse signal is a multi-peak pulse signal, obtaining the trigger time of all trigger points and marking the threshold number of each trigger point.

[0036] In a third aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and the computer program is configured to execute the scintillation pulse sampling device provided in the second aspect when executed.

[0037] In a fourth aspect, an embodiment of the present application provides an electronic device, comprising: a processor and a memory storing a computer program, wherein the processor is configured to execute the scintillation pulse sampling method provided in the second aspect when running the computer program.

[0038] The pulse sampling device, method, electronic device and storage medium provided by the present application are as follows: the main chip configures the voltage threshold of each threshold module through each voltage unit; the system module determines the number of target threshold modules that need to be started for detection according to the estimated voltage amplitude of the flicker pulse signal, and starts each target threshold module through a start instruction; the flicker pulse signal is input into each target threshold module in parallel, and the flicker pulse signal and the corresponding voltage threshold signal output by the voltage unit are respectively connected to the input end of the threshold comparator, and the comparison signal output by the threshold comparator is sent to the system module; the system module determines each voltage threshold of the flicker pulse signal and the corresponding detection time according to the comparison signal ; The system module restores the waveform of the scintillation pulse signal according to the time series based on the integrated information of all detection time-voltage threshold pairs, can perform sampling and processing on the scintillation pulse signal, can adapt to the sampling requirements of the scintillation pulse signal, has great flexibility, determines the amplitude range of the scintillation pulse signal to be sampled, ensures that the voltage threshold setting range completely covers the amplitude range of the scintillation pulse signal to be sampled, determines the voltage threshold accuracy, and combines the overall power consumption to determine the number of voltage threshold settings. It is suitable for a large energy range of scintillation pulses. When facing particle detection with a wide energy dynamic range, it can take into account the sampling and restoration accuracy of both small and large energy scintillation pulses. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solution of this application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of this application and should not be regarded as limiting the scope of protection of this application. In each of the drawings, similar components are numbered similarly.

[0040] Figure 1 A schematic diagram showing the structure of a threshold module setting of a scintillation pulse sampling device provided in an embodiment of the present application is shown;

[0041] Figure 2 A schematic structural diagram showing another threshold module setting of the scintillation pulse sampling device provided in an embodiment of the present application is shown;

[0042] Figure 3 A schematic diagram showing a flow chart of a scintillation pulse sampling method provided in an embodiment of the present application is shown;

[0043] Figure 4 A schematic diagram showing a differential comparator involved in the scintillation pulse sampling method provided in an embodiment of the present application is shown;

[0044] Figure 5 A schematic diagram showing a time interpolation method involved in the scintillation pulse sampling method provided in an embodiment of the present application is shown;

[0045] Figure 6A schematic diagram showing a delay chain involved in the scintillation pulse sampling method provided in an embodiment of the present application is shown;

[0046] Figure 7 The following is a logical timing diagram of the noise time acquisition involved in the scintillation pulse sampling method provided in an embodiment of the present application;

[0047] Figure 8 A schematic diagram of the process of acquiring the arrival time involved in the scintillation pulse sampling method provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0048] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0049] The components of the embodiments of the present application generally described and illustrated in the drawings herein may be arranged and designed in a variety of different configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed application, but rather merely represents selected embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative effort are within the scope of protection of the present application.

[0050] Hereinafter, the terms "including", "having" and their cognates, which may be used in various embodiments of the present application, are intended only to indicate specific features, numbers, steps, operations, elements, components or combinations of the foregoing items, and should not be understood as first excluding the existence of one or more other features, numbers, steps, operations, elements, components or combinations of the foregoing items or the possibility of adding one or more features, numbers, steps, operations, elements, components or combinations of the foregoing items.

[0051] Furthermore, the terms “first,” “second,” “third,” etc., are merely used for distinguishing descriptions and are not to be understood as indicating or implying relative importance.

[0052] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which the various embodiments of the present application belong. The terms (such as those defined in generally used dictionaries) will be interpreted as having the same meaning as in the context of the relevant technical field and will not be interpreted as having an idealized meaning or an overly formal meaning unless clearly defined in the various embodiments of the present application.

[0053] Example 1

[0054] An embodiment of the present application provides a flicker pulse sampling device, including a system module and a threshold voltage module; wherein the system module includes a main chip, and the main chip is provided with a chip select pin and a signal pin; the threshold voltage module includes multiple threshold modules, each threshold module is provided with a signal input terminal, a voltage input terminal, a signal output terminal, a chip select unit, a threshold comparator and multiple voltage units. In each threshold module, the voltage input terminal is connected to the main chip, the output terminal of the voltage unit and the signal input terminal are respectively connected to the input terminal of the threshold comparator, the chip select unit is connected to the chip select pin of the main chip, and the output terminal of the threshold comparator is connected to the signal pin of the main chip via the signal output terminal; the main chip configures the voltage threshold of each threshold module. For example, the main chip can configure the voltage threshold of each threshold module by using a DAC (digital-to-analog converter) or a resistor network voltage divider. The system module determines the number of target threshold modules that need to be started for detection based on the estimated voltage amplitude of the flicker pulse signal, and starts each target threshold module through a start instruction; the flicker pulse signal is input into each target threshold module in parallel, and the flicker pulse signal and the corresponding voltage threshold signal output by the voltage unit are respectively connected to the input end of the threshold comparator, and the comparison signal output by the threshold comparator is sent to the system module; the system module determines each voltage threshold and the corresponding detection time of the flicker pulse signal based on the comparison signal; the system module restores the waveform of the flicker pulse signal in a time sequence based on the integrated information of all detection time-voltage threshold pairs.

[0055] The scintillation pulse sampling device provided by the embodiment of the present application is used to implement the sampling and processing of scintillation pulse signals, and has the following beneficial effects: 1. The voltage threshold setting is simple. First, the amplitude range of the scintillation pulse signal to be sampled is determined to ensure that the voltage threshold setting range completely covers the amplitude range of the scintillation pulse signal to be sampled; secondly, the voltage threshold accuracy is determined, and the voltage threshold setting number is determined in combination with the number of FPGA differential pins and the overall power consumption. The voltage threshold setting scheme can be known, and the present application does not need to be re-determined due to changes in the scintillation pulse amplitude caused by technological iterations. 2. The applicable scintillation pulse energy range is large. The voltage threshold setting range of the present application completely covers the amplitude range of the scintillation pulse signal to be sampled. The difference between the scintillation pulse information of small energy and large energy is only the different number of voltage thresholds triggered, but as long as the valid voltage threshold number is met, it is considered to be a valid pulse. Therefore, when facing particle detection with a wide energy dynamic range, it can take into account the accuracy of sampling and restoration of scintillation pulses of small energy and large energy at the same time.

[0056] Specifically, the scintillation pulse sampling device includes a system module and a threshold voltage module. The system module, such as FPGA firmware, can serve as a main control component, and the chip circuits contained in the threshold voltage module serve as auxiliary components to provide multiple voltage thresholds selected by the system module.

[0057] The provided scintillation pulse sampling device can achieve fine sampling of different amplitudes. Therefore, the main factors to be considered in designing the scintillation pulse sampling device include threshold setting range, amplitude range adjustment, device selection and implementation, etc. These aspects will be explained in detail below.

[0058] The first aspect is the voltage threshold setting range. The voltage threshold setting range is determined according to the amplitude range of the scintillation pulse signal to be sampled. It is necessary to make the set voltage threshold setting range completely cover the amplitude range of the scintillation pulse signal. The amplitude of the pulse signal in different detection scenarios varies greatly. For example, in the particle detection scenario, the pulse signal fluctuates between 2 and 2.5V depending on the corresponding particle energy. In this case, the minimum voltage threshold can be set to 0V and the maximum voltage threshold can be set to greater than 2.5V to ensure that the set voltage threshold completely covers the pulse signal to be sampled.

[0059] Secondly, amplitude range adjustment. The amplitude of the pulse signal is typically between 0 and 5V to accommodate the signal processing circuitry of common low-voltage readout electronics. If it is not within this amplitude range, sensitivity adjustment can be used to bring it within this range. Methods for adjusting sensitivity include adjusting the supply voltage of front-end components such as photoelectric converters to adjust gain, and adjusting the resistance of back-end signal amplification circuits to adjust gain.

[0060] Third, device selection is based on range. After determining the amplitude range of the scintillation pulse signal to be sampled, the voltage unit and threshold comparator are selected based on this amplitude range. Considering the output voltage range of the voltage unit, such as the DAC, and the allowable input voltage range of the threshold comparator, they are selected to meet the amplitude requirements of the pulse signal. For example, the threshold comparator can be a differential comparator, and the input voltage range of the differential comparator is set.

[0061] Fourth, the number of voltage threshold settings. Theoretically, a greater number of voltage threshold settings allows for more precise pulse waveform characterization and better digitization. However, due to limitations such as voltage threshold setting accuracy, the number of differential pins on the FPGA chip, PCB layout area, and power consumption, an unlimited number of voltage threshold settings is not possible.

[0062] It is worth noting that there are accuracy issues in setting the voltage threshold, and the voltage noise may become larger as the voltage threshold becomes higher. Therefore, the interval between the set voltage thresholds must be greater than the peak-to-peak value of the voltage noise.

[0063] The number of differential pins on an FPGA chip is also limited. For a voltage threshold, the differential signal output of the pulse signal to be sampled and the voltage threshold after passing through the threshold comparator requires a pair of FPGA differential pins to process it. For example, setting 64 voltage thresholds requires the FPGA chip to have 64 pairs of differential pins. There are also limitations on PCB layout area and power consumption. In situations such as system integration, the size and power consumption of a single detector readout electronics are particularly important. The greater the number of voltage threshold settings, the greater the number of differential pins required on the FPGA chip, the larger the PCB layout area, and the more cumbersome the entire system. Therefore, it is necessary to comprehensively consider multiple factors to ultimately determine the number of voltage threshold settings.

[0064] Based on this, the scintillation pulse sampling device provided in this embodiment includes a main control system module and a threshold voltage module. The threshold voltage module includes multiple threshold modules, each of which is equipped with multiple voltage units. The main chip configures the voltage threshold of each threshold module. By combining the voltage thresholds of multiple voltage units and the voltage thresholds of the threshold modules, a pulse sampling solution with selectable multiple voltage thresholds is provided.

[0065] Specifically, each threshold module is provided with a signal input terminal, a voltage input terminal, a signal output terminal, a chip select unit, a threshold comparator, and multiple voltage units. Within each threshold module, the voltage input terminal is connected to the main chip, the output terminal of the voltage unit and the signal input terminal are respectively connected to the input terminal of the threshold comparator, the chip select unit is connected to the chip select pin of the main chip, and the output terminal of the threshold comparator is connected to the signal pin of the main chip via the signal output terminal. Optionally, the threshold comparator is a differential comparator.

[0066] According to a specific embodiment of the present application, the voltage unit includes a digital-to-analog converter (DAC) for setting different voltage thresholds.

[0067] According to another specific embodiment of the present application, the voltage unit includes a digital-to-analog converter and a voltage dividing resistor connected in series to the digital-to-analog converter.

[0068] Furthermore, the voltage divider resistors in each voltage unit in the threshold module are equivalent circuits.

[0069] Multiple voltage thresholds within the threshold module can be implemented using a digital-to-analog converter (DAC), a resistor network voltage divider, or a combination of the two. Using a DAC to directly assign voltage thresholds offers the advantage of flexible settings. The DAC output voltage threshold can be modified directly via serial communication, and the voltage threshold settings are stored in an E2PROM (also known as EEPROM, short for electrically erasable programmable read-only memory) and automatically read upon power-up. Furthermore, the DAC method also allows for more flexible calibration. Using a resistor network voltage divider offers the advantages of higher precision and lower cost. By utilizing the principle of resistor series voltage division, each voltage threshold can be derived from one end of a high-precision resistor.

[0070] Combining a DAC with a resistor network takes advantage of both. The voltage thresholds to be set are divided into several voltage intervals. The maximum value of each interval, i.e., the voltage threshold, is provided by the DAC, while the unit voltage threshold subdivision within the interval is achieved by the resistor network. For example, for a voltage threshold setting range of 0-3V, three DACs provide 1V, 2V, and 3V, respectively, while the voltage subdivisions between 0-1V, 1-2V, and 2-3V are achieved by the resistor network.

[0071] like Figure 1 As shown in FIG, a schematic diagram of the structure of a threshold module 100 of an 8-way voltage unit. The number of thresholds is not limited to 8, and can be 12, 16, 24, 32, etc. Figure 2 The figure shows another structure diagram with DAC and 16 thresholds. The number of pins of threshold modules with different threshold numbers will vary.

[0072] Figure 1 and Figure 2 In the DAC, the pin types are mainly divided into three categories, namely power pins, input pins and output pins. The power pins include VCC, VEE, and GND, which are used to power DAC102 and threshold comparator 101. The input pin Signal_in is used to input the flash pulse signal, SDA, SCL, V ref Indicates the driving and reference voltage pins under the DAC solution, V max / V min Indicates the maximum / minimum voltage under the resistor network solution, CS indicates the chip select pin, and the output pin V out1 、V out2 、V out3 、V out4 、V out5 、V out6 、V out7 、V out8 , used as the differential signal output after threshold comparison.

[0073] According to a specific embodiment of the present application, the chip select unit 103 includes an AND gate circuit 1031 and an inversion circuit 1032. The chip select unit 103 is connected to one input end of the AND gate circuit 1031 via the inversion circuit 1032, the signal input end is connected to the other input end of the AND gate circuit 1031, and the output end of the AND gate circuit 1031 is connected to the signal input end of each threshold comparator 101.

[0074] The chip select signal is used to select whether to connect to the module. It is high by default and low after being inverted. When ANDed with the flash pulse signal, the output clock is low and will not trigger the threshold comparator. When the threshold module is needed, the chip select signal is pulled low and the flash pulse signal is valid.

[0075] According to a specific embodiment of the present application, the main chip configures the voltage threshold of each threshold module through serial communication, and stores the voltage threshold setting in an erasable memory. The threshold module automatically reads the voltage threshold from the erasable memory each time it is powered on.

[0076] According to a specific implementation of the present application, the threshold module and the system module are connected in a plug-in manner; the main chip and each threshold module are connected in a plug-in manner.

[0077] In this embodiment, plug-in connections can be used to adapt to different application requirements. In existing technologies, such as high-speed ADC direct digitization methods, the high-speed ADC is a single unit, making plug-in connections inconvenient. However, the waveform digitization device provided in this application, due to its modular design, enables plug-in connections between the threshold module and the system module. The plug-in connection between the main chip and each threshold module facilitates flexible organization, updating, and adaptation to different application requirements and varying accuracy requirements based on actual needs.

[0078] According to a specific embodiment of the present application, the main chip configures the voltage threshold of each threshold module through serial communication, and stores the voltage threshold setting in an erasable memory. The threshold module automatically reads the voltage threshold from the erasable memory each time it is powered on.

[0079] In this embodiment, the threshold modules and system modules are pluggable to accommodate varying precision requirements. The system module can access all LVDS differential I / O ports as needed, allowing for the flexible combination of a specified number of threshold modules. The system module identifies the number of enabled threshold modules and adaptively adjusts the voltage threshold intervals corresponding to each threshold module to accommodate the corresponding number of thresholds. Multiple threshold modules can be freely combined based on precision requirements, maximizing FPGA resource utilization.

[0080] According to a specific embodiment of the present application, the number of the threshold modules is M, the number of voltage units in each threshold module is N, and the number of voltage thresholds of the system module is M×N, where M and N are both positive integers.

[0081] According to a specific embodiment of the present application, the voltage thresholds of adjacent threshold modules gradually increase and the spacing therebetween is equal, and the voltage thresholds of adjacent voltage units within the threshold module gradually increase and the spacing therebetween is equal.

[0082] Taking the total number of thresholds as 512 and the number of threshold setting module thresholds as 64 as an example, the FPGA part sets an 8-way DAC, that is, 8-way voltage thresholds, which are equally spaced. The threshold size can be freely modified. Assume that it is set to V 64 、V 128 、V 192 ,…,V 512 , connect 8 threshold modules, and the 64 thresholds in each threshold module are equally spaced. Take the first threshold module as an example, it is V0, V1, ..., V 63 , other threshold modules are similar in principle, and their DAC and resistor network schemes can be freely selected according to needs.

[0083] When the accuracy requirement is 512 thresholds, the 3.3V voltage is divided into 512 equal parts (9 bits), the chip select signals of the eight threshold modules are all pulled low, and each threshold is set in turn.

[0084] According to a specific embodiment of the present application, the system module is configured to identify the number of enabled threshold modules and adaptively change the size interval of the corresponding voltage threshold in each threshold module to adapt to the corresponding number of thresholds.

[0085] For example, the number of threshold modules to be enabled for identification can be determined based on the accuracy required. If the accuracy requirement is less stringent, such as 256 thresholds, the chip select signals of the first four threshold modules can be pulled low, and the thresholds can be read at intervals. Furthermore, if a traditional MVT solution is used, a threshold setting module with eight thresholds can be selected. By pulling low the chip select signal of only the first threshold module, the thresholds can be modified accordingly, allowing the solution to function as a traditional eight-threshold MVT solution.

[0086] The scintillation pulse sampling device provided can perform sampling and processing on the scintillation pulse signal, can adapt to the sampling requirements of the scintillation pulse signal, has great flexibility, determines the amplitude range of the scintillation pulse signal to be sampled, ensures that the voltage threshold setting range completely covers the amplitude range of the scintillation pulse signal to be sampled, determines the voltage threshold accuracy, and combines the overall power consumption to determine the number of voltage threshold settings. It is suitable for a large range of scintillation pulse energy. When facing particle detection with a wide energy dynamic range, it can take into account the sampling and restoration accuracy of both small and large energy scintillation pulses.

[0087] Example 2

[0088] See also Figure 3 , is a flow chart of a scintillation pulse sampling method provided in an embodiment of the present application, which is applied to the scintillation pulse sampling device provided in the above embodiment. Figure 3 As shown, the method mainly includes the following steps:

[0089] In step S301 , the main chip configures the voltage threshold of each threshold module through each voltage unit.

[0090] In this embodiment, the method of configuring the voltage threshold of each threshold module is the same as that in Embodiment 1, and is not described here in detail to avoid repetition.

[0091] In step S302 , the system module determines the number of target threshold modules that need to be activated for detection according to the estimated voltage amplitude of the scintillation pulse signal, and activates each target threshold module through an activation instruction.

[0092] The system module connects multiple threshold modules and first obtains the estimated voltage amplitude of the scintillation pulse signal to be sampled. Based on this estimated voltage amplitude, the system determines the number of threshold modules required, which are defined as target threshold modules. A start command is sent to the chip select unit of each target threshold module via the chip select pin to activate the target threshold module.

[0093] According to a specific embodiment of the present application, the system module determines the target threshold modules to be activated based on the estimated voltage amplitude of the scintillation pulse signal, and before the step of sending an activation instruction to the chip select unit of each target threshold module via the chip select pin, the method further includes:

[0094] Determining whether a voltage threshold of the system module covers an estimated voltage amplitude of the scintillation pulse signal;

[0095] If the voltage threshold of the system module covers the estimated voltage amplitude of the scintillation pulse signal, performing the step of determining a target threshold module to be activated according to the estimated voltage amplitude of the scintillation pulse signal;

[0096] If the voltage threshold of the system module does not cover the estimated voltage amplitude of the scintillation pulse signal, adjust the estimated voltage amplitude of the scintillation pulse signal so that the estimated voltage amplitude of the scintillation pulse signal after adjustment is within the coverage range of the voltage threshold of the system module.

[0097] For example, the sensitivity can be adjusted so that the estimated voltage amplitude of the blind pulse signal after adjustment is within the coverage range of the voltage threshold of the system module. It should be noted that the sensitivity adjustment method includes: adjusting the supply voltage of front-end devices such as photoelectric conversion to adjust the gain, adjusting the resistance value of the back-end signal amplification circuit to adjust the gain, etc., so that the estimated voltage amplitude of the blind pulse signal after adjustment is within the coverage range of the voltage threshold of the system module.

[0098] According to a specific embodiment of the present application, the step of the system module determining the target threshold module to be activated according to the estimated voltage amplitude of the scintillation pulse signal includes:

[0099] Determining the number of threshold modules according to the estimated voltage amplitude of the scintillation pulse signal, the detection voltage accuracy, and the number of voltage units in each threshold module;

[0100] A threshold module that meets the quantity requirement is selected from all threshold modules as a target threshold module.

[0101] According to a specific embodiment of the present application, after the step of starting each target threshold module through a start instruction, the method further includes:

[0102] Configure the voltage threshold of each target threshold module;

[0103] The voltage threshold of each target threshold module is split into voltage thresholds of corresponding voltage units.

[0104] According to a specific embodiment of the present application, the voltage threshold of each target threshold module is split into the voltage thresholds of the corresponding voltage units in the following manner:

[0105] The number of the threshold modules is M, the number of the voltage units is N, M and N are both positive integers, and the number accuracy of the voltage threshold required for detection is P=M×N;

[0106] The voltage threshold of the i-th target threshold module is recorded as V i×N , where 1≤i≤M;

[0107] Set the voltage threshold V of the i-th target threshold module i×N The voltage threshold of each voltage unit in the corresponding N voltage units is split.

[0108] For example, according to a specific embodiment of the present application, the number of threshold modules M is 8, and the number of voltage units in the threshold module is 64; if the voltage quantity accuracy required for detection is 512, the number of target threshold modules is 8, and the voltage thresholds of each target threshold module are V 64 、V 128 、V192 ,…,V 512 , where the voltage threshold is V 64 The unit voltage thresholds of each voltage unit in the target threshold module are V0, V1, ..., V 63 , the voltage threshold is V 512 The target threshold module has a cell voltage threshold of V 448 、V 449 ,…,V 511 ;

[0109] If the voltage number accuracy required for detection is 256, the number of target threshold modules is 4, and the voltage thresholds of each target threshold module are V 64 、V 128 、V 192 ,…,V 256 , where the voltage threshold is V 64 The unit voltage thresholds of each voltage unit in the target threshold module are V0, V1, ..., V 63 , the voltage threshold is V 256 The target threshold module has a cell voltage threshold of V 192 、V 193 ,…,V 255 .

[0110] According to a specific embodiment of the present application, the step of sending a startup instruction to the chip select unit of each target threshold module through the chip select pin includes:

[0111] Switch the chip select pin corresponding to each target threshold module to a low level;

[0112] The signal input terminals of each target threshold module are connected in parallel to the flicker pulse signal, and the input terminals of the threshold comparator are connected to the flicker pulse signal and the voltage threshold signal output by each voltage unit, respectively. The chip select pin is set to a high level by default. The chip select pin corresponding to each target threshold module is inverted and set to a low level. When ANDed with the flicker pulse signal, the output clock is low, and the threshold module will not be triggered. When the corresponding target threshold module needs to be triggered, the chip select signal of the corresponding target threshold module is pulled low, and the flicker pulse signal is valid.

[0113] In step S303, the flicker pulse signal is connected in parallel to the signal input ends of each target threshold module, the flicker pulse signal and the corresponding voltage threshold signal output by the voltage unit are connected to the input ends of the threshold comparator respectively, and the comparison signal output by the threshold comparator is sent to the system module.

[0114] Exemplarily, the target threshold module activated by the flicker pulse signal is input in parallel and connected to one input end of each threshold comparator, and the different voltage thresholds corresponding to each voltage unit are input to the other input end of the corresponding threshold comparator. Each threshold comparator generates a comparison signal based on the amplitude of the flicker pulse signal and the size of the corresponding voltage threshold, and outputs it to the system module.

[0115] According to a specific embodiment of the present application, the steps of respectively connecting the scintillation pulse signal and the corresponding voltage threshold signal output by the voltage unit to the input end of a threshold comparator, and sending the comparison signal output by the threshold comparator to the system module include:

[0116] The low-level chip selection signal connected to the chip selection unit is inverted by the inversion circuit of the chip selection unit and then input into the AND gate circuit of the chip selection unit;

[0117] The scintillation pulse signal is input into the AND gate circuit via the signal input terminal;

[0118] The output end of the AND gate circuit inputs the scintillation pulse signal into the signal input end of each threshold comparator.

[0119] The chip select unit includes an AND gate circuit and an inversion circuit, the chip select pin of the system module is preset to a high level, and the step of outputting a comparison signal to the system module includes:

[0120] The low-level chip selection signal input by the chip selection unit is inverted by the inversion circuit and then input into the AND gate circuit;

[0121] The scintillation pulse signal is input into the AND gate circuit via the signal input terminal;

[0122] The output end of the AND gate circuit inputs the flicker pulse signal into the signal input end of each threshold comparator. If the amplitude of the flicker pulse signal is greater than the voltage threshold received by the threshold comparator, the threshold comparator outputs a jump signal to the system module and records the time when the jump occurs through the system module; if the amplitude of the flicker pulse signal is less than the voltage threshold received by the threshold comparator, the threshold comparator does not jump.

[0123] The chip select pin defaults to high level, and after being inverted, it is low level. When ANDed with the flash pulse signal, the output clock is low level and will not trigger the comparator threshold. When the threshold module is needed, the chip select signal is pulled low and the flash pulse signal is valid.

[0124] In step S304 , the system module determines each voltage threshold value and corresponding detection time of the scintillation pulse signal according to the comparison signal.

[0125] According to a specific implementation of the present application, step S304 includes:

[0126] Determine a voltage threshold corresponding to a voltage unit connected to a threshold comparator corresponding to the comparison signal;

[0127] Obtaining a signal point time when the scintillation pulse signal corresponding to the comparison signal crosses the corresponding voltage threshold, and obtaining a noise point time when the scintillation pulse signal corresponding to the comparison signal first crosses a noise voltage threshold;

[0128] The voltage threshold corresponding to each comparison signal is associated with the signal time and the noise time.

[0129] In this embodiment, the noise time is determined by obtaining the first time point after the signal crosses the baseline and does not return to the baseline within a preset time.

[0130] In this embodiment, the signal location time and / or the noise location time are both achieved by TDC identifying different transition point moments in the comparison signal.

[0131] In this embodiment, the noise exposure time is acquired through a timing logic implemented by a threshold comparator and a TDC.

[0132] In step S305 , the system module restores the waveform of the scintillation pulse signal in a time sequence according to the integrated information of all detection time-voltage threshold pairs.

[0133] In this embodiment, waveform digitization processing is mainly performed by detecting the scintillation pulse signal through the voltage threshold, obtaining the time when the scintillation pulse signal triggers each voltage threshold, and then restoring the waveform based on the voltage value-time information.

[0134] The time information of the flicker pulse signal can be divided into two aspects: the method for obtaining the time at the signal level and the method for obtaining the time at the noise level. The method for obtaining the time at the signal level can be obtained using the existing MVT method, such as recording the flipping time of the high and low levels in the comparison signal output by the comparator through the TDC to obtain the time corresponding to when the rising edge or falling edge of the flicker pulse signal crosses different thresholds. However, when the threshold is set to be equivalent to the noise baseline, it is more difficult to obtain the time corresponding to the signal below the noise voltage threshold. The method for obtaining the time at the noise level provided in this embodiment is based on the FPGA to directly obtain the first time point after the pulse exceeds the baseline and does not return to the baseline in a short time, and use this time point as the start time of the pulse.

[0135] Those skilled in the art need to understand that "short time" in this application is a relative concept, which may vary according to the type, amplitude or detection accuracy requirements of the scintillation pulse signal. For example, for some signals with relatively regular waveforms, short time may refer to no more than 100ns or no more than 50ns. For some applications with higher detection accuracy requirements, short time may refer to no more than 20ns or no more than 10ns.

[0136] The above process mainly uses the threshold comparator and TDC. TDC is used to obtain time, and the threshold comparator is used to compare the signal (including the flicker pulse signal and the noise signal) with the voltage threshold. When the signal crosses the voltage threshold, a corresponding edge trigger signal is generated (such as the edge moment corresponding to the high and low level flip). The threshold comparator uses a differential comparator, for example Figure 4 The figure shows a threshold comparator implemented based on an LVDS input interface. In differential signal communication, high and low levels are identified by the relative magnitude of the voltages at the positive and negative input terminals of the differential interface. When the voltage at the positive input terminal is higher than that at the negative input terminal, the input signal is considered a logic '1'; when the voltage at the positive input terminal is lower than that at the negative input terminal, the input signal is considered a logic '0'. A flash pulse signal is connected to the positive input terminal, and a voltage threshold is connected to the negative input terminal. When the pulse signal voltage amplitude exceeds the threshold, the differential comparator identifies the input signal as a logic '1'; when the pulse signal voltage amplitude falls below the threshold, the differential comparator identifies the input signal as a logic '0'. The moment the analog pulse signal crosses the voltage threshold corresponds to the rising or falling edge transition of the logic signal identified by the LVDS receiver.

[0137] Use TDC to calculate the transition time, that is, the time to reach the threshold. The time obtained by TDC is realized by time interpolation using the internal resources of FPGA. Figure 5 The figure shows a schematic diagram of the time interpolation method. The measurement of the edge signal arrival time consists of two parts: coarse time measurement and fine time measurement. Coarse time measurement refers to a long-range, low-precision measurement of the signal occurrence time, which is usually achieved by using a counter to count the number of flips of the periodic clock signal. c The coarse time of the rising edge transition of the signal to be measured Hit under the interpolation TDC measurement method. The coarse time measurement can be completed by recording the number of clock signal flips when the signal to be measured jumps to a high level, that is, T c =n×T, where n is also called the coarse count; T is the cycle time of the clock signal. Fine time measurement refers to a high-precision measurement of the interval between the signal occurrence moment and the moment corresponding to the coarse time count, usually using a delay chain. f is the fine time measurement result, which is the time when the rising edge jump of the measured signal Hit occurs and Tc The time interval between moments. The time interpolation method is used to measure the pulse generation time, and the measurement result includes two parts, namely the rough time T in the figure. c and fine time T f The time of pulse occurrence is recorded as T c -T f .

[0138] like Figure 6 The figure shows a schematic diagram of a delay chain. The delay chain is composed of a plurality of delay units cascaded together, and the delay time of each delay unit is ΔT. The signal to be measured Hit is connected to the first-stage delay unit, which records the level state of the current Hit signal. After ΔT time, the signal state recorded by the first-stage delay unit will be transmitted to the second-stage delay unit and the current signal level state will be re-recorded; at the same time, the second-stage delay unit will pass its previously recorded level state to the next-stage delay unit and re-record the level state passed by the first-stage delay unit. The working method of subsequent delay units is similar. At time t, the level state recorded by the n-stage delay unit is the level state of the signal to be measured Hit before time n×ΔT. Therefore, the time interpolation method is used to measure the time of the rising edge jump of the signal to be measured Hit, and it is only necessary to measure the time at T f Fine-time measurement can be achieved by constantly recording the level state recorded by each delay unit in the delay chain and finding the first delay unit n with a low level state from the first to the last level. In this way, the signal processing time can be obtained.

[0139] The acquisition of the noise time is based on FPGA, using a threshold comparator and TDC to implement a timing logic, thereby obtaining effective time information of the noise. If the voltage threshold of the threshold comparator is set below the noise amplitude, when the voltage is greater than the set threshold, the level will flip. Figure 7 The following diagram shows a simple example. The top sequence represents the clock cycle, while the bottom sequence shows the level transitions at the threshold comparator output. When a pulse doesn't arrive, there's baseline noise, which constantly triggers the threshold comparator, resulting in a result between A and B. The level constantly transitions, but this time is not the actual pulse onset time, requiring additional timing judgment.

[0140] like Figure 8The figure shows the sequential logic process for acquiring time in the presence of noise, as provided by this embodiment. clk is the clock signal, signal is the level signal output by the threshold comparator, time is the continuously changing time information, cnt is the counter output signal, reg, reg_timeup, and reg_timedown are registers, and flag_up, flag_reg, and flag_down are flag signals. When there is no pulse input, signal continuously transitions, as in the previous section of the figure. The transition positions of multiple TDC signals within a clock cycle must be determined. If signal is high, cnt begins counting; if signal is low, cnt is cleared. When pulse level data is input, cnt continuously accumulates according to the clock signal until the pulse ends and returns to the state without pulse input. When cnt = 1, reg triggers and latches the current time information. When cnt reaches a certain count N, the flag_up signal goes high. When the flag_up signal is high, the reg data is assigned to reg_timeup, which is the actual time triggered by the rising edge.

[0141] The flag_reg signal pulls high when it detects the flag_up signal is high, and pulls low when it detects cnt is 1 again. Based on the flag_reg signal, the flag_down signal pulls high only when the flag_reg signal is high and cnt is 0. When the flag_down signal is high, the time data is assigned to reg_timeup, which is the actual time of the falling edge trigger. This way, the actual rising and falling edge trigger times of the pulse can be obtained.

[0142] This method requires knowing the approximate pulse width in advance and setting a value N to make a rough estimate. When the pulse width is large, the value of N will be very large. Due to the limited number of digits in cnt, certain settings are necessary. When cnt reaches the maximum number of digits, the next step is to assign cnt a value of N+1 and continue counting until the maximum value is reached.

[0143] Furthermore, with a 64 threshold (TH_ALL), a reference voltage of 3.3V (V ref For example, with a noise amplitude of 80mV, the thresholds are evenly distributed from 0 to 3.3V, with an interval of 3.3V / (64–1)=52.4mV. The two lowest thresholds (TH_Trigger, 0mv and 52.4mv) are acquired using the noise-based time acquisition method, while the other thresholds are acquired using the signal-based time acquisition method. This allows for obtaining trigger point timing information at any threshold. Parameters can also be quickly adjusted and modified.

[0144] After acquiring data pairs consisting of voltage thresholds and detection times, the system module restores and displays the waveform, achieving waveform digitization. Specific waveform restoration methods include: 1. Scatter plot; 2. Line graph; 3. Curve smoothing; 4. Equal time interval interpolation (V-T transformation).

[0145] In this embodiment, methods for restoring the waveform of the scintillation pulse signal include a scatter plot, a broken line graph, curve smoothing, and an equal time interval interpolation method.

[0146] Exemplarily, step S305 includes:

[0147] determining waveform characteristic parameters of the scintillation pulse signal according to the comparison signal, and selecting a matching target fitting model according to the waveform characteristic parameters;

[0148] The target fitting model is used to fit all detection time-voltage threshold pair information to obtain the waveform of the scintillation pulse signal.

[0149] In this embodiment, the waveform characteristic parameters may be: the characteristics of the time point of the trigger voltage threshold (rising edge, falling edge, overall). The pulse shape can be determined by the waveform characteristic parameters, and the fitting model can be adaptively selected, which can be used in the pulse identification process.

[0150] Furthermore, determining the waveform characteristic parameters of the scintillation pulse signal according to the comparison signal includes:

[0151] Determining a voltage threshold and a trigger time corresponding to each of the comparison signals;

[0152] Summarizing the voltage thresholds of all comparison signals to determine the actual voltage range of the scintillation pulse signal;

[0153] Integrate the voltage thresholds corresponding to each trigger time to obtain the voltage sequence corresponding to the time series;

[0154] The waveform characteristic parameters of the pulse signal are obtained according to the voltage sequence corresponding to the time series.

[0155] In this way, relatively accurate waveform characteristic parameters can be obtained.

[0156] In this embodiment, the method further includes:

[0157] The system module determines any two adjacent trigger times among all trigger times corresponding to the highest voltage threshold;

[0158] The peak interval of the scintillation pulse signal is determined according to any two adjacent trigger times.

[0159] In this way, the scintillation pulse peak interval can be determined based on the two time points of the highest trigger voltage threshold.

[0160] In addition, according to a specific embodiment of the present application, after the step of determining the number of threshold modules based on the estimated voltage amplitude of the scintillation pulse signal, the detection voltage accuracy, and the number of voltage units in each threshold module, the method further includes:

[0161] Obtaining predefined global variables, wherein the global variables include a total threshold number, an effective threshold number, and a noise threshold number, wherein the total threshold number is the sum of the effective threshold number and the noise threshold number;

[0162] Calculate the actual number of thresholds included in the target threshold module according to the number of threshold modules;

[0163] If the actual threshold value is greater than the effective threshold value, the scintillation pulse signal is determined to be a effective signal.

[0164] Three global variables are defined in the hardware description language (Verilog). The first describes the total number of thresholds, TH_ALL, which is the number of voltage thresholds set within the voltage threshold range. The second describes the number of valid thresholds, TH_MVT. A signal is considered valid only when the signal to be sampled triggers more than this threshold, thus filtering out low-amplitude signals outside the energy window. The third describes the noise voltage threshold, TH_Trigger. A signal is considered valid only when a voltage threshold above this threshold is triggered, rather than being a noise signal or a signal buried in noise. Global variables can be flexibly set and quickly modified, enabling adaptive adjustments to meet the needs of different application scenarios.

[0165] TH_ALL=TH_MVT+TH_Trigger; Generally, the noise threshold does not need to be modified, so only TH_ALL needs to be modified.

[0166] After obtaining the waveform's horizontal axis time information according to the above steps, the coordinate point information also needs to be obtained. When multiple threshold modules are freely combined, each threshold processing channel is a separate processing channel, and the thresholds are parallel to each other. Each threshold has a flag signal, which can be regarded as synchronous processing of the comparator output signal. When a rising edge of a pulse is recognized, it is pulled high. When a falling edge is recognized, it is delayed by one clock cycle to write the data to the cache, and then pulled low. This operation is repeated when a rising edge is recognized again.

[0167] In the case where there is a baseline in the flicker pulse signal, the pulse signal segment from the pulse arrival time to the pulse end time, or the pulse signal segment within the period when the minimum noise threshold is triggered by the falling edge of the pulse is considered a group of pulses. After a group of pulses is identified, the pulse information is packaged and sent to the PC, or for needs such as area calculation and time calculation.

[0168] Furthermore, the step of obtaining the noise threshold time when the scintillation pulse signal corresponding to the comparison signal first crosses the noise threshold includes:

[0169] If the scintillation pulse signal is a single-peak pulse signal, obtain the trigger time of the trigger point before / after the rising edge and the trigger time of the trigger point before / after the falling edge as the noise time, and set the other times to zero;

[0170] If the scintillation pulse signal is a multi-peak pulse signal, the triggering time of all triggering points is obtained and the threshold number of each triggering point is marked.

[0171] This implementation provides five methods for outputting time information, which can be selected through FPGA firmware implementation: 1. Outputting the rising edge first, the falling edge first; 2. Outputting the rising edge first, the falling edge last; 3. Outputting the rising edge last, the falling edge first; 4. Outputting the rising edge last, the falling edge last; and 5. Outputting all points. Methods 1 through 4 are suitable for single-peak pulse signals, while method 5 is suitable for multi-peak pulse signals.

[0172] For the front and back point output methods of single-peak pulse signals, the coordinate point obtained by "taking the front" is the first value triggered. For rising edges, the time information is immediately latched when the flag signal goes high. Similarly, for falling edges, the time information is immediately latched when the flag signal goes low. The coordinate point obtained by "taking the back" is the last value triggered. For rising edges, the time information is not latched after the flag signal goes high and continues to change based on the pulse triggering situation. Similarly, for falling edges, the time information is not latched when the flag signal goes low. When the pulse end is detected (the pulse end time or the minimum over-noise threshold is triggered by the falling edge of the pulse), the time information of the threshold is output.

[0173] For the full-point output mode of multi-peak pulse signals, the present invention will add a "threshold number" as a frame header in each threshold output information, and write the time information into the cache whenever the falling edge of the flag signal is identified. Similarly, when the end of the pulse is identified (the pulse end time or the minimum threshold over-noise threshold is triggered by the falling edge of the pulse), the time information of the threshold is output. This method will have a dead time of 1 clock cycle, but considering comprehensively, it has no effect on the reproduction of the waveform. Those skilled in the art should note that the dead time is for a single threshold, and there is no dead time between thresholds. Assuming a 200M system clock, the dead time is 5ns. If a single threshold fluctuation occurs within 5ns, it can be approximately regarded as the superposition of noise signals, and there is no visible effect on the final waveform recovery.

[0174] In specific implementations, if methods 1-4 are selected, the time information corresponding to the untriggered threshold will be assigned a value of zero. For method 5, this issue does not need to be considered because the output information includes the threshold number. Regardless of the above methods, the length of the output information can be calculated, so the size of the data packet can be expressed as a parameter to achieve an adaptive output coordinate sequence.

[0175] The provided scintillation pulse sampling method can perform sampling and processing on scintillation pulse signals, can adapt to the sampling requirements of scintillation pulse signals, has great flexibility, determines the amplitude range of the scintillation pulse signal to be sampled, ensures that the voltage threshold setting range completely covers the amplitude range of the scintillation pulse signal to be sampled, determines the voltage threshold accuracy, and combines the overall power consumption to determine the number of voltage threshold settings. It is suitable for a large energy range of scintillation pulses. When facing particle detection with a wide energy dynamic range, it can take into account the sampling and restoration accuracy of both small and large energy scintillation pulses.

[0176] The embodiments of the present application also relate to electronic devices capable of implementing the methods of the embodiments of the present application.

[0177] In some embodiments, an electronic device is provided, which may include a processor and a memory storing a computer program, wherein the processor is configured to execute the scintillation pulse sampling method of any embodiment of the present application when running the computer program.

[0178] In some embodiments, the waveform digitization method described herein can be implemented using a single or multiple electronic devices. In some embodiments, the method can be implemented using cloud-based or distributed electronic devices.

[0179] In some embodiments, the electronic device includes a processor that can perform various appropriate operations and processes based on programs and / or data stored in a read-only memory (ROM) or programs and / or data loaded from a storage portion into a random access memory (RAM). The processor can be a single-core or multi-core processor, or it can include multiple processors. In some embodiments, the processor can include a general-purpose main processor (such as a CPU) and one or more special coprocessors, such as a graphics processing unit (GPU), a neural network processor (NPU), a digital signal processor (DSP), or other general or application-specific integrated circuits. Various programs and data required for the operation of the electronic device are also stored in the RAM. The processor, ROM, and RAM are connected to each other via a bus.

[0180] The processor and the memory are used together to execute the program stored in the memory. When the program is executed by the computer, the steps or functions of the methods described in the above embodiments can be implemented.

[0181] In some embodiments, the electronic device may be combined with various components to obtain methods, devices, and systems having the advantages of the present invention.

[0182] Although not shown, in some embodiments, a computer-readable storage medium is further provided, storing a computer program configured to execute any of the methods of the embodiments of the present application when executed. The computer program includes various program modules / units that constitute the apparatus according to the embodiments of the present application. When the computer program composed of the various program modules / units is executed, it can implement the functions corresponding to the various steps in the methods described in the above embodiments. The computer program can also be executed on the electronic device described in the embodiments of the present application.

[0183] In the embodiments of the present application, the cache is a storage medium, including non-volatile and / or volatile items that can be used to store information by any method or technology. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0184] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of this application, ordinary technicians in this field can also make many forms without departing from the purpose of this application and the scope of protection of the claims, all of which are within the protection of this application.

Claims

1. A scintillation pulse sampling device, characterized in that: It includes a system module and a threshold voltage module, wherein the system module includes a main chip, and the main chip is provided with a chip selection pin and a signal pin; The threshold voltage module includes a plurality of threshold modules, each of which is provided with a signal input terminal, a voltage input terminal, a signal output terminal, a chip selection unit, a threshold comparator and a plurality of voltage units. In each threshold module, the voltage input terminal is connected to the main chip, the output terminal of the voltage unit and the signal input terminal are respectively connected to the input terminal of the threshold comparator, the chip selection unit is connected to the chip selection pin of the main chip, and the output terminal of the threshold comparator is connected to the signal pin of the main chip via the signal output terminal; The main chip configures the voltage threshold of each threshold module through each voltage unit; The system module determines the number of target threshold modules that need to be activated for detection according to the estimated voltage amplitude of the scintillation pulse signal, and activates each target threshold module through a startup instruction; Input the flicker pulse signal to each target threshold module in parallel, connect the flicker pulse signal and the corresponding voltage threshold signal output by the voltage unit to the input end of the threshold comparator respectively, and send the comparison signal output by the threshold comparator to the system module; The system module determines each voltage threshold and corresponding detection time of the scintillation pulse signal according to the comparison signal; The system module restores the waveform of the scintillation pulse signal in a time sequence according to the integrated information of all detection time-voltage threshold pairs.

2. The scintillation pulse sampling device according to claim 1, characterized in that: The voltage unit includes a digital-to-analog converter.

3. The scintillation pulse sampling device according to claim 1, characterized in that: The voltage unit includes a digital-to-analog converter and a voltage dividing resistor connected in series to the digital-to-analog converter.

4. The scintillation pulse sampling device according to claim 3, characterized in that: The voltage-dividing resistors in each voltage unit in the threshold module are equivalent circuits.

5. The scintillation pulse sampling device according to claim 1, characterized in that: The threshold comparator is a differential comparator.

6. The scintillation pulse sampling device according to any one of claims 1 to 5, characterized in that: The chip select unit includes an AND gate circuit and an inversion circuit. The chip select unit is connected to one input end of the AND gate circuit via the inversion circuit, the signal input end is connected to the other input end of the AND gate circuit, and the output end of the AND gate circuit is connected to the signal input end of each threshold comparator.

7. The scintillation pulse sampling device according to claim 1, characterized in that: The main chip configures the voltage threshold of each threshold module through serial communication, and stores the voltage threshold setting in an erasable memory. The threshold module automatically reads the voltage threshold from the erasable memory each time it is powered on.

8. The scintillation pulse sampling device according to claim 1, characterized in that: The threshold module is connected to the system module in a plug-in manner; the main chip is connected to each threshold module in a plug-in manner.

9. The scintillation pulse sampling device according to claim 1, characterized in that: The number of the threshold modules is M, the number of voltage units in each threshold module is N, and the number of voltage thresholds of the system module is M×N, wherein M≥2 and N is a positive integer.

10. The scintillation pulse sampling device according to claim 9, characterized in that: The voltage thresholds corresponding to adjacent threshold modules gradually increase and the intervals are equal, and the voltage thresholds corresponding to adjacent voltage units in the same threshold module gradually increase and the intervals are equal.

11. The scintillation pulse sampling device according to claim 1, characterized in that: The system module is configured to identify the number of threshold modules that are enabled, and adaptively change the size interval of the corresponding voltage threshold in each threshold module to adapt to the corresponding number of thresholds.

12. A scintillation pulse sampling method, characterized in that: The scintillation pulse sampling method comprises: The main chip configures the voltage threshold of each threshold module through each voltage unit; The system module determines the number of target threshold modules that need to be activated for detection according to the estimated voltage amplitude of the flicker pulse signal, and activates each target threshold module through a startup instruction; Input the flicker pulse signal to each target threshold module in parallel, connect the flicker pulse signal and the corresponding voltage threshold signal output by the voltage unit to the input end of the threshold comparator respectively, and send the comparison signal output by the threshold comparator to the system module; The system module determines each voltage threshold and corresponding detection time of the scintillation pulse signal according to the comparison signal; The system module restores the waveform of the scintillation pulse signal in a time sequence according to the integrated information of all detection time-voltage threshold pairs.

13. The scintillation pulse sampling method according to claim 12, characterized in that: Before the step of the system module determining the number of target threshold modules to be started according to the estimated voltage amplitude of the scintillation pulse signal and starting each target threshold module through a start instruction, the scintillation pulse sampling method further includes: Determining whether the voltage threshold of the system module covers the estimated voltage amplitude of the flicker pulse signal; If the voltage threshold of the system module covers the estimated voltage amplitude of the flicker pulse signal, executing the step of determining the number of target threshold modules that need to be activated according to the estimated voltage amplitude of the flicker pulse signal; If the voltage threshold of the system module does not cover the estimated voltage amplitude of the flicker pulse signal, adjust the estimated voltage amplitude of the flicker pulse signal so that the estimated voltage amplitude of the flicker pulse signal after adjustment is within the coverage range of the voltage threshold of the system module.

14. The scintillation pulse sampling method according to claim 12, characterized in that: The step of the system module determining the number of target threshold modules that need to be activated according to the estimated voltage amplitude of the flicker pulse signal includes: Determine the number of target threshold modules that need to be activated according to the estimated voltage amplitude of the scintillation pulse signal, the detection voltage accuracy and the number of voltage units in each threshold module; A threshold module that meets the quantity requirement is selected from all threshold modules as a target threshold module.

15. The scintillation pulse sampling method according to claim 16, characterized in that: After the step of starting each target threshold module by a start instruction, the scintillation pulse sampling method further includes: Configure the voltage threshold of each target threshold module; The voltage threshold of each target threshold module is split into voltage thresholds of corresponding voltage units.

16. The scintillation pulse sampling method according to claim 15, characterized in that: The voltage threshold of each target threshold module is split into the voltage thresholds of the corresponding voltage units in the following manner: The number of the threshold modules is M, the number of the voltage units is N, M and N are both positive integers, and the number accuracy of the voltage threshold required for detection is P=M×N; The voltage threshold of the i-th target threshold module is recorded as V i×N , where 1≤i≤M; Set the voltage threshold V of the i-th target threshold module i×N The voltage threshold of each voltage unit in the corresponding N voltage units is split.

17. The scintillation pulse sampling method according to claim 12, characterized in that: The step of starting each target threshold module through a start instruction includes: Switch the chip select pin corresponding to each target threshold module to a low level; The signal input end of each target threshold module is connected to the flicker pulse signal in parallel, and the input end of the threshold comparator is respectively connected to the flicker pulse signal and the voltage threshold signal output by each voltage unit. The chip select pin is high level by default, and the chip select pin corresponding to each target threshold module is low level after inversion, and is ANDed with the flicker pulse signal. The output clock is low level and will not trigger the corresponding target threshold module; when the corresponding target threshold module needs to be triggered, the chip select signal of the corresponding target threshold module is pulled low, and the flicker pulse signal is valid.

18. The scintillation pulse sampling method according to claim 12, characterized in that: The steps of respectively connecting the flicker pulse signal and the corresponding voltage threshold signal output by the voltage unit to the input end of the threshold comparator, and sending the comparison signal output by the threshold comparator to the system module include: The low-level chip selection signal connected to the chip selection unit is inverted by the inversion circuit of the chip selection unit and then input into the AND gate circuit of the chip selection unit; The scintillation pulse signal is input into the AND gate circuit via the signal input terminal; The output end of the AND gate circuit inputs the flicker pulse signal into the signal input end of each threshold comparator.

19. The scintillation pulse sampling method according to claim 14, characterized in that: After the step of determining the number of target threshold modules to be started according to the estimated voltage amplitude of the scintillation pulse signal, the detection voltage accuracy and the number of voltage units in each threshold module, the scintillation pulse sampling method further includes: Acquire predefined global variables, wherein the global variables include a total threshold number, an effective threshold number, and a noise threshold number, wherein the total threshold number is the sum of the effective threshold number and the noise threshold number; Calculate the actual number of thresholds included in the target threshold module according to the number of threshold modules; If the actual threshold value is greater than the effective threshold value, the flicker pulse signal is determined to be a effective signal.

20. The scintillation pulse sampling method according to claim 12, characterized in that: Methods for restoring the waveform of the scintillation pulse signal include scatter plot, line graph, curve smoothing and equal time interval interpolation.

21. The scintillation pulse sampling method according to claim 12, characterized in that: The system module restores the waveform of the scintillation pulse signal in a time sequence according to the integrated information of all detection time-voltage threshold pairs, including: Determining waveform characteristic parameters of the scintillation pulse signal according to the comparison signal, and selecting a matching target fitting model according to the waveform characteristic parameters; The target fitting model is used to fit all detection time-voltage threshold pair information to obtain the waveform of the scintillation pulse signal.

22. The scintillation pulse sampling method according to claim 21, characterized in that: The step of determining the waveform characteristic parameters of the scintillation pulse signal according to the comparison signal comprises: Determine the voltage threshold and trigger time corresponding to each of the comparison signals; Summarizing the voltage thresholds of all comparison signals to determine the actual voltage range of the scintillation pulse signal; Integrate the voltage thresholds corresponding to each trigger time to obtain the voltage sequence corresponding to the time series; The waveform characteristic parameters of the pulse signal are obtained according to the voltage sequence corresponding to the time series.

23. The scintillation pulse sampling method according to claim 21, characterized in that: The scintillation pulse sampling method also includes: The system module determines any two adjacent trigger times among all trigger times corresponding to the highest voltage threshold; The peak interval of the scintillation pulse signal is determined according to any two adjacent trigger times.

24. The scintillation pulse sampling method according to claim 12, characterized in that: The step of the system module determining each voltage threshold and the corresponding detection time of the scintillation pulse signal according to the comparison signal comprises: Determine a voltage threshold corresponding to a voltage unit connected to a threshold comparator corresponding to the comparison signal; Acquire the signal point time when the scintillation pulse signal corresponding to the comparison signal crosses the corresponding voltage threshold, and acquire the noise point time when the scintillation pulse signal corresponding to the comparison signal crosses the noise voltage threshold for the first time; The voltage threshold corresponding to each comparison signal is associated with the signal time and the noise time.

25. The scintillation pulse sampling method according to claim 24, characterized in that: The noise time is determined by obtaining the first time point after the signal crosses the baseline and does not return to the baseline within a preset time.

26. The scintillation pulse sampling method according to claim 24, characterized in that: The signal time and / or the noise time are both achieved by TDC identifying different jump point moments in the comparison signal.

27. The scintillation pulse sampling method according to claim 24, characterized in that: The noise time is obtained through a threshold comparator and a timing logic implemented by a TDC.

28. The scintillation pulse sampling method according to claim 24, characterized in that: The step of obtaining the noise time when the scintillation pulse signal corresponding to the comparison signal first crosses the corresponding voltage threshold comprises: If the scintillation pulse signal is a single-peak pulse signal, the trigger time of the front / rear trigger point of the rising edge and the trigger time of the front / rear trigger point of the falling edge are obtained as the noise time, and the other times are set to zero; If the scintillation pulse signal is a multi-peak pulse signal, the triggering time of all triggering points is obtained and the threshold number of each triggering point is marked.

29. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and the computer program is configured to perform the scintillation pulse sampling method according to any one of claims 12 to 28 when executed.

30. An electronic device, characterized in that: include: A processor and a memory storing a computer program, wherein the processor is configured to execute the scintillation pulse sampling method according to any one of claims 12 to 28 when running the computer program.

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