Scintillation pulse signal time detection device and method, electronic device and medium

Abstract

The embodiment of the invention provides a time detection device and method for a scintillation pulse signal, an electronic device and a medium, a system module determines the number of target threshold modules needing to be started for detection according to the estimated voltage amplitude of the scintillation pulse signal, and starts each target threshold module through a starting instruction; the flicker pulse signals are input into the target threshold modules in parallel, the flicker pulse signals and corresponding voltage threshold signals output by the voltage unit are connected to the input end of the threshold comparator, and comparison signals output by the threshold comparator are sent to the system module; and the system module determines each voltage threshold of the scintillation pulse signal and the corresponding detection time according to the comparison signal. According to the method, time detection can be carried out on the scintillation pulse signal, the real zero-crossing point of the scintillation pulse is obtained in a full-digital mode, the threshold comparator is used, meanwhile, the influence of baseline noise caused by too low threshold setting is avoided, and the obtained pulse detection time is more accurate.

Description

Technical Field

[0001] The present application relates to the field of ionizing radiation detection, and in particular to a time detection device, method, electronic device and medium for a scintillation pulse signal. Background Art

[0002] Scintillation detectors can detect the fluorescence generated by the interaction between high-energy particles such as Gamma and X and scintillation crystals to obtain the time, size and position of energy deposition of particles in the scintillator. Figure 1 After the high-energy particles react with the scintillating crystals, fluorescence is generated. After the fluorescence is transmitted in the scintillating crystals, it is received by the photoelectric converter and converted into electrons. After being converted into photons, it will be amplified by the photoelectric device and finally converted into an electrical scintillation pulse signal. This electrical pulse is called a scintillation pulse. Its formation time, amplitude, position and other information correspond to the time, size and position of the energy deposition of the particles in the scintillator. Therefore, by obtaining the formation time, amplitude and position of the scintillation pulse, the corresponding information of the particles in the scintillator can be obtained.

[0003] At time T0, the incident particle deposits energy with the scintillator in the scintillation detector and generates visible light photons. These visible light photons are converted into photoelectrons at the photocathode and amplified through multiplication to reach the anode of the photomultiplier tube (PMT) to form a scintillation pulse. There is a delay of ΔT between the formation time of the scintillation pulse and the time when the visible light photon reaches the photodetection surface. This time is called the transit time. For the same PMT, ΔT is relatively fixed. Therefore, in order to obtain the energy deposition time of the particle in the scintillation crystal, it is necessary to obtain the precise pulse formation time. The pulse formation time requires the start time of the pulse, so the accuracy of the pulse start time will determine the accuracy of the pulse formation time. There are three main existing methods for obtaining the pulse start time: edge discrimination, constant ratio discrimination, and MVT fitting.

[0004] The first is edge discrimination (Leading-Edge Discriminator, hereinafter referred to as LED). This method is to use the time when the rising edge of the flashing pulse crosses a preset voltage threshold as the start time of the pulse. The second method is the constant fraction discriminator (hereinafter referred to as CFD). The input flashing pulse is divided into two paths. One pulse is delayed according to a fixed time constant (Delayed pulse), and the other pulse is attenuated according to a fixed attenuation ratio (Attenuated pulse). The two pulses are then subtracted. The time T when the voltage of the subtracted signal crosses the baseline voltage is recorded as the start time of the pulse. The third method is the multi-voltage threshold sampling method (Multi-VoltageThreshold, hereinafter referred to as MVT) to calculate the start time after fitting, obtain the voltage time point through the MVT method, and then fit the pulse. The pulse start time is obtained by calculating the 0 point through the fitted curve.

[0005] The disadvantage of edge discrimination is that for pulses with relatively slow rising edges and relatively large amplitude variation ranges, a time walk effect will occur, which will ultimately affect the accuracy of time information extraction. Figure 2 and Figure 3 , Pulse A and Pulse B are two scintillation pulses with different amplitudes generated at the same time. Figure 2 As shown in the figure, under the LED method, the measured times are T1 and T2 respectively. ΔT = T1-T2 is the measurement error caused by the time walk effect. The measurement error caused by the time walk effect can be reduced by setting a lower threshold. However, there is a certain amount of noise in the actual circuit, and a too low threshold will be falsely triggered by the noise and also affect the time extraction accuracy. See Figure 3 The disadvantage of the constant ratio discrimination method is that if the models of the two pulses are inconsistent, the difference between the calculated start times of the two pulses will have a significant error. Therefore, if it is used in a scenario such as PET that requires time coincidence calculation, the calculation of coincidence time will have errors. The disadvantage of the MTV fitting method is that the fitting result will be seriously affected by the amplitude time point used for fitting, which will lead to deviations in the calculation of the start time. Summary of the invention

[0006] In order to solve at least one of the above technical problems, the embodiments of the present application provide a time detection device, method, electronic device and medium for a scintillation pulse signal.

[0007] In the first aspect, an embodiment of the present application provides a time detection device for a flicker pulse signal, comprising a system module and a threshold voltage module; wherein the system module comprises a main chip, and the main chip is provided with a chip select pin and a signal pin; the threshold voltage module comprises a plurality of threshold modules, each threshold module is provided with a signal input terminal, a voltage input terminal, a signal output terminal, a chip select unit, a threshold comparator and a plurality of voltage units, in each threshold module, the voltage input terminal is connected to the main chip, the output terminal of the voltage unit and the signal input terminal are respectively connected to the input terminal of the threshold comparator, the chip select unit is connected to the chip select pin of the main chip, and the output terminal of the threshold comparator is connected via The signal output end is connected to the signal pin of the main chip; the main chip configures the voltage threshold of each threshold module through each voltage unit; the system module determines the number of target threshold modules that need to be started for detection according to the estimated voltage amplitude of the flicker pulse signal, and starts each target threshold module through a start instruction; the flicker pulse signal is input into each target threshold module in parallel, and the flicker pulse signal and the corresponding voltage threshold signal output by the voltage unit are respectively connected to the input end of the threshold comparator, and the comparison signal output by the threshold comparator is sent to the system module; the system module determines each voltage threshold and the corresponding detection time of the flicker pulse signal according to the comparison signal.

[0008] According to a specific implementation of the present application, the voltage unit includes a digital-to-analog converter.

[0009] According to a specific implementation of the present application, the voltage unit includes a digital-to-analog converter and a voltage-dividing resistor connected in series to the digital-to-analog converter.

[0010] According to a specific implementation of the present application, the voltage-dividing resistors in each voltage unit in the threshold module are equivalent circuits.

[0011] According to a specific implementation of the present application, the threshold comparator is a differential comparator.

[0012] According to a specific embodiment of the present application, the chip select unit includes an AND gate circuit and an inversion circuit. The chip select unit is connected to an input end of the AND gate circuit via the inversion circuit, the signal input end is connected to another input end of the AND gate circuit, and the output end of the AND gate circuit is connected to the signal input end of each threshold comparator.

[0013] According to a specific implementation of the present application, the main chip configures the voltage threshold of each threshold module through serial communication, and stores the voltage threshold setting in an erasable memory, and the threshold module automatically reads the voltage threshold from the erasable memory each time the power is turned on.

[0014] According to a specific implementation of the present application, the threshold module is connected to the system module in a plug-in manner; and the main chip is connected to each threshold module in a plug-in manner.

[0015] According to a specific implementation of the present application, the number of the threshold modules is M, the number of voltage units in each threshold module is N, and the number of voltage thresholds of the system module is M×N, where M≥2 and N is a positive integer.

[0016] According to a specific implementation of the present application, voltage thresholds corresponding to adjacent threshold modules gradually increase and are spaced at equal intervals, and voltage thresholds corresponding to adjacent voltage units in the same threshold module gradually increase and are spaced at equal intervals.

[0017] According to a specific implementation of the present application, the system module is configured to identify the number of threshold modules that are enabled, and adaptively change the size interval of the corresponding voltage threshold in each threshold module to adapt to the corresponding number of thresholds.

[0018] In the second aspect, an embodiment of the present application provides a time detection method for a flicker pulse signal, which is applied to the time detection device for a flicker pulse signal provided in the first aspect, and the method includes: the system module determines the number of target threshold modules that need to be started for detection according to the estimated voltage amplitude of the flicker pulse signal, and starts each target threshold module through a start instruction; the flicker pulse signal is input into each target threshold module in parallel, and the flicker pulse signal and the corresponding voltage threshold signal output by the voltage unit are respectively connected to the input end of the threshold comparator, and the comparison signal output by the threshold comparator is sent to the system module; the system module determines each voltage threshold and the corresponding detection time of the flicker pulse signal according to the comparison signal.

[0019] According to a specific embodiment of the present application, after the step of starting each target threshold module through a start-up instruction, the time detection method of the flashing pulse signal also includes: configuring the voltage threshold of each target threshold module; splitting the voltage threshold of each target threshold module into the voltage threshold of the corresponding voltage unit.

[0020] According to a specific implementation of the present application, the voltage threshold of each target threshold module is split into the voltage threshold of the corresponding voltage unit in the following manner: the number of the target threshold modules is M, the number of the voltage units is N, M and N are both positive integers, and the number accuracy of the voltage threshold required for detection is P = M × N; the voltage threshold of the i-th target threshold module is sequentially recorded as V i×N , where 1≤i≤M; the voltage threshold V of the i-th target threshold module i×N The voltage threshold of each voltage unit in the corresponding N voltage units is split.

[0021] According to a specific implementation manner of the present application, the step of starting each target threshold module through a start instruction includes: switching the chip select pin corresponding to each target threshold module to a low level; the signal input end of each target threshold module is connected to the flickering pulse signal in parallel, and the input end of the threshold comparator is respectively connected to the flickering pulse signal and the voltage threshold signal output by each voltage unit, the chip select pin is high level by default, and the chip select pin corresponding to each target threshold module is low level after being inverted, and is ANDed with the flickering pulse signal, and the output clock is low level, and the corresponding target threshold module will not be triggered; when the corresponding target threshold module needs to be triggered, the chip select signal of the corresponding target threshold module is pulled low, and the flickering pulse signal is valid.

[0022] According to a specific embodiment of the present application, the flicker pulse signal and the corresponding voltage threshold signal output by the voltage unit are respectively connected to the input end of the threshold comparator, and the comparison signal output by the threshold comparator is sent to the system module, including: the low-level chip select signal connected to the chip select unit is inverted by the inversion circuit of the chip select unit and then input into the AND gate circuit of the chip select unit; the flicker pulse signal is input into the AND gate circuit via the signal input end; the output end of the AND gate circuit inputs the flicker pulse signal into the signal input end of each threshold comparator.

[0023] According to a specific embodiment of the present application, the system module determines the steps of each voltage threshold and the corresponding detection time of the flicker pulse signal according to the comparison signal, including: determining the corresponding voltage threshold of the voltage unit connected to the threshold comparator corresponding to the comparison signal; obtaining the signal time when the flicker pulse signal corresponding to the comparison signal crosses the corresponding voltage threshold, and obtaining the noise time when the flicker pulse signal corresponding to the comparison signal first crosses the corresponding voltage threshold; associating the voltage threshold corresponding to each comparison signal with the signal time and the noise time.

[0024] According to a specific embodiment of the present application, the noise time is determined by acquiring the first time point after the signal crosses the baseline and does not return to the baseline within a preset time.

[0025] According to a specific implementation of the present application, the signal presence time and / or the noise presence time are both achieved by TDC identifying different transition point moments in the comparison signal.

[0026] According to a specific implementation of the present application, the noise time is acquired through a timing logic implemented by a threshold comparator and a TDC.

[0027] According to a specific embodiment of the present application, the step of obtaining the noise treatment time when the flicker pulse signal corresponding to the comparison signal first crosses the corresponding voltage threshold includes: if the flicker pulse signal is a single-peak flicker pulse signal, obtaining the trigger time of the front / back trigger point of the rising edge and the trigger time of the front / back trigger point of the falling edge as the noise treatment time, and setting other times to zero; if the flicker pulse signal is a multi-peak flicker pulse signal, obtaining the trigger time of all trigger points and marking the threshold number of each trigger point.

[0028] According to a specific implementation of the present application, the step of using the TDC method to obtain the noise time when the flash pulse signal corresponding to the comparison signal first crosses the corresponding voltage threshold includes: a counter counts the comparison signal, if the comparison signal is a high level, starts counting and accumulates successively according to the clock cycle, if the comparison signal is a low level, the count is cleared; when the count is 1 for the first time, the basic register triggers the latch of the current time; when the count reaches a preset number of times, the rising edge flag is set to 1, and the basic register assigns the current time as the actual time triggered by the rising edge to the rising jump register, and sets the register flag to 1; when the count is 1 again, the register flag is set to zero.

[0029] According to a specific implementation of the present application, the method also includes: when the register flag bit is 1 and the count is 0, the falling edge flag bit is set to 1, and the basic register assigns the current time as the actual time triggered by the falling edge to the falling jump register; obtains the actual time triggered by the rising edge and the actual time triggered by the falling edge of the comparison signal.

[0030] According to a specific implementation of the present application, the comparison signal is a differential signal, and the step of using the MTV method to obtain the noise treatment time when the flicker pulse signal corresponding to the comparison signal first crosses the corresponding voltage threshold includes: using a counter to perform a coarse measurement of the differential signal to obtain a first time corresponding to a plurality of consecutive rising edge jump moments; using a delay chain to perform a fine measurement of the differential signal to obtain the time interval between the plurality of consecutive rising edge jump moments and the first time as the second time; and obtaining the noise treatment time of the flicker pulse signal based on the first time and the second time.

[0031] According to a specific implementation of the present application, the delay chain includes N delay units connected in series, and the delay time of each delay unit is ΔT; the step of using the delay chain to perform fine measurement on the differential signal to obtain the time interval between each rising edge jump moment and the first time as the second time, and obtaining the noise treatment time of the flicker pulse signal according to the first time and the second time includes: inputting the differential signal into the delay chain, each delay unit respectively records the real-time level state when receiving the differential signal and transmits the real-time level state to the delay unit of the next stage, and each delay unit receives the real-time signal level state recorded by all the previous delay units; searching backward for the real-time level state recorded by each delay unit in sequence according to the cascade order, taking the delay unit corresponding to the real-time level state of the low level that appears for the first time as the target delay unit, and determining the number n of the target delay unit; calculating the noise treatment time according to the pulse width, number of stages and the first time of the flicker pulse signal.

[0032] In a third aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and the computer program is configured to execute the time detection method of the scintillation pulse signal provided in the second aspect when executed.

[0033] In a fourth aspect, an embodiment of the present application provides an electronic device, comprising: a processor and a memory storing a computer program, wherein the processor is configured to execute the time detection method of the scintillation pulse signal provided in the second aspect when running the computer program.

[0034] The time detection device, method, electronic device and medium of the scintillation pulse signal provided by the present application above, the system module determines the number of target threshold modules that need to be started for detection according to the estimated voltage amplitude of the scintillation pulse signal, and starts each target threshold module through a start instruction; the scintillation pulse signal is input into each target threshold module in parallel, the scintillation pulse signal and the corresponding voltage threshold signal output by the voltage unit are respectively connected to the input end of the threshold comparator, and the comparison signal output by the threshold comparator is sent to the system module; the system module determines each voltage threshold and the corresponding detection time of the scintillation pulse signal according to the comparison signal. Time detection can be performed on the scintillation pulse signal, and the real zero-crossing point of the scintillation pulse is obtained in a fully digital manner. When using the threshold comparator, it will not be affected by the baseline noise because the threshold is set too low. Therefore, the pulse detection time obtained by this method is more accurate, so that the time of energy deposition of particles in the scintillator is more accurate, thereby increasing the time resolution. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solution of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present application and should not be regarded as limiting the scope of protection of the present application. In each of the drawings, similar components are numbered similarly.

[0036] Figure 1 A schematic diagram of a scintillation detector and a scintillation pulse formation process provided by an embodiment of the present application is shown;

[0037] Figure 2 A pulse waveform schematic diagram of the LED method provided in an embodiment of the present application is shown;

[0038] Figure 3 A pulse waveform schematic diagram of the CFD method provided in an embodiment of the present application is shown;

[0039] Figure 4 A schematic diagram showing the structure of a threshold module setting of a time detection device for a scintillation pulse signal provided in an embodiment of the present application is shown;

[0040] Figure 5 A schematic structural diagram showing another threshold module setting of the time detection device for scintillation pulse signals provided in an embodiment of the present application;

[0041] Figure 6 A schematic diagram showing a flow chart of a method for detecting the time of a scintillation pulse signal provided in an embodiment of the present application is shown;

[0042] Figure 7 A schematic diagram showing a differential comparator involved in the time detection method of a scintillation pulse signal provided in an embodiment of the present application is shown;

[0043] Figure 8 A schematic diagram showing a time interpolation method involved in a time detection method for a scintillation pulse signal provided in an embodiment of the present application is shown;

[0044] Fig. 9 A schematic diagram showing a delay chain involved in a time detection method for a scintillation pulse signal provided in an embodiment of the present application is shown;

[0045] Fig.10 A logical timing diagram of noise time acquisition involved in the time detection method of the scintillation pulse signal provided in an embodiment of the present application is shown;

[0046] Fig.11 A schematic diagram of the process of acquiring the arrival time involved in the time detection method of the scintillation pulse signal provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0047] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0048] The components of the embodiments of the present application generally described and shown in the drawings herein may be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0049] Hereinafter, the terms "including", "having" and their cognates, which may be used in various embodiments of the present application, are intended only to indicate specific features, numbers, steps, operations, elements, components, or combinations of the foregoing items, and should not be understood as first excluding the existence of one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing items or adding the possibility of one or more features, numbers, steps, operations, elements, components, or combinations of the foregoing items.

[0050] Furthermore, the terms “first”, “second”, “third”, etc. are merely used for distinguishing descriptions and are not to be understood as indicating or implying relative importance.

[0051] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meanings as those generally understood by those skilled in the art to which the various embodiments of the present application belong. The terms (such as those defined in generally used dictionaries) will be interpreted as having the same meanings as the contextual meanings in the relevant technical field and will not be interpreted as having idealized meanings or overly formal meanings unless clearly defined in the various embodiments of the present application.

[0052] Example 1

[0053] The embodiment of the present application provides a time detection device for a flicker pulse signal, comprising a system module and a threshold voltage module; wherein the system module comprises a main chip, and the main chip is provided with a chip select pin and a signal pin; the threshold voltage module comprises a plurality of threshold modules, each of which is provided with a signal input terminal, a voltage input terminal, a signal output terminal, a chip select unit, a threshold comparator and a plurality of voltage units, in each threshold module, the voltage input terminal is connected to the main chip, the output terminal of the voltage unit and the signal input terminal are respectively connected to the input terminal of the threshold comparator, the chip select unit is connected to the chip select pin of the main chip, and the output terminal of the threshold comparator is connected via the The signal output terminal is connected to the signal pin of the main chip; the main chip configures the voltage threshold of each threshold module through each voltage unit; the system module determines the number of target threshold modules that need to be started for detection according to the estimated voltage amplitude of the flicker pulse signal, and starts each target threshold module through a start instruction; the flicker pulse signal is input into each target threshold module in parallel, and the flicker pulse signal and the corresponding voltage threshold signal output by the voltage unit are respectively connected to the input end of the threshold comparator, and the comparison signal output by the threshold comparator is sent to the system module; the system module determines each voltage threshold of the flicker pulse signal and the corresponding detection time according to the comparison signal. For example, the main chip can configure the voltage threshold of each threshold module by using a DAC (digital analog converter) or a resistor network voltage divider, and the detection time includes the signal time and the noise time.

[0054] The time detection device of the flicker pulse signal provided in the embodiment of the present application is used to realize the time detection processing of the flicker pulse signal. The time detection device of the flicker pulse signal provided in the embodiment of the present application includes a system module and a threshold voltage module, and the threshold voltage module includes a plurality of threshold modules, and each threshold module is provided with a plurality of voltage units. The main chip configures the voltage threshold of each threshold module. Through the combination of the voltage thresholds of the plurality of voltage units and the combination of the voltage thresholds of the threshold module, a pulse sampling scheme with selectable multiple voltage thresholds is provided.

[0055] Specifically, each threshold module is provided with a signal input terminal, a voltage input terminal, a signal output terminal, a chip selection unit, a threshold comparator and a plurality of voltage units. In each threshold module, the voltage input terminal is connected to the main chip, the output terminal of the voltage unit and the signal input terminal are respectively connected to the input terminal of the threshold comparator, the chip selection unit is connected to the chip selection pin of the main chip, and the output terminal of the threshold comparator is connected to the signal pin of the main chip via the signal output terminal. Optionally, the threshold comparator is a differential comparator.

[0056] According to a specific implementation of the present application, the voltage unit includes a digital-to-analog converter (DAC) for setting different voltage thresholds.

[0057] According to another specific implementation of the present application, the voltage unit includes a digital-to-analog converter and a voltage-dividing resistor connected in series to the digital-to-analog converter.

[0058] Furthermore, the voltage-dividing resistors in each voltage unit in the threshold module are equivalent circuits.

[0059] In this embodiment, the multiple voltage thresholds in the threshold module can be realized by a digital-to-analog converter (DAC) or a resistor network voltage divider or a combination of the two. The method of directly giving the voltage threshold using DAC has the advantage of flexible setting. The voltage threshold output by the DAC can be modified directly through the serial communication method, and the voltage threshold setting is stored in the E2PROM (also known as EEPROM, the abbreviation of electrically erasable programmable read-only memory), which can be automatically read each time the power is turned on. At the same time, the DAC method can also be used for more flexible correction. The resistor network voltage divider method has the advantages of higher accuracy and lower cost. Using the principle of resistor series voltage divider, each voltage threshold can be drawn from one end of a high-precision resistor.

[0060] Combining DAC and resistor network can make better use of the advantages of both. The many voltage thresholds to be set are divided into several voltage intervals. The maximum value of each interval, i.e., the voltage threshold, is provided by DAC, while the voltage threshold subdivision within the interval is realized by the resistor network. For example, for the voltage threshold setting range of 0-3V, 3 DACs provide 1V, 2V, and 3V respectively, while the voltage subdivision between 0-1V, 1-2V, and 2-3V is realized by the resistor network.

[0061] like Figure 4 As shown in FIG. 1 , it is a schematic diagram of the structure of a threshold module 100 of an 8-way voltage unit. The number of thresholds is not limited to 8, and can be 12, 16, 24, 32, etc. Figure 5 Another schematic diagram of a structure with 2 DACs and 16 thresholds is shown. The number of pins of threshold modules with different numbers of thresholds will be different.

[0062] Figure 4 and Figure 5 The pin types are mainly divided into three categories, namely power pins, input pins and output pins. The power pins include VCC, VEE, and GND, which are used to power DAC102 and threshold comparator 101. The input pin Signal_in is used to input a flash pulse signal, which can be a flash pulse signal. SDA, SCL, V ref Indicates the driving and reference voltage pins under the DAC solution, V max / V min Indicates the maximum / minimum voltage under the resistor network solution, CS indicates the chip select pin, and the output pin Vout1 、V out2 、V out3 、V out4 、V out5 、V out6 、V out7 、V out8 , used as the differential signal output after threshold comparison.

[0063] According to a specific embodiment of the present application, the chip select unit 103 includes an AND gate circuit 1031 and an inversion circuit 1032. The chip select unit 103 is connected to an input end of the AND gate circuit 1031 via the inversion circuit 1032, the signal input end is connected to another input end of the AND gate circuit 1031, and the output end of the AND gate circuit 1031 is connected to the signal input end of each threshold comparator 101.

[0064] The chip select signal is used to select whether to connect to the module. It is high by default and low after being inverted. When ANDed with the flash pulse signal, the output clock is low and will not trigger the threshold comparator. When the threshold module is needed, the chip select signal is pulled low and the flash pulse signal is valid.

[0065] According to a specific implementation of the present application, the main chip configures the voltage threshold of each threshold module through serial communication, and stores the voltage threshold setting in an erasable memory, and the threshold module automatically reads the voltage threshold from the erasable memory each time the power is turned on.

[0066] According to a specific implementation of the present application, the threshold module is connected to the system module in a plug-in manner; and the main chip is connected to each threshold module in a plug-in manner.

[0067] In this embodiment, plug-in connection can be used to meet different application requirements. In the prior art, such as the high-speed ADC direct digitization method, the high-speed ADC is a whole, which is not convenient for plug-in connection. However, the waveform digitization device provided by this application realizes the plug-in connection between the threshold module and the system module due to the modular setting. The plug-in connection between the main chip and each threshold module is convenient for flexible organization, updating and upgrading, and adaptation to different application requirements according to actual needs, and adapting to different accuracy requirements.

[0068] According to a specific implementation of the present application, the main chip configures the voltage threshold of each threshold module through serial communication, and stores the voltage threshold setting in an erasable memory, and the threshold module automatically reads the voltage threshold from the erasable memory each time the power is turned on.

[0069] In this embodiment, the threshold module and the system module are plug-in connected to meet the needs of different precisions. The system module can lead out all LVDS differential IO ports as needed, freely combine a specified number of threshold modules, and the system module recognizes the number of threshold modules started, and adaptively changes the size interval of each voltage threshold corresponding to each threshold module to adapt the corresponding number of thresholds. Freely combine multiple threshold modules according to the precision requirements to maximize the use of FPGA resources.

[0070] According to a specific implementation of the present application, the number of the threshold modules is M, the number of voltage units in each threshold module is N, and the number of voltage thresholds of the system module is M×N, wherein M and N are both positive integers.

[0071] According to a specific implementation of the present application, the voltage thresholds of adjacent threshold modules gradually increase and the intervals are equal, and the voltage thresholds of adjacent voltage units in the threshold module gradually increase and the intervals are equal.

[0072] Taking the total number of thresholds as 512 and the number of threshold modules as 64 as an example, the FPGA part sets an 8-way DAC, that is, 8-way voltage thresholds, which are equally spaced. The threshold size can be freely modified. Assume that it is set to V 64 、V 128 、V 192 ,…,V 512 , 8 external threshold modules are connected, and the 64 thresholds in each threshold module are equally spaced. Taking the first threshold module as an example, it is V0, V1, ..., V 63 , other threshold modules are analogous in turn, and their DAC and resistor network solutions can be freely selected according to requirements.

[0073] When the accuracy requirement is 512 thresholds, the 3.3V voltage is divided into 512 equal parts (9 bits), the chip select signals of the 8 threshold modules are all pulled low, and each threshold is set in turn.

[0074] According to a specific implementation of the present application, the system module is configured to identify the number of threshold modules that are enabled, and adaptively change the size interval of the corresponding voltage threshold in each threshold module to adapt to the corresponding number of thresholds.

[0075] For example, the number of threshold modules for identification startup can be determined according to the accuracy requirements. If the accuracy requirements are not so high, such as 256 thresholds, the chip select signals of the first four threshold modules can be pulled low, and the thresholds can be read at intervals. Furthermore, if the traditional MVT solution is used, a threshold module with 8 thresholds can be selected, and only the chip select signal of the first threshold module can be pulled low. The threshold is modified accordingly, and it can be used as a traditional 8-threshold MVT solution.

[0076] The time detection device for the scintillation pulse signal provided in this embodiment can perform time detection on the scintillation pulse signal, obtain the real zero-crossing point of the scintillation pulse in a fully digital manner, and will not be affected by baseline noise due to the threshold value being set too low when using the threshold comparator. Therefore, the pulse detection time obtained by this method is more accurate, so that the time of energy deposition of particles in the scintillator can be obtained more accurately, thereby increasing the time resolution.

[0077] Example 2

[0078] See also Figure 6 , is a flow chart of a method for detecting the time of a scintillation pulse signal provided in an embodiment of the present application, and the method is applied to the device for detecting the time of a scintillation pulse signal provided in the above embodiment. Figure 6 As shown, the method mainly comprises the following steps:

[0079] In step S601, the system module determines the number of target threshold modules that need to be activated for detection according to the estimated voltage amplitude of the scintillation pulse signal, and activates each target threshold module through an activation instruction.

[0080] The system module is connected to multiple threshold modules, first obtains the estimated voltage amplitude of the flicker pulse signal to be sampled, and determines the number of threshold modules required according to the estimated voltage amplitude of the flicker pulse signal, which is defined as the target threshold module. A start instruction is sent to the chip select unit of each target threshold module through the chip select pin to start the target threshold module.

[0081] According to a specific implementation of the present application, after the step of starting each target threshold module through a start instruction, the method further includes:

[0082] Configure the voltage threshold of each target threshold module;

[0083] The voltage threshold of each target threshold module is split into voltage thresholds of corresponding voltage units.

[0084] According to a specific implementation of the present application, the voltage threshold of each target threshold module is split into the voltage threshold of the corresponding voltage unit in the following manner:

[0085] The number of the target threshold modules is M, the number of the voltage units is N, M and N are both positive integers, and the number accuracy of the voltage threshold required for detection is P=M×N;

[0086] The voltage threshold of the i-th target threshold module is recorded as V i×N , where 1≤i≤M;

[0087] Set the voltage threshold V of the i-th target threshold module i×NThe voltage threshold of each voltage unit in the corresponding N voltage units is split.

[0088] For example, according to a specific implementation of the present application, the number of threshold modules M is 8, and the number of voltage units in the threshold module is 64; if the voltage quantity accuracy required for detection is 512, the number of modules of the target threshold module is 8, and the voltage thresholds of each target threshold module are V 64 、V 128 、V 192 ,…,V 512 , where the voltage threshold is V 64 The voltage thresholds of each voltage unit in the target threshold module are V0, V1, ..., V 63 , the voltage threshold is V 512 The voltage threshold of each voltage unit in the target threshold module is V 448 、V 449 ,…,V 511 ;

[0089] If the voltage number accuracy required for detection is 256, the number of target threshold modules is 4, and the voltage thresholds of each target threshold module are V 64 、V 128 、V 192 ,…,V 256 , where the voltage threshold is V 64 The voltage thresholds of each voltage unit in the target threshold module are V0, V1, ..., V 63 , the voltage threshold is V 256 The voltage threshold of each voltage unit in the target threshold module is V 192 、V 193 ,…,V 255 .

[0090] According to a specific implementation of the present application, the step of sending a start instruction to a chip select unit of each target threshold module through a chip select pin includes:

[0091] Switch the chip select pin corresponding to each target threshold module to a low level;

[0092] The signal input end of each target threshold module is connected to the flicker pulse signal in parallel, and the input end of the threshold comparator is connected to the flicker pulse signal and the voltage threshold signal output by each voltage unit respectively. The chip select pin is high by default, and the chip select pin corresponding to each target threshold module is low after being inverted, and is ANDed with the flicker pulse signal. The output clock is low and will not trigger the threshold module. When the corresponding target threshold module needs to be triggered, the chip select signal of the corresponding target threshold module is pulled low, and the flicker pulse signal is valid.

[0093] Step S602, input the flicker pulse signal in parallel to each target threshold module, connect the flicker pulse signal and the corresponding voltage threshold signal output by the voltage unit to the input end of the threshold comparator respectively, and send the comparison signal output by the threshold comparator to the system module.

[0094] Exemplarily, the target threshold module started by the flicker pulse signal is input in parallel and connected to one input end of each threshold comparator, and the different voltage thresholds corresponding to each voltage unit are input to the other input end of the corresponding threshold comparator. Each threshold comparator generates a comparison signal according to the amplitude of the flicker pulse signal and the size of the corresponding voltage threshold, and outputs it to the system module.

[0095] According to a specific implementation of the present application, the step of connecting the flicker pulse signal and the corresponding voltage threshold signal output by the voltage unit to the input end of the threshold comparator respectively, and sending the comparison signal output by the threshold comparator to the system module includes:

[0096] The low-level chip selection signal connected to the chip selection unit is inverted by the inversion circuit of the chip selection unit and then input into the AND gate circuit of the chip selection unit;

[0097] The scintillation pulse signal is input into the AND gate circuit via the signal input terminal;

[0098] The output end of the AND gate circuit inputs the flicker pulse signal into the signal input end of each threshold comparator.

[0099] The chip selection unit includes an AND gate circuit and an inversion circuit, the chip selection pin of the system module is preset to a high level, and the step of outputting a comparison signal to the system module includes:

[0100] The low-level chip selection signal connected to the chip selection unit is inverted by the inversion circuit and then input into the AND gate circuit;

[0101] The scintillation pulse signal is input into the AND gate circuit via the signal input terminal;

[0102] The output end of the AND gate circuit inputs the flicker pulse signal into the signal input end of each threshold comparator. If the amplitude of the flicker pulse signal is greater than the corresponding voltage threshold received by the threshold comparator, the threshold comparator outputs a jump signal to the system module and records the time when the jump occurs through the system module; if the amplitude of the flicker pulse signal is less than the corresponding voltage threshold received by the threshold comparator, the threshold comparator does not jump.

[0103] The chip select pin is high by default, and low after inversion. When ANDed with the flash pulse signal, the output clock is low and will not trigger the comparator threshold. When the threshold module is needed, the chip select signal is pulled low and the flash pulse signal is valid.

[0104] Step S603: the system module determines each voltage threshold value and the corresponding detection time of the scintillation pulse signal according to the comparison signal.

[0105] According to a specific implementation of the present application, step S603 includes:

[0106] Determine a voltage threshold corresponding to a voltage unit connected to a threshold comparator corresponding to the comparison signal;

[0107] Acquire the signal time when the scintillation pulse signal corresponding to the comparison signal crosses the corresponding voltage threshold, and acquire the noise time when the scintillation pulse signal corresponding to the comparison signal crosses the corresponding voltage threshold for the first time;

[0108] The voltage threshold corresponding to each comparison signal is associated with the signal time and the noise time.

[0109] In this embodiment, the noise time is determined by acquiring the first time point after the signal crosses the baseline and does not return to the baseline within a preset time.

[0110] In this embodiment, the signal presence time and / or the noise presence time are both realized by TDC identifying different transition point moments in the comparison signal.

[0111] In this embodiment, the noise presence time is acquired through a timing logic implemented by a threshold comparator and a TDC.

[0112] In this embodiment, the waveform digitization processing is mainly performed by detecting the flicker pulse signal through the voltage threshold, obtaining the time when the flicker pulse signal triggers each voltage threshold, and then restoring the waveform based on the voltage value-time information.

[0113] The time information detection of the flicker pulse signal can be divided into two aspects: the signal time acquisition method and the noise time acquisition method. The signal time acquisition method can be acquired by the existing MVT method, such as recording the flip time of the high and low levels in the comparison signal output by the comparator through TDC to obtain the time corresponding to the rising edge or falling edge of the flicker pulse signal crossing different thresholds. However, when the threshold is set to be equivalent to the noise baseline, it is more difficult to acquire the time corresponding to the signal below the noise voltage threshold. The noise time acquisition method provided in this embodiment is based on FPGA to directly acquire the first time point after the pulse exceeds the baseline and does not return to the baseline in a short time, and this time point is used as the start time of the pulse.

[0114] In this embodiment, the step of obtaining the noise time when the scintillation pulse signal corresponding to the comparison signal first crosses the corresponding voltage threshold by TDC method includes:

[0115] The counter counts the comparison signal, and if the comparison signal is at a high level, starts counting and accumulates successively according to the clock cycle; if the comparison signal is at a low level, the count is reset;

[0116] When the count reaches 1 for the first time, the base register triggers latching of the current time;

[0117] When the count reaches the preset number of times, the rising edge flag is set to 1, and the basic register assigns the current time as the actual time triggered by the rising edge to the rising jump register, and sets the register flag to 1;

[0118] When the count reaches 1 again, the register flag is set to zero.

[0119] In this embodiment, the method further includes:

[0120] When the register flag is 1 and the count is 0, the falling edge flag is set to 1, and the basic register uses the current time as the actual time triggered by the falling edge to assign the falling jump register;

[0121] The actual time when the rising edge triggers and the actual time when the falling edge triggers of the comparison signal are acquired.

[0122] Those skilled in the art should understand that "short time" in the present application is a relative concept, which may vary according to the type, amplitude or detection accuracy requirements of the scintillation pulse signal. For example, for some signals with relatively regular waveforms, short time may refer to no more than 100ns or no more than 50ns. For some applications with higher detection accuracy requirements, short time may refer to no more than 20ns or no more than 10ns.

[0123] The above process mainly uses the threshold comparator and TDC. TDC is used to obtain time, and the threshold comparator is used to compare the signal (including the flicker pulse signal and the noise signal) with the voltage threshold. When the signal crosses the voltage threshold, a corresponding edge trigger signal is generated (such as the edge time corresponding to the high and low level flip). The threshold comparator uses a differential comparator, for example Figure 7The threshold comparator based on LVDS input interface is shown. The high and low levels in differential signal communication are identified by the relative size of the voltages at the positive input terminal and the negative input terminal in the differential interface, that is, when the voltage at the positive input terminal is higher than the voltage at the negative input terminal, the input signal is considered to be logic '1'; when the voltage at the positive input terminal is lower than the voltage at the negative input terminal, the input signal is considered to be logic '0'. Connect the flash pulse signal to the positive input terminal and connect the voltage threshold to the negative input terminal. When the pulse signal voltage amplitude is higher than the threshold, the differential comparator considers the input signal to be logic '1'; when the pulse signal voltage amplitude is lower than the threshold, the differential comparator considers the input signal to be logic '0'. The moment when the analog pulse signal crosses the voltage threshold corresponds to the moment when the rising edge jump or falling edge jump of the logic signal identified by the LVDS receiver occurs.

[0124] In this embodiment, the comparison signal is a differential signal, and the step of using the MTV method to obtain the noise time when the flicker pulse signal corresponding to the comparison signal first crosses the corresponding voltage threshold includes:

[0125] Using a counter to roughly measure the differential signal, obtaining a first time corresponding to a plurality of consecutive rising edge transition moments;

[0126] Using a delay chain to perform fine measurement on the differential signal, and obtaining the time interval between the consecutive multiple rising edge transition moments and the first time as the second time;

[0127] The noise removal time of the scintillation pulse signal is obtained according to the first time and the second time.

[0128] Use TDC to calculate the transition time, that is, the time to reach the threshold. The time obtained by TDC is realized by time interpolation using the internal resources of FPGA. Figure 8 The figure shows a schematic diagram of the time interpolation method. The measurement of the edge signal arrival time consists of two parts: coarse time measurement and fine time measurement. Coarse time measurement refers to a long-range, low-precision measurement of the signal occurrence time, which is usually achieved by using a counter to count the number of flips of the periodic clock signal. c It is the coarse time of the rising edge jump time of the measured signal Hit under the interpolation TDC measurement. The coarse time measurement can be completed by recording the number of periodic clock signal flips when the measured signal jumps to a high level, that is, T c =n×T, where n is also called the coarse count; T is the cycle time of the clock signal. Fine time measurement refers to a high-precision measurement of the interval time between the signal occurrence moment and the moment corresponding to the coarse time count, usually using a delay chain for measurement. f is the fine time measurement result, which is the time when the rising edge jump of the measured signal Hit occurs and Tc The time interval between moments. The pulse occurrence time is measured by time interpolation method, and the measurement result includes two parts, namely the rough time T in the figure. c and fine time T f The time of pulse occurrence is recorded as T c -T f .

[0129] In one embodiment, the delay chain includes N delay units connected in series, and the delay time of each delay unit is ΔT;

[0130] The step of using a delay chain to perform fine measurement on the differential signal, obtaining the time interval between each rising edge transition moment and the first time as the second time, and obtaining the noise removal time of the scintillation pulse signal according to the first time and the second time includes:

[0131] The differential signal is input into the delay chain, each delay unit respectively records the real-time level state when receiving the differential signal and transmits the real-time level state to the delay unit at the subsequent stage, and each delay unit receives the real-time signal level state recorded by all the previous delay units;

[0132] Searching the real-time level states recorded by each delay unit in sequence backward in the cascade order, taking the delay unit corresponding to the real-time level state that appears low level for the first time as the target delay unit, and determining the number of stages n of the target delay unit;

[0133] The noise exposure time is calculated according to the pulse width and the level of the scintillation pulse signal and the first time.

[0134] like Fig. 9 The figure shows a schematic diagram of a delay chain, which is composed of a plurality of delay units cascaded in series, and the delay time of each delay unit is ΔT. The signal to be measured Hit is connected to the first-stage delay unit, which records the level state of the current Hit signal. After ΔT time, the signal state recorded by the first-stage delay unit will be transmitted to the second-stage delay unit and the current signal level state will be re-recorded; at the same time, the second-stage delay unit will pass its previously recorded level state to the next-stage delay unit and re-record the level state passed by the first-stage delay unit. The working method of subsequent delay units is similar. At time t, the level state recorded by the nth-stage delay unit is the level state of the signal to be measured Hit before time n×ΔT. Therefore, the time for the rising edge jump of the signal to be measured Hit is measured by time interpolation method, and it is only necessary to measure the time at T f By constantly recording the level state recorded by each delay unit in the delay chain and finding the first delay unit with a low level state from the first level to the last level, fine time measurement can be achieved. In this way, the signal processing time can be obtained.

[0135] The acquisition of the noise time is based on FPGA, using threshold comparator and TDC to implement a timing logic, so as to obtain effective time information of the noise. If the voltage threshold of the threshold comparator is set below the noise amplitude, when there is a voltage greater than the set threshold, the level will flip. Fig.10 The figure shows a simple schematic diagram. The timing above is the clock cycle, and the level flipping of the threshold comparator output is shown below. When the pulse does not come, there will be a baseline noise, which will also continuously trigger the threshold comparator, forming a result between A and B. The level keeps flipping, and the time at this time is not the real start time of the pulse, so some timing judgment needs to be added.

[0136] like Fig.11 The figure shows the sequential logic process provided by the present embodiment. clk is the clock signal, signal is the level signal output by the threshold comparator, time is the continuously changing time information, cnt is the counter output signal, and reg, flag_up are the flag signals. When there is no pulse input, signal will continue to jump like the previous part in the figure. At this time, the signal jump positions of multiple TDCs in one clock cycle need to be judged. If the signal is high at this time, cnt starts counting; if the signal is low at this time, cnt is cleared. When the pulse level data enters, cnt will continue to accumulate according to the clock signal until the pulse ends and returns to the state when there is no pulse input. When cnt=1, reg triggers the latch to store the current time information; when cnt reaches a certain count N, the flag_up signal will be pulled high; and when the flag_up signal is high, the reg data will be assigned to reg_timeup, which is the real time triggered by the rising edge. In this way, the real time when the pulse starts can be obtained.

[0137] This method requires knowing the approximate pulse width in advance and setting an N to make a judgment. This N is used to roughly estimate the pulse width. When the pulse width is large, the value of N will be very large. At this time, due to the limited number of cnt digits, certain settings are required. When cnt reaches the maximum number of digits, the next step is to assign cnt to N+1 and continue to accumulate the count until the maximum value is reached.

[0138] Furthermore, with a 64 threshold (TH_ALL), a reference voltage of 3.3V (V ref), the noise amplitude is 80mv as an example, the threshold is evenly distributed from 0 to 3.3V, that is, the interval is 3.3V / (64–1)=52.4mv, the lowest 2-way threshold (TH_Trigger, 0mv, 52.4mv) adopts the noise time acquisition method, and the other thresholds adopt the signal time acquisition method, so that the time information of the trigger point under any threshold can be obtained. And the parameters can be quickly adjusted and modified.

[0139] Exemplarily, the system module restores the waveform of the scintillation pulse signal in a time sequence according to the integrated information of all time-voltage pairs.

[0140] After the system module obtains the data pair information composed of each voltage threshold and detection time, it restores and displays the waveform to realize waveform digitization. The specific methods of restoring the waveform may include: 1. scatter plot; 2. line graph; 3. curve smoothing; 4. equal time interval interpolation method (V-T transformation).

[0141] After obtaining the horizontal axis time information of the waveform according to the above steps, it is also necessary to obtain the coordinate point information. When multiple threshold modules are used in free combination, each threshold processing is a separate processing channel, and the thresholds are in parallel. Each threshold has a flag signal, which can be regarded as a synchronous processing of the comparator output signal. When the rising edge of the pulse is recognized, it is pulled high. When the falling edge is recognized, it is delayed by one clock cycle to write the data into the cache, and then pulled low. When the rising edge is recognized again, this operation is repeated.

[0142] In the case where there is a baseline in the flicker pulse signal, the pulse signal segment from the pulse arrival time to the pulse end time, or the pulse signal segment within the period when the minimum noise threshold is triggered by the pulse falling edge is considered a group of pulses. After a group of pulses is identified, the pulse information is packaged and sent to the PC, or for needs such as area calculation, time calculation, etc.

[0143] Furthermore, the step of obtaining the noise location time when the scintillation pulse signal corresponding to the comparison signal first crosses the noise threshold includes:

[0144] If the scintillation pulse signal is a single-peak pulse signal, the trigger time of the front / rear trigger point of the rising edge and the trigger time of the front / rear trigger point of the falling edge are obtained as the noise time, and the other times are set to zero;

[0145] If the scintillation pulse signal is a multi-peak pulse signal, the triggering time of all triggering points is obtained and the threshold number of each triggering point is marked.

[0146] This embodiment provides five ways to output time information, which can be selected through the FPGA firmware implementation method: 1. Take the rising edge before and the falling edge before; 2. Take the rising edge before and the falling edge after; 3. Take the rising edge after and the falling edge before; 4. Take the rising edge after and the falling edge after; 5. Output all points. Among them, methods 1 to 4 are suitable for single-peak pulse signals, and method 5 is suitable for multi-peak pulse signals.

[0147] For the output method of the front and back points of the single-peak pulse signal, the coordinate point obtained by "taking the front" is the first value of the trigger. For the rising edge, when the flag signal is pulled high, the time information is latched immediately; the same is true for the falling edge, when the flag signal is pulled low, the time information is latched immediately. The coordinate point obtained by "taking the back" is the last value of the trigger. For the rising edge, when the flag signal is pulled high, the time information is not latched, and it will continue to change according to the pulse triggering situation; the same is true for the falling edge, when the flag signal is pulled low, the time information is also not latched. When the end of the pulse is recognized (the pulse end time or the minimum threshold of over-noise is triggered by the falling edge of the pulse), the time information of the threshold is output.

[0148] For the full-point output mode of multi-peak pulse signals, the present invention will add a "threshold number" as a frame header in each threshold output information, and write the time information into the cache whenever the falling edge of the flag signal is identified. Similarly, when the end of the pulse is identified (the pulse end time or the minimum threshold of over-noise is triggered by the falling edge of the pulse), the time information of the threshold is output. This method will have a dead time of 1 clock cycle, but considering comprehensively, it has no effect on the reproduction of the waveform. Those skilled in the art should note that the dead time is for a single threshold, and there is no dead time between thresholds. Assuming a system clock of 200M, the dead time is 5ns. If a single threshold fluctuation occurs within 5ns, it can be approximately regarded as the superposition of noise signals, and there is no visible effect on the final waveform recovery.

[0149] In the specific implementation, if method 1 to method 4 are selected, the time information corresponding to the untriggered threshold will be assigned a value of zero. For method 5, since the output information contains the threshold number, this problem does not need to be considered. Regardless of the above methods, the length of the output information can be calculated, so the size of the data packet can be expressed as a parameter to achieve an adaptive output coordinate sequence.

[0150] It should be noted that cache is a storage medium, including non-volatile and / or volatile items that can be used to store information by any method or technology. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM). The output mode in this embodiment can be a mode of communicating with the host computer such as 100M Ethernet, Gigabit Ethernet, 10G FSP optical fiber, etc.

[0151] Compared with the traditional MVT method, the time detection method of the flicker pulse signal provided by the present application does not need to restore the pulse waveform by solving the equation group to obtain the function curve in the process of processing the pulse signal, and expands the traditional MVT method from sampling only for known pulse shape signals to sampling any pulse signal. Since the number of thresholds can be modified freely, the parameter adjustment can be fast, simple and adaptive output coordinate sequence, which can adapt to different sampling requirements and has greater flexibility. Its sampling effect can be equivalent to an analog-to-digital converter with a sampling rate of 100KSps to 100GSps. In this embodiment, the signal sampling point is obtained only when the threshold is triggered, and the result will be output. It is non-continuous sampling and power consumption is reduced. The position of the acquired sampling point is closely related to the measured signal. The signal changes frequently → rich information → many samples, and the signal changes slowly → less information → fewer samples, and almost no redundant data is generated; in application scenarios such as spectrum acquisition, the points generated are all useful information, and there is no need to accumulate a large number of points (with redundant data) like a high-speed ADC. There is huge potential for development. The TDC accuracy is affected by the performance of the device and can theoretically reach the picosecond level. If the storage medium / transmission rate is sufficient, it can be comparable to a sampling rate of about 500GSps+.

[0152] The embodiments of the present application also relate to electronic devices capable of implementing the methods of the embodiments of the present application.

[0153] In some embodiments, an electronic device is provided, which may include a processor and a memory storing a computer program, wherein the processor is configured to execute the time detection method of the scintillation pulse signal of any embodiment of the present application when running the computer program.

[0154] In some embodiments, the time detection method of the scintillation pulse signal described in the present application can be implemented using a single or multiple electronic devices. In some embodiments, it can be implemented using cloud or distributed electronic devices.

[0155] In some embodiments, the electronic device includes a processor, which can perform various appropriate operations and processes according to the program and / or data stored in the read-only memory (ROM) or the program and / or data loaded from the storage portion into the random access memory (RAM). The processor can be a single-core or multi-core processor, or it can include multiple processors. In some embodiments, the processor may include a general-purpose main processor (such as a CPU) and one or more special coprocessors, such as a graphics processing unit (GPU), a neural network processor (NPU), a digital signal processor (DSP) or other general or application-specific integrated circuits. In RAM, various programs and data required for the operation of the electronic device are also stored. The processor, ROM, and RAM are connected to each other via a bus.

[0156] The processor and the memory are used together to execute the program stored in the memory. When the program is executed by the computer, the steps or functions of the methods described in the above embodiments can be implemented.

[0157] In some embodiments, the electronic device may be combined with various components to obtain a method, device, and system having the advantages of the present invention.

[0158] Although not shown, in some embodiments, a computer-readable storage medium is also provided, storing a computer program, which is configured to execute any method of the present application embodiment when it is run. The computer program includes various program modules / units constituting the device according to the embodiment of the present application, and the computer program composed of various program modules / units can realize the functions corresponding to the various steps in the method described in the above embodiment when it is executed. The computer program can also be run on an electronic device as described in the embodiment of the present application.

[0159] The time detection device for scintillation pulse signals provided can perform time detection on scintillation pulse signals, obtain the real zero-crossing point of the scintillation pulse in a fully digital manner, and will not be affected by baseline noise due to too low a threshold value when using a threshold comparator. Therefore, the pulse detection time obtained by this method is more accurate, so that the time of energy deposition of particles in the scintillator is obtained more accurately, thereby increasing the time resolution.

[0160] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A time detection device for a scintillation pulse signal, characterized in that: It includes a system module and a threshold voltage module; wherein the system module includes a main chip, and the main chip is provided with a chip selection pin and a signal pin; The threshold voltage module includes a plurality of threshold modules, each of which is provided with a signal input terminal, a voltage input terminal, a signal output terminal, a chip selection unit, a threshold comparator and a plurality of voltage units. In each threshold module, the voltage input terminal is connected to the main chip, the output terminal of the voltage unit and the signal input terminal are respectively connected to the input terminal of the threshold comparator, the chip selection unit is connected to the chip selection pin of the main chip, and the output terminal of the threshold comparator is connected to the signal pin of the main chip via the signal output terminal; The main chip configures the voltage threshold of each threshold module through each voltage unit; The system module determines the number of target threshold modules that need to be activated for detection according to the estimated voltage amplitude of the scintillation pulse signal, and activates each target threshold module through a startup instruction; Input the flicker pulse signal to each target threshold module in parallel, connect the flicker pulse signal and the corresponding voltage threshold signal output by the voltage unit to the input end of the threshold comparator respectively, and send the comparison signal output by the threshold comparator to the system module; The system module determines each voltage threshold value and the corresponding detection time of the scintillation pulse signal according to the comparison signal.

2. The time detection device of the scintillation pulse signal according to claim 1, characterized in that: The voltage unit includes a digital-to-analog converter.

3. The time detection device of the scintillation pulse signal according to claim 1, characterized in that: The voltage unit includes a digital-to-analog converter and a voltage dividing resistor connected in series to the digital-to-analog converter.

4. The time detection device of the scintillation pulse signal according to claim 3, characterized in that: The voltage-dividing resistors in each voltage unit in the threshold module are equivalent circuits.

5. The time detection device of the scintillation pulse signal according to claim 1, characterized in that: The threshold comparator is a differential comparator.

6. The time detection device of the scintillation pulse signal according to any one of claims 1 to 5, characterized in that: The chip select unit includes an AND gate circuit and an inversion circuit. The chip select unit is connected to one input end of the AND gate circuit via the inversion circuit, the signal input end is connected to the other input end of the AND gate circuit, and the output end of the AND gate circuit is connected to the signal input end of each threshold comparator.

7. The time detection device of the scintillation pulse signal according to claim 1, characterized in that: The main chip configures the voltage threshold of each threshold module through serial communication, and stores the voltage threshold setting in an erasable memory. The threshold module automatically reads the voltage threshold from the erasable memory each time it is powered on.

8. The time detection device of the scintillation pulse signal according to claim 1, characterized in that: The threshold module is connected to the system module in a plug-in manner; the threshold module is connected to the system module in a plug-in manner; the main chip is connected to each threshold module in a plug-in manner.

9. The time detection device of the scintillation pulse signal according to claim 1, characterized in that: The number of the threshold modules is M, the number of voltage units in each threshold module is N, and the number of voltage thresholds of the system module is M×N, wherein M≥2 and N is a positive integer.

10. The time detection device of the scintillation pulse signal according to claim 9, characterized in that: The voltage thresholds corresponding to adjacent threshold modules gradually increase and the intervals are equal, and the voltage thresholds corresponding to adjacent voltage units in the same threshold module gradually increase and the intervals are equal.

11. The time detection device of the scintillation pulse signal according to claim 1, characterized in that: The system module is configured to identify the number of threshold modules that are enabled, and adaptively change the size interval of the corresponding voltage threshold in each threshold module to adapt to the corresponding number of thresholds.

12. A time detection method for a scintillation pulse signal, characterized in that: The time detection method of the scintillation pulse signal comprises: The system module determines the number of target threshold modules that need to be activated for detection according to the estimated voltage amplitude of the flicker pulse signal, and activates each target threshold module through a startup instruction; Input the flicker pulse signal to each target threshold module in parallel, connect the flicker pulse signal and the corresponding voltage threshold signal output by the voltage unit to the input end of the threshold comparator respectively, and send the comparison signal output by the threshold comparator to the system module; The system module determines each voltage threshold value and the corresponding detection time of the scintillation pulse signal according to the comparison signal.

13. The time detection method of scintillation pulse signal according to claim 12, characterized in that: After the step of starting each target threshold module by a start instruction, the time detection method of the scintillation pulse signal further includes: Configure the voltage threshold of each target threshold module; The voltage threshold of each target threshold module is split into voltage thresholds of corresponding voltage units.

14. The time detection method of scintillation pulse signal according to claim 13, characterized in that: The voltage threshold of each target threshold module is split into the voltage thresholds of the corresponding voltage units in the following manner: The number of the target threshold modules is M, the number of the voltage units is N, M and N are both positive integers, and the number accuracy of the voltage threshold required for detection is P=M×N; The voltage threshold of the i-th target threshold module is recorded as V i×N , where 1≤i≤M; Set the voltage threshold V of the i-th target threshold module i×N The voltage threshold of each voltage unit in the corresponding N voltage units is split.

15. The time detection method of scintillation pulse signal according to claim 12, characterized in that: The step of starting each target threshold module through a start instruction includes: Switch the chip select pin corresponding to each target threshold module to a low level; The signal input end of each target threshold module is connected to the flicker pulse signal in parallel, and the input end of the threshold comparator is respectively connected to the flicker pulse signal and the voltage threshold signal output by each voltage unit. The chip select pin is high level by default, and the chip select pin corresponding to each target threshold module is low level after inversion, and is ANDed with the flicker pulse signal. The output clock is low level and will not trigger the corresponding target threshold module. When the corresponding target threshold module needs to be triggered, the chip select signal of the corresponding target threshold module is pulled low, and the flicker pulse signal is valid.

16. The time detection method of scintillation pulse signal according to claim 12, characterized in that: The steps of respectively connecting the flicker pulse signal and the corresponding voltage threshold signal output by the voltage unit to the input end of the threshold comparator, and sending the comparison signal output by the threshold comparator to the system module include: The low-level chip selection signal connected to the chip selection unit is inverted by the inversion circuit of the chip selection unit and then input into the AND gate circuit of the chip selection unit; The scintillation pulse signal is input into the AND gate circuit via the signal input terminal; The output end of the AND gate circuit inputs the flicker pulse signal into the signal input end of each threshold comparator.

17. The time detection method of a scintillation pulse signal according to any one of claims 12 to 16, characterized in that: The step of the system module determining each voltage threshold and the corresponding detection time of the scintillation pulse signal according to the comparison signal comprises: Determine a voltage threshold corresponding to a voltage unit connected to a threshold comparator corresponding to the comparison signal; Acquire the signal time when the scintillation pulse signal corresponding to the comparison signal crosses the corresponding voltage threshold, and acquire the noise time when the scintillation pulse signal corresponding to the comparison signal crosses the corresponding voltage threshold for the first time; The voltage threshold corresponding to each comparison signal is associated with the signal time and the noise time.

18. The time detection method of scintillation pulse signal according to claim 17, characterized in that: The noise time is determined by obtaining the first time point after the signal crosses the baseline and does not return to the baseline within a preset time.

19. The time detection method of scintillation pulse signal according to claim 17, characterized in that: The signal time and / or the noise time are both achieved by TDC identifying different jump point moments in the comparison signal.

20. The time detection method of scintillation pulse signal according to claim 17, characterized in that: The noise time is obtained through a threshold comparator and a timing logic implemented by a TDC.

21. The time detection method of scintillation pulse signal according to claim 17, characterized in that: The step of obtaining the noise time when the scintillation pulse signal corresponding to the comparison signal first crosses the corresponding voltage threshold comprises: If the scintillation pulse signal is a single-peak scintillation pulse signal, the trigger time of the front / rear trigger point of the rising edge and the trigger time of the front / rear trigger point of the falling edge are obtained as the noise time, and other times are set to zero; If the scintillation pulse signal is a multi-peak scintillation pulse signal, the triggering time of all triggering points is obtained and the threshold number of each triggering point is marked.

22. The time detection method of scintillation pulse signal according to claim 17, characterized in that: The step of obtaining the noise time when the scintillation pulse signal corresponding to the comparison signal first crosses the corresponding voltage threshold by TDC method comprises: The counter counts the comparison signal, and if the comparison signal is at a high level, starts counting and accumulates successively according to the clock cycle; if the comparison signal is at a low level, the count is reset; When the count reaches 1 for the first time, the base register triggers latching of the current time; When the count reaches the preset number of times, the rising edge flag is set to 1, and the basic register assigns the current time as the actual time triggered by the rising edge to the rising jump register, and sets the register flag to 1; When the count reaches 1 again, the register flag is set to zero.

23. The time detection method of scintillation pulse signal according to claim 22, characterized in that: The time detection method further includes: When the register flag is 1 and the count is 0, the falling edge flag is set to 1, and the basic register uses the current time as the actual time triggered by the falling edge to assign the falling jump register; The actual time when the rising edge triggers and the actual time when the falling edge triggers of the comparison signal are acquired.

24. The time detection method of scintillation pulse signal according to claim 17, characterized in that: The comparison signal is a differential signal, and the step of using the MTV method to obtain the noise time when the flicker pulse signal corresponding to the comparison signal first crosses the corresponding voltage threshold includes: Using a counter to roughly measure the differential signal, obtaining a first time corresponding to a plurality of consecutive rising edge transition moments; Using a delay chain to perform fine measurement on the differential signal, and obtaining the time interval between the consecutive multiple rising edge transition moments and the first time as the second time; The noise removal time of the scintillation pulse signal is obtained according to the first time and the second time.

25. The time detection method of scintillation pulse signal according to claim 24, characterized in that: The delay chain includes N delay units connected in series, and the delay time of each delay unit is ΔT; The step of using a delay chain to perform fine measurement on the differential signal, obtaining the time interval between each rising edge transition moment and the first time as the second time, and obtaining the noise removal time of the scintillation pulse signal according to the first time and the second time includes: The differential signal is input into the delay chain, each delay unit respectively records the real-time level state when receiving the differential signal and transmits the real-time level state to the delay unit at the subsequent stage, and each delay unit receives the real-time signal level state recorded by all the previous delay units; Searching the real-time level states recorded by each delay unit in sequence backward in the cascade order, taking the delay unit corresponding to the real-time level state that appears low level for the first time as the target delay unit, and determining the number of stages n of the target delay unit; The noise exposure time is calculated according to the pulse width and the level of the scintillation pulse signal and the first time.

26. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and the computer program is configured to execute the time detection method of the scintillation pulse signal according to any one of claims 12 to 25 when executed.

27. An electronic device, characterized in that: include: A processor and a memory storing a computer program, wherein the processor is configured to execute the time detection method of the scintillation pulse signal according to any one of claims 12 to 25 when running the computer program.

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