Underwater cable acquisition system

Abstract

The embodiment of the invention discloses an underwater cable acquisition system. In two adjacent digital packets of the same cable of the system, an odd link formed by connecting a plurality of odd-path acquisition stations in series and an even link formed by connecting a plurality of even-path acquisition stations in series are established between a front-stage digital packet and a rear-stage digital packet; when the odd link and the even link normally operate, establishing a normal odd-path instruction path in a first direction and a normal odd-path data path in a second direction in the odd link, and establishing a normal even-path instruction path in the first direction and a normal even-path data path in the second direction in the even link; and when any link is abnormal, an emergency instruction path in a second direction and an emergency data path in a first direction are established between a post-stage normal node and a post-stage digital packet of an abnormal node of the abnormal link, the first direction is consistent with the link direction, and the second direction is opposite to the link direction. According to the scheme, the stability of the underwater cable acquisition system can be improved, and resource waste is avoided.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of exploration technology, and in particular to an underwater cable acquisition system. Background Art

[0002] The cable acquisition system is an important part of marine exploration. The underwater cable acquisition system is the underwater part of the cable system, which is mainly used for the acquisition and transmission of underwater seismic signals.

[0003] Current underwater cable acquisition systems usually use Figure 1 The single link structure shown, that is, two adjacent digital packets (such as Figure 1 The front-stage SCU and the rear-stage SCU shown in FIG. 1 are connected by a collection station (such as Figure 1 Signal transmission is carried out using a single link consisting of FATS) in the CAN bus.

[0004] However, during the implementation process, the inventors found that the prior art has the following defects: when a single-link underwater cable acquisition system in the prior art fails in one or several devices or in the path between devices, the entire link will fail, thereby reducing the stability of the cable acquisition system and causing a waste of system resources. Summary of the invention

[0005] In view of the above problems, embodiments of the present invention are proposed to provide an underwater cable acquisition system that overcomes the above problems or at least partially solves the above problems.

[0006] According to one aspect of an embodiment of the present invention, there is provided an underwater cable acquisition system, the underwater cable acquisition system comprising at least one cable, each cable comprising a plurality of digital packets, wherein in two adjacent digital packets of the same cable, an odd link formed by a plurality of odd-path acquisition stations connected in series is established between a preceding digital packet and a succeeding digital packet, and an even link formed by a plurality of even-path acquisition stations connected in series is established between a preceding digital packet and a succeeding digital packet;

[0007] When the odd link and the even link operate normally, a normal odd path instruction path in a first direction is established in the odd link and a normal odd path data path in a second direction is established in the odd link, and a normal even path instruction path in a first direction is established in the even link and a normal even path data path in a second direction is established in the even link;

[0008] When an abnormality occurs in any link, an emergency command path in the second direction is established between a normal node at a later stage of the abnormal node of the abnormal link and a digital packet at a later stage, and an emergency data path in the first direction is established;

[0009] The first direction is consistent with the link direction, and the second direction is opposite to the link direction.

[0010] In an optional embodiment, the digital packet includes: four forward digital packet ports and four backward digital packet ports;

[0011] The collector includes: two forward collector ports and two backward collector ports;

[0012] The instruction path and data path between the previous digital packet and the next digital packet include: four backward digital packet ports of the previous digital packet, two forward collector ports and two backward collector ports of the odd-path collection station and the even-path collection station, and four forward digital packet ports of the next digital packet.

[0013] In an optional implementation, when the odd link and the even link operate normally, the normal odd link data path and the normal even link data path adopt an interval data frame assembly method;

[0014] When an abnormality occurs in any link, the data path of the normal link adopts the continuous data frame assembly method.

[0015] In an optional implementation, the digital package includes: a high-voltage to medium-voltage module, a medium-voltage to low-voltage module, a control chip, a first medium-voltage MOS transistor, a second medium-voltage MOS transistor, a third medium-voltage MOS transistor, and a fourth medium-voltage MOS transistor;

[0016] The control chip is respectively connected to the gates of the first medium voltage MOS transistor, the second medium voltage MOS transistor, the third medium voltage MOS transistor, and the fourth medium voltage MOS transistor;

[0017] The output end of the high-voltage to medium-voltage module is respectively connected to the source of the first medium-voltage MOS tube, the second medium-voltage MOS tube, the third medium-voltage MOS tube, and the fourth medium-voltage MOS tube, and the output end of the high-voltage to medium-voltage module is connected to the input end of the medium-voltage to low-voltage module, and the output end of the medium-voltage to low-voltage module is connected to the control chip.

[0018] In an optional implementation, the collector includes: a medium voltage to low voltage module, a control chip, a fifth medium voltage MOS tube, and a sixth medium voltage MOS tube;

[0019] Among them, the control chip is respectively connected to the gates of the fifth medium-voltage MOS tube and the sixth medium-voltage MOS tube; the source of the fifth medium-voltage MOS tube and the sixth medium-voltage MOS tube is connected to the input end of the medium-voltage to low-voltage module; the output end of the medium-voltage to low-voltage module is connected to the control chip.

[0020] In an optional implementation, when the link is normal, the preceding digital packet first powers up the odd-path collection stations in the odd-path link step by step with medium voltage, and then powers up the even-path collection stations in the even-path link step by step with medium voltage;

[0021] When an abnormality occurs in any link, the subsequent digital packets are powered up step by step with medium voltage to the collection stations in the abnormal link.

[0022] In an optional implementation, the first type of transmission line between the digital packet and the collection station is superimposed with power signals and instructions, and the second type of transmission line between the digital packet and the collection station is superimposed with power signals and data.

[0023] In an optional implementation, the digital packets are connected to the odd-path high-voltage power lines and the even-path high-voltage power lines respectively;

[0024] When any high-voltage power line is abnormal, the abnormal high-voltage power line is shut down to supply high-voltage power to the digital packets corresponding to the abnormal node.

[0025] In an optional implementation, the digital packet includes an odd-path high-voltage input MOS tube, an even-path high-voltage input MOS tube, an odd-path high-voltage output MOS tube, and an even-path high-voltage output MOS tube;

[0026] After the odd-path high-voltage input MOS tube and / or the even-path high-voltage input MOS tube of the previous-stage digital package are turned on, the high-voltage to medium-voltage module of the previous-stage digital package receives the high-voltage input;

[0027] After the odd-path high-voltage output MOS tube and / or the even-path high-voltage output MOS tube of the previous-stage digital package are turned on, and the odd-path high-voltage input MOS tube and / or the even-path high-voltage input MOS tube of the subsequent-stage digital package are turned on, the high-voltage to medium-voltage module of the subsequent-stage digital package receives the high-voltage input.

[0028] In an optional implementation, the front-stage digital package also detects the characteristic resistance of the rear-stage digital package through the safety loop detection module; when the characteristic resistance exceeds a preset range, the odd-path high-voltage output MOS tube and the even-path high-voltage output MOS tube are turned off.

[0029] According to the underwater cable acquisition system provided by the embodiment of the present invention, in two adjacent digital packets of the same cable of the system, an odd link formed by a plurality of odd-path acquisition stations in series and an even link formed by a plurality of even-path acquisition stations in series are established between the preceding digital packet and the succeeding digital packet; when the odd link and the even link are operating normally, a normal odd-path instruction path in the first direction and a normal odd-path data path in the second direction are established in the odd link, and a normal even-path instruction path in the first direction and a normal even-path data path in the second direction are established in the even link; when an abnormality occurs in any link, an emergency instruction path in the second direction and an emergency data path in the first direction are established between the succeeding normal node of the abnormal node of the abnormal link and the succeeding digital packet, the first direction is consistent with the link direction, and the second direction is opposite to the link direction. The underwater cable acquisition system establishes a parallel odd link and an even link between the preceding digital packet and the succeeding digital packet, and when an abnormality occurs in a certain link, the normal operation of the link between the preceding digital packet and the succeeding digital packet can be guaranteed by switching the direction of the data path and the instruction path in the abnormal link, thereby improving the stability of the underwater cable acquisition system and avoiding waste of resources.

[0030] The above description is only an overview of the technical solution of the embodiment of the present invention. In order to more clearly understand the technical means of the embodiment of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the embodiment of the present invention more obvious and easy to understand, the specific implementation method of the embodiment of the present invention is specifically listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the embodiments of the present invention. Moreover, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0032] Figure 1 A schematic diagram of an underwater cable acquisition system provided by the prior art is shown;

[0033] Figure 2 A schematic diagram of a forward link provided in Embodiment 1 of the present application is shown;

[0034] Figure 3 A reverse link schematic diagram provided in Embodiment 1 of the present application is shown;

[0035] Figure 4 A schematic diagram of an underwater cable acquisition system provided in Embodiment 1 of the present application is shown;

[0036] Figure 5 A schematic diagram of another underwater cable acquisition system provided in Embodiment 1 of the present application is shown;

[0037] Figure 6 A port schematic diagram of a collection station provided in Embodiment 1 of the present application is shown;

[0038] Figure 7 A port schematic diagram of a digital packet provided in Embodiment 1 of the present application is shown;

[0039] Figure 8 A schematic diagram of a data frame assembly method in an underwater cable acquisition system provided in Embodiment 1 of the present application is shown;

[0040] Fig. 9 A schematic diagram of a digital packet structure provided in Embodiment 2 of the present application is shown;

[0041] Fig.10 A schematic diagram of the structure of a collection station provided in Embodiment 2 of the present application is shown;

[0042] Fig.11 A schematic diagram of a medium voltage power supply under normal conditions provided in Embodiment 2 of the present application is shown;

[0043] Fig.12 A schematic diagram of medium voltage power supply under abnormal conditions provided in Embodiment 2 of the present application is shown;

[0044] Fig.13 A schematic diagram of a transmission line provided in Embodiment 2 of the present application is shown;

[0045] Fig.14 Another transmission line schematic diagram provided in the second embodiment of the present application is shown;

[0046] Fig.15 A schematic diagram of transmission line signal separation provided in the second embodiment of the present application is shown;

[0047] Fig.16 A schematic diagram of a high-voltage power transmission architecture provided in Embodiment 3 of the present application is shown;

[0048] Fig.17 A schematic diagram of a digital packet high voltage power supply structure provided in Embodiment 3 of the present application is shown;

[0049] Fig.18 A schematic diagram of a high-voltage power transmission architecture under abnormal conditions provided in Embodiment 3 of the present application is shown;

[0050] Fig.19 A schematic diagram of a safety circuit detection module provided in Embodiment 3 of the present application is shown. DETAILED DESCRIPTION

[0051] The exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present invention and to enable the scope of the present invention to be fully communicated to those skilled in the art.

[0052] Embodiment 1

[0053] Embodiment 1 of the present application provides an underwater cable acquisition system, which can be applied to cable acquisition systems such as submarine cable acquisition systems and towing cable acquisition systems. The underwater cable acquisition system includes multiple digital packages. Specifically, the underwater cable acquisition system usually includes at least one cable, and each cable includes multiple digital packages. Taking the underwater submarine cable acquisition system as an example, it is mainly composed of a deck cable, an extension section, a submarine cable digital package, a submarine cable working section (generally including multiple submarine cable acquisition stations, such as a four-component submarine cable acquisition station), a tail tag, etc.

[0054] The underwater cable equipment is connected in series to form a corresponding link, which can provide a transmission path for instructions, data, power supply, etc., that is, the link can carry instruction paths, data paths and / or power supply paths, etc. Among them, the instruction path direction is taken as the link direction, such as Figure 2 As shown in FIG, when the link direction is consistent with the direction of the submarine cable (the direction in which the deck cable points to the tail mark), the link is a forward link; Figure 3 As shown in FIG. 1 , when the link direction is opposite to the direction of the submarine cable, the link is a reverse link. Also, when the link direction is device A→device B, device A is called the front-end device, and device B is called the back-end device.

[0055] This application mainly optimizes the digital package and acquisition station of the cable in the underwater cable acquisition system. For specific optimization methods, please refer to Figure 4 and Figure 5 .

[0056] In this application, in two adjacent digital packets of the same cable, the digital packet near the starting point of the link direction is called the previous digital packet, and the digital packet near the end point of the link direction is called the next digital packet. An odd link formed by multiple odd-path collection stations connected in series is established between the previous digital packet and the next digital packet, and an even link formed by multiple even-path collection stations connected in series is established between the previous digital packet and the next digital packet. Figure 4 and Figure 5 As shown, two parallel links, namely, an odd link and an even link, are established between the front-stage SCU (front-stage digital package) and the rear-stage SCU (rear-stage digital package). The odd link is formed by the series connection of the acquisition stations FATS1, FATS3, FATS5, and FATS7, and the even link is formed by the series connection of the acquisition stations FATS2, FATS4, FATS6, and FATS8.

[0057] When the odd link and the even link operate normally, a normal odd-path instruction path in the first direction is established in the odd link and a normal odd-path data path in the second direction is established in the odd link, and a normal even-path instruction path in the first direction is established in the even link and a normal even-path data path in the second direction is established in the even link; wherein, the first direction is consistent with the link direction, and the second direction is opposite to the link direction. Thus, instructions are transmitted in parallel in the normal odd-path instruction path and the normal even-path instruction path in the first direction, and data are transmitted in parallel in the normal odd-path data path and the normal even-path data path in the second direction. The instruction path is used for instruction transmission, and the data path is used for the transmission of collected data. Figure 4 As shown, the odd link and the even link carry the instruction path (CMD path) and the data path (DATA path) respectively. The path direction of the normal odd path instruction path and the normal even path instruction path is consistent with the link direction, and the path direction of the normal odd path data path and the normal even path data path is opposite to the link direction. Figure 4 In the figure, the normal odd-path instruction path is the preceding SCU→FATS1→FATS3→FATS5→FATS7→the succeeding SCU, and the normal odd-path data path is the succeeding SCU→FATS7→FATS5→FATS3→FATS1→the preceding SCU; the normal even-path instruction path is the preceding SCU→FATS2→FATS4→FATS6→FATS8→the succeeding SCU, and the normal even-path data path is the succeeding SCU→FATS8→FATS6→FATS4→FATS2→the preceding SCU.

[0058] When an abnormality occurs in any link, an emergency command path in the second direction is established between the rear-stage normal node and the rear-stage digital packet of the abnormal node of the abnormal link, and an emergency data path in the first direction is established. Wherein, the abnormal node is an abnormal device or device connection in the link, the abnormal link is an odd link and / or an even link containing the abnormal node, and the rear-stage normal node of the abnormal node is the next normal acquisition station in the abnormal link along the link direction located at the abnormal node. Thus, in an abnormal situation, the direction of the command path between the rear-stage normal node and the rear-stage digital packet of the abnormal link is opposite to that in a normal situation, and correspondingly, the direction of the data path between the rear-stage normal node and the rear-stage digital packet of the abnormal link is opposite to that in a normal situation. The command path and data path between the front-stage normal node of the abnormal node in the abnormal link (the previous normal acquisition station of the abnormal node along the link direction in the abnormal link) and the front-stage digital packet remain unchanged. The command path and data path of the normal link also remain unchanged. In this case, the emergency command path in the abnormal link is connected with the normal command path in the normal link to form a command path (the first command path in the abnormal case), the emergency data path in the abnormal link is connected with the normal data path in the normal link to form a data path (the first data path in the abnormal case), and the command path between the previous digital packet and the previous normal node in the abnormal link is another command path (the second command path in the abnormal case), and the data path between the previous digital packet and the previous normal node in the abnormal link is another data path (the second data path in the abnormal case).

[0059] During the specific implementation process, if an abnormality occurs in the odd link, an emergency odd path instruction path in the second direction and an emergency odd path data path in the first direction are established between the subsequent normal node of the abnormal node of the odd link and the subsequent digital packet, the emergency odd path instruction path in the second direction in the odd link and the normal even path instruction path in the first direction in the even link form the first instruction path in the abnormal situation, the emergency odd path data path in the first direction in the odd link and the normal even path data path in the second direction in the even link form the first data path in the abnormal situation, the odd path instruction path in the first direction between the previous data packet and the previous normal collection station in the odd link forms the second instruction path in the abnormal situation, and the odd path data path in the second direction between the previous data packet and the previous normal collection station in the odd link forms the second data path in the abnormal situation.

[0060] Correspondingly, if an abnormality occurs in the even link, an emergency even-path instruction path in the second direction and an emergency even-path data path in the first direction are established between the subsequent normal node and the subsequent digital packet of the abnormal node of the even link, the emergency even-path instruction path in the second direction in the even link and the normal odd-path instruction path in the first direction in the odd link form the first instruction path in the abnormal situation, the emergency even-path data path in the first direction in the even link and the normal odd-path data path in the second direction in the odd link form the first data path in the abnormal situation, the even-path instruction path in the first direction between the previous data packet and the previous normal collection station in the even link forms the second instruction path in the abnormal situation, and the even-path data path in the second direction between the previous data packet and the previous normal collection station in the even link forms the second data path in the abnormal situation.

[0061] like Figure 5 As shown, if FATS4 in the even link is abnormal, FATS4 is an abnormal node, the even link is an abnormal link, the odd link is a normal link, FATS2 is a normal node at the previous stage, and FATS6 is a normal node at the next stage. Then a reverse even link is established between the next stage SCU and FATS6, that is, an emergency even path instruction path in the second direction and an emergency even path data path in the first direction are established between the next stage SCU and FATS6. In this abnormal case, the first instruction path is: previous stage SCU→FATS1→FATS3→FATS5→FATS7→next stage SCU→FATS8→FATS6, and the second instruction path is: previous stage SCU→FATS2; the first data path is: FATS6→FATS8→next stage SCU→FATS7→FATS5→FATS3→FATS1→previous stage SCU, and the second data path is: FATS2→previous stage SCU. Therefore, except that the abnormal FATS cannot transmit data, other nodes can still operate normally.

[0062] In an optional implementation, the digital packet includes four forward digital packet ports and four backward digital packet ports; the collector includes two forward collector ports and two backward collector ports; the instruction path and data path between the front-stage digital packet and the rear-stage digital packet include: the four backward digital packet ports of the front-stage digital packet, the two forward collector ports and two backward collector ports of the odd-path collection station and the even-path collection station, and the four forward digital packet ports of the rear-stage digital packet. Among them, the forward port refers to the port for receiving / sending information from the front-stage device, and the backward port refers to the port for receiving / sending information from the rear-stage device.

[0063] Specifically, when the link is normal, two signal channels in the positive link direction and two signal channels in the reverse link direction can be constructed between the previous digital packet and the subsequent digital packet through the port. The two signal channels in the positive link direction are respectively used as normal odd-path instruction channels and normal even-path instruction channels, and the two signal channels in the reverse link direction are respectively used as normal odd-path data channels and normal data instruction channels. Alternatively, the two signal channels in the positive link direction can be respectively used as normal odd-path data channels and normal even-path data channels, and the two signal channels in the reverse link direction can be respectively used as normal odd-path instruction channels and normal even-path instruction channels.

[0064] Therefore, in the actual implementation process, the corresponding channels can be obtained by constructing various signal channels including ports and establishing the mapping relationship between information channels and various instruction channels and data channels. Since the power-on direction of the device is consistent with the link direction, the signal channel composed of the port is established when the acquisition package is powered on, and the forward link direction is determined, and then the port is mapped to the instruction channel or the data channel according to the port data source. For example, if the port receives a signal sent by the upper-level device, indicating that the signal transmission direction is consistent with the power-on direction, then the port is mapped to the instruction channel; if the port receives a signal sent by the lower-level device, indicating that the signal transmission direction is opposite to the power-on direction, then the port is mapped to the data channel.

[0065] When an abnormality occurs in any link, between the normal node and the digital packet of the abnormal node of the abnormal link, the original data path is switched to the command path to obtain the emergency command path, and the original command path is switched to the data path to obtain the emergency data path. Therefore, there is no need to change the signal path, and only the mapping relationship between the signal path, the command path and the data path needs to be changed to quickly obtain the emergency data path / emergency signal path, thereby improving the path switching efficiency in abnormal situations.

[0066] refer to Figure 6 The collection station includes a forward collector port F_TX, a forward collector port F_RX, a backward collector port R_TX, and a backward collector port R_RX. The forward collector port F_RX and the backward collector port R_TX form a channel P1, and the forward collector port F_TX and the backward collector port R_RX form another channel P2. The signal transmission directions of channel P1 and channel P2 are opposite. When channel P1 is an instruction channel and channel P2 is a data channel, it is a forward link; when channel P1 is a data channel and channel P2 is an instruction channel, it is a reverse link.

[0067] refer to Figure 7, the data packet includes forward data packet ports F_TX1, F_TX2, F_RX1, F_RX2 and backward data packet ports R_TX1, R_TX2, R_RX1, R_RX2. Among them, F_RX1, R_TX1, F_TX2, R_TX2 map instruction channels; F_RX2, R_TX2, F_TX1, R_TX1 map data channels. The data packet can set F_RX2 and F_TX2 as reverse ports through configuration.

[0068] In an optional implementation, when the odd link and the even link are operating normally, the normal odd data path and the normal even data path adopt an interval data frame assembly method; when an abnormality occurs in any link, the data path of the normal link adopts a continuous data frame assembly method. Among them, the interval data frame assembly method means that there is at least one data frame length gap between two data frames, and the continuous data frame assembly method means that there is no gap between two data frames. After the link is abnormal, the data in the emergency data path will be transmitted to the data path in the normal link. At this time, due to the use of the continuous data frame assembly method, the data transmission speed can be guaranteed to be the same or close to that under normal conditions of the link. As the physical intersection of dual-link transmission, the digital packet SCU is responsible for balancing the effective load on the two data pipelines. For different scenarios, SCU has different working modes, including: dual-link mode (both the front-end and rear-end links are normal), single-link to dual-link mode (one link in the front-end is faulty, and the rear-end link is normal), dual-link to single-link mode (the front-end link is normal, and one link in the rear-end is faulty), and single-link mode (one link in both the front-end and rear-end is faulty). SCU needs to use different port configurations and different routing methods for each working mode to ensure orderly transmission.

[0069] refer to Figure 8 If the odd link and even link between digital package SCU1 and data package SCU2 are operating normally, the data frame assembly is performed by interval assembly, and a gap of the length of a data frame is spaced between two adjacent data frames; if FATS10 in the even link between digital package SCU2 and data package SCU3 is abnormal, a reverse link (emergency data channel and emergency command channel) is established between acquisition station FATS12 and digital package SCU3. Acquisition station FATS12 transmits seismic data to digital package SCU3 by interval assembly, and digital package SCU3 further transmits data to FATS11. Then, continuous assembly is used in the data channel of FATS11→FATS9→FATS7 to transmit seismic data.

[0070] It can be seen that the underwater cable acquisition system of the embodiment of the present application establishes parallel odd links and even links between the front-stage digital package and the rear-stage digital package. When an abnormality occurs in a link, the normal operation of the link between the front-stage digital package and the rear-stage digital package can be guaranteed by switching the direction of the data path and the instruction path in the abnormal link, thereby improving the stability of the underwater cable acquisition system and avoiding waste of resources.

[0071] Embodiment 2

[0072] Embodiment 2 of the present application provides a link medium-voltage power supply architecture for an underwater cable acquisition system.

[0073] refer to Fig. 9 The digital package SCU includes: a high-voltage to medium-voltage module, a medium-voltage to low-voltage module, a control chip, a first medium-voltage MOS tube, a second medium-voltage MOS tube, a third medium-voltage MOS tube, and a fourth medium-voltage MOS tube. Fig. 9 As shown, the control chip FPGA is respectively connected to the gates of the first medium voltage MOS tube M1, the second medium voltage MOS tube M2, the third medium voltage MOS tube M3, and the fourth medium voltage MOS tube M4, and is used to control the conduction and cutoff of the first medium voltage MOS tube M1, the second medium voltage MOS tube M2, the third medium voltage MOS tube M3, and the fourth medium voltage MOS tube M4. The output end of the high-voltage to medium voltage module is respectively connected to the source of the first medium voltage MOS tube M1, the second medium voltage MOS tube M2, the third medium voltage MOS tube M3, and the fourth medium voltage MOS tube M4, and the output end of the high-voltage to medium voltage module is connected to the input end of the medium voltage to low voltage module. The high-voltage to medium voltage module is used to convert the high voltage input into a low voltage output, for example, converting 600V into 53V; the output end of the medium voltage to low voltage module is connected to the control chip, and is used to convert the medium voltage input into a low voltage output, for example, converting 53V into 5V. The drains of the first medium voltage MOS tube M1, the second medium voltage MOS tube M2, the third medium voltage MOS tube M3, and the fourth medium voltage MOS tube M4 are connected to the collector. It can be seen that the digital package includes four independently controlled MOS switches. When the two forward MOS tubes (M1 and M2) are turned on, the digital package can provide medium voltage to the forward link; when the two backward MOS tubes (M3 and M4) are turned on, the digital package can provide medium voltage to the backward link, thereby realizing bidirectional medium voltage supply.

[0074] refer to Fig.10 The collector includes: a medium voltage to low voltage module, a control chip, a fifth medium voltage MOS tube, and a sixth medium voltage MOS tube. Fig.10As shown, the control chip FPGA is respectively connected to the gates of the fifth medium-voltage MOS tube M5 and the sixth medium-voltage MOS tube M6, and is used to control the conduction and cutoff of the fifth medium-voltage MOS tube M5 and the sixth medium-voltage MOS tube M6; the source of the fifth medium-voltage MOS tube M5 and the sixth medium-voltage MOS tube M6 is connected to the input end of the medium-voltage to low-voltage module; the output end of the medium-voltage to low-voltage module is connected to the control chip, and the medium-voltage to low-voltage module can convert the medium-voltage input into a low-voltage output and provide it to the control chip, for example, converting a 53V voltage into a 5V voltage. It can be seen from this that the acquisition station can realize adaptive bidirectional power supply. When only M5 is turned on, the front-stage device can provide a medium-voltage power supply, and when only M6 is turned on, the rear-stage device can provide a medium-voltage power supply. When M5 and M6 are turned on at the same time, the acquisition station outputs power to the rear stage, and the input voltage drop can also be reduced.

[0075] In an optional implementation, in order to ensure the accurate operation of the cable, this implementation can adopt the following medium-voltage power supply method: when the link is normal, the front-stage digital packet first powers on the odd-path collection stations in the odd-path link step by step with medium voltage, and then powers on the even-path collection stations in the even-path link step by step with medium voltage; after an abnormality occurs in any link, the rear-stage digital packet powers on the collection stations in the abnormal link step by step with medium voltage.

[0076] refer to Fig.11 Under normal conditions of dual links, the high voltage power supply 600V is converted into a 53V medium voltage power supply through a high voltage to medium voltage module and provided to the front-stage SCU control chip. The control chip of the front-stage SCU first turns on the MOS tube in the rear odd link and the forward MOS tube of the acquisition station 3, thereby powering on the medium voltage of the acquisition station 3. After the power-on of the acquisition station 3 is completed, the rear MOS tube of the acquisition station 3 and the forward MOS tube of the acquisition station 5 are turned on, thereby powering on the medium voltage of the acquisition station 5, and so on and so forth to complete the medium voltage power-on of the odd link; then the front-stage SCU turns on the MOS tube of the rear even link and the forward MOS tube of the acquisition station 4, thereby powering on the medium voltage of the acquisition station 4. After the medium voltage of the acquisition station 4 is powered on, the rear MOS tube of the acquisition station 4 and the forward MOS tube of the acquisition station 6 are turned on, thereby powering on the medium voltage of the acquisition station 6, and so on and so forth to complete the step-by-step power-on of the even link. Then the high voltage input of the rear-stage SCU is turned on to supply power to the rear-stage SCU.

[0077] refer to Fig.12 When the collection station 6 in the even link is abnormal, the forward even link MOS tube of the rear SCU is turned on, so that the rear SCU supplies medium voltage power to the collection station 8.

[0078] In an optional implementation, the embodiment of the present application requires instruction transmission, data transmission and power transmission between the digital packet and the collection station. Fig.13 The architecture shown in the figure requires eight pairs of twisted pairs to connect one SCU to two FATSs, which requires a large number of transmission lines. In order to achieve transmission optimization, this implementation adopts Fig.14 The power transmission multiplexing architecture shown is the first type of transmission line between the digital packet and the acquisition station (corresponding to Fig.14 The black transmission line) is superimposed with power signals and instructions, and the second type of transmission line between the digital packet and the acquisition station (corresponding to Fig.14 Gray transmission lines) are superimposed with power signals and data, so that only four pairs of twisted pairs are needed between a digital packet and two acquisition stations, reducing the number of transmission lines used in the cable body, increasing the redundancy of the cable body core wires, and improving the maintainability of the cable body. Specifically, Fig.15 As shown, in this embodiment, the DC component on the transmission line is isolated by capacitors, and the AC component on the transmission line is isolated by differential mode inductors. Fig.15 As shown, the upper-level device injects the power signal into the two pairs of transmission lines through the common-mode inductor and the differential-mode inductor, and the lower-level device extracts the power signal from the two pairs of transmission lines through the differential-mode inductor and the common-mode inductor.

[0079] It can be seen that in the medium-voltage power supply architecture of the underwater cable acquisition system provided in the embodiment of the present application, the four medium-voltage MOS tubes independently controlled by the digital packet and the two medium-voltage MOS tubes independently controlled by the collector can flexibly realize medium-voltage power-on and signal transmission in any direction, and reduce the number of transmission lines by multiplexing the transmission lines of power supply and command / data signals, thereby saving costs.

[0080] Embodiment 3

[0081] Embodiment 3 of the present application provides a high-voltage power supply architecture for an underwater cable acquisition system.

[0082] The underwater cable collection system is laid on the seabed. In a complex working environment, the cable body may be scratched, or the dragging force may be too large, causing damage and leakage. If the single-channel high-voltage power supply architecture in the prior art is adopted, it needs to be recycled and replaced in this case, which greatly affects the efficiency of the operation. The embodiment of the present application provides a dual-link high-voltage power supply architecture to solve this technical problem.

[0083] refer to Fig.16 , the digital packets in the embodiment of the present application are respectively connected to the odd-path high-voltage power lines (corresponding to Fig.16 Black solid line) and even-circuit high-voltage power line (corresponding Fig.16 Black dotted line). Specifically, after the high-voltage power supply is connected to the junction box, two independent high-voltage power lines are led out of the junction box, namely the odd-path high-voltage power line and the even-path high-voltage power line. The two high-voltage power lines are controllably converged and separated in the digital package. The high-voltage line is divided into independent small segments by the switch in the digital package, and a certain faulty small segment is isolated by controlling the switch of the digital package to realize flexible configuration of the high-voltage power supply.

[0084] refer to Fig.17, the digital package includes odd-path high-voltage input MOS tubes M7 and M9, even-path high-voltage input MOS tubes M8 and M10, odd-path high-voltage output MOS tubes M11 and M13, and even-path high-voltage output MOS tubes M12 and M14. And the gates of M7-M14 are all connected to the control chip FPGA of the digital package, and the control chip FPGA can control the conduction and cutoff of each high-voltage input / output MOS tube. During the power supply process, after the odd-path high-voltage input MOS tube and / or the even-path high-voltage input MOS tube of the previous digital package is turned on, the high-voltage current is directed to the high-voltage to medium-voltage module of the previous digital package, so that the high-voltage to medium-voltage module receives the high-voltage input and converts it into a medium-voltage output to provide to the local power supply, while the odd-path / even-path high-voltage output MOS tube is not turned on, and the organization current is conducted to the next-stage digital package. After the odd-path high-voltage output MOS tube and / or the even-path high-voltage output MOS tube of the previous-stage digital package are turned on, and the odd-path high-voltage input MOS tube and / or the even-path high-voltage input MOS tube of the subsequent-stage digital package are turned on, the high-voltage power supply is input into the subsequent-stage digital package, so that the high-voltage to medium-voltage module of the subsequent-stage digital package receives the high-voltage input.

[0085] refer to Fig.18 When any high-voltage power line is abnormal, the abnormal high-voltage power line is turned off to supply high-voltage power to the digital packet corresponding to the abnormal node. As shown in 18, when an abnormality occurs in the high-voltage odd circuit H, the fault bypass is achieved by turning off the MOS tube (black dotted box) adjacent to the fault point, and a single high-voltage ( Fig.18 In order to adopt high-voltage dual circuit (power supply), at the same time, the dual-circuit high-voltage power supply structure can be restored at the next digital packet after the fault point.

[0086] In an optional implementation, in actual application scenarios, the high voltage power supply usually reaches 600V. In order to ensure the safety of personnel and equipment, a safety circuit detection module is introduced in this implementation to detect whether the subsequent equipment is safe. Fig.19 The front-stage digital package also detects the characteristic resistance of the rear-stage digital package through the safety circuit detection module; when the characteristic resistance exceeds the preset range, the odd-path high-voltage output MOS tube and the even-path high-voltage output MOS tube are turned off.

[0087] It can be seen that the dual-link high-voltage power supply architecture of the underwater cable acquisition system provided in the embodiment of the present application can terminate the power supply of a certain high-voltage power supply link to the corresponding digital packet when an abnormality occurs in a certain high-voltage power supply node, while the other high-voltage power supply link can still supply power to the digital packet, thereby improving the stability of the high-voltage power supply of the underwater cable acquisition system, reducing the frequency of recovery and replacement, and thus reducing maintenance costs.

[0088] It should be noted that, in the present invention, relational terms such as first and second, etc. are merely used to distinguish one entity or operation from another entity or operation, and do not represent any actual relationship or order between the entities or operations.

[0089] The illustrations provided by the present invention are only used to schematically illustrate the basic concept of the present invention. The illustrations only show the components related to the present invention rather than being drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0090] The "connection" in the present invention includes both direct connection and indirect connection, such as connection through some active devices, passive devices or electrically conductive media; it may also include connection through other active devices or passive devices on the basis of achieving the same or similar functional purposes as is well known to those skilled in the art, such as connection through circuits or components such as switches and follower circuits.

[0091] The description and application of the present invention here are illustrative, and it is not intended to limit the scope of the present invention to the above-mentioned embodiments. The effects or advantages involved in the embodiments may not be embodied in the embodiments due to interference from various factors, and the description of the effects or advantages is not used to limit the embodiments. The deformation and change of the embodiments disclosed here are possible, and the replacement of the embodiments and the various equivalent parts are well known to those of ordinary skill in the art. It should be clear to those skilled in the art that the present invention can be implemented in other forms, structures, arrangements, proportions, and with other components, materials and parts without departing from the spirit or essential features of the present invention. Other deformations and changes can be made to the embodiments disclosed here without departing from the scope and spirit of the present invention.

Claims

1. An underwater cable acquisition system, comprising at least one cable, each cable comprising a plurality of digital packets, characterized in that: In two adjacent digital packets of the same cable, an odd link formed by a plurality of odd-path collection stations connected in series is established between the preceding digital packet and the succeeding digital packet, and an even link formed by a plurality of even-path collection stations connected in series is established between the preceding digital packet and the succeeding digital packet; When the odd link and the even link operate normally, a normal odd path instruction path in a first direction is established in the odd link and a normal odd path data path in a second direction is established in the odd link, and a normal even path instruction path in a first direction is established in the even link and a normal even path data path in a second direction is established in the even link; When an abnormality occurs in any link, an emergency command path in the second direction is established between a normal node at a later stage of the abnormal node of the abnormal link and a digital packet at a later stage, and an emergency data path in the first direction is established; The first direction is consistent with the link direction, and the second direction is opposite to the link direction.

2. The underwater cable acquisition system according to claim 1, characterized in that: The digital packet includes: four forward digital packet ports and four backward digital packet ports; The collector includes: two forward collector ports and two backward collector ports; The instruction path and data path between the previous digital packet and the next digital packet include: four backward digital packet ports of the previous digital packet, two forward collector ports and two backward collector ports of the odd-path collection station and the even-path collection station, and four forward digital packet ports of the next digital packet.

3. The underwater cable acquisition system according to claim 1, characterized in that: When the odd link and the even link are operating normally, the normal odd link data path and the normal even link data path adopt the interval data frame assembly mode; When an abnormality occurs in any link, the data path of the normal link adopts the continuous data frame assembly method.

4. The underwater cable acquisition system according to any one of claims 1 to 3, characterized in that: The digital package includes: a high-voltage to medium-voltage module, a medium-voltage to low-voltage module, a control chip, a first medium-voltage MOS tube, a second medium-voltage MOS tube, a third medium-voltage MOS tube, and a fourth medium-voltage MOS tube; The control chip is respectively connected to the gates of the first medium voltage MOS transistor, the second medium voltage MOS transistor, the third medium voltage MOS transistor, and the fourth medium voltage MOS transistor; The output end of the high-voltage to medium-voltage module is respectively connected to the source of the first medium-voltage MOS tube, the second medium-voltage MOS tube, the third medium-voltage MOS tube, and the fourth medium-voltage MOS tube, and the output end of the high-voltage to medium-voltage module is connected to the input end of the medium-voltage to low-voltage module, and the output end of the medium-voltage to low-voltage module is connected to the control chip.

5. The underwater cable acquisition system according to claim 4, characterized in that: The collector includes: a medium voltage to low voltage module, a control chip, a fifth medium voltage MOS tube, and a sixth medium voltage MOS tube; Among them, the control chip is respectively connected to the gates of the fifth medium-voltage MOS tube and the sixth medium-voltage MOS tube; the source of the fifth medium-voltage MOS tube and the sixth medium-voltage MOS tube is connected to the input end of the medium-voltage to low-voltage module; the output end of the medium-voltage to low-voltage module is connected to the control chip.

6. The underwater cable acquisition system according to claim 5, characterized in that: When the link is normal, the preceding digital packet first powers up the odd-path collection stations in the odd-path link step by step with medium voltage, and then powers up the even-path collection stations in the even-path link step by step with medium voltage; When an abnormality occurs in any link, the subsequent digital packets are powered up step by step with medium voltage to the collection stations in the abnormal link.

7. The underwater cable acquisition system according to claim 5, characterized in that: The first type of transmission line between the digital packet and the collection station is superimposed with power signals and instructions, and the second type of transmission line between the digital packet and the collection station is superimposed with power signals and data.

8. The underwater cable acquisition system according to claim 5, characterized in that: The digital package is connected to the odd-path high-voltage power line and the even-path high-voltage power line respectively; When any high-voltage power line is abnormal, the abnormal high-voltage power line is shut down to supply high-voltage power to the digital packets corresponding to the abnormal node.

9. The underwater cable acquisition system according to claim 8, characterized in that: The digital package includes odd-path high-voltage input MOS tube, even-path high-voltage input MOS tube, odd-path high-voltage output MOS tube, even-path high-voltage output MOS tube; After the odd-path high-voltage input MOS tube and / or the even-path high-voltage input MOS tube of the previous-stage digital package are turned on, the high-voltage to medium-voltage module of the previous-stage digital package receives the high-voltage input; After the odd-path high-voltage output MOS tube and / or the even-path high-voltage output MOS tube of the previous-stage digital package are turned on, and the odd-path high-voltage input MOS tube and / or the even-path high-voltage input MOS tube of the subsequent-stage digital package are turned on, the high-voltage to medium-voltage module of the subsequent-stage digital package receives the high-voltage input.

10. The underwater cable acquisition system according to claim 9, characterized in that: The front-stage digital packet detects the characteristic resistance of the rear-stage digital packet through the safety circuit detection module; When the characteristic resistance exceeds a preset range, the odd-path high-voltage output MOS tube and the even-path high-voltage output MOS tube are turned off.

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