Integrated design data conversion system

Abstract

The invention discloses an integrated design data conversion system which comprises a system control module and a power management module, the system control module adopts a cold backup design, 1553B bus communication and data interaction are achieved, RS422 communication and LVDS communication control of carrying equipment are achieved, a main control panel and a backup control panel are completely the same, and the main control panel and the backup control panel are completely the same. A signal backup relation is formed through kneading of the bottom plate; the power management module distributes power to the carrying equipment and supplies power to the system control module; the system control module and the power management module carry out information interaction through an internal connector. According to the invention, the light and small design is realized, and the reliability and safety problems of carrying equipment and a communication interface of the whole device are solved.

Description

Technical Field

[0001] The invention relates to an integrated design data conversion system, belonging to the technical field of spacecraft data management. Background Art

[0002] Since the entire structure of existing spacecraft has been completed long ago, according to the functional layout of the equipment, the space available for new equipment is very small. The newly added data conversion system has strict requirements on volume and weight. At the same time, if an abnormal short circuit occurs in the onboard equipment, it must not cause any impact on the bus and other power supply equipment. This places high demands on the reliability and safety of the power supply interface and communication interface between the onboard equipment and the entire device.

[0003] The shortcomings of the prior art are:

[0004] 1553B bus communication control usually uses CPU as the core of the control system. This control method requires external SRAM, Flash and other memories to store data and programs, and external FPGA to realize RS422 and LVDS communication of the mounted equipment. This design method is obviously not applicable when the volume and weight requirements are so strict, and it cannot meet the requirements of lightweight and miniaturized design.

[0005] The power supply of the distribution circuit is generally distributed by traditional large relays. There are 7 distribution routes (5 primary bus power supplies + 2 thermal control power supplies), which has a large area and does not meet the requirements of lightweight and miniaturized design.

[0006] Generally, busbar protection strategies are primary protection strategies, which cannot meet the reliability and safety issues of the power supply interface between the mounted equipment and the whole device. Summary of the invention

[0007] The technical problem solved by the present invention is: to overcome the shortcomings of the prior art and provide an integrated integrated design data conversion system to better meet the task requirements of limited layout space, high power supply reliability and safety requirements, and communication isolation in the field of deep space data management.

[0008] The technical solution of the present invention is: an integrated design data conversion system, including a system control module and a power management module, wherein:

[0009] The system control module adopts cold backup design to realize 1553B bus communication and data interaction, RS422 communication and LVDS communication control of the mounted equipment. The main and backup control boards are exactly the same, and the signal backup relationship is formed through the bottom board.

[0010] The power management module supplies power to the onboard equipment power distribution and system control module;

[0011] The system control module and the power management module exchange information through the internal connector.

[0012] Preferably, the system control module includes: 1553B bus interface circuit, RS422 differential output conversion circuit, RS422 differential input conversion circuit, LVDS differential input conversion circuit, LVDS differential output conversion circuit, FPGA, configuration refresh circuit, program memory, reset circuit, enable control circuit, power conversion circuit;

[0013] The configuration refresh circuit is connected to the program memory to read the configuration data therefrom, receives the power-on reset signal of the reset circuit, performs global configuration and timing dynamic refresh on the FPGA, and outputs the reset signal to the FPGA and the enable control circuit; the enable control circuit is also connected to the RS422 differential output conversion circuit and the LVDS differential output conversion circuit, and outputs the enable control signal to them;

[0014] The 1553B bus interface circuit connects to the FPGA and exchanges information on the one hand, and sends 1553B bus signals to the 1553B bus device end on the other hand;

[0015] The RS422 differential output conversion circuit receives signals from the FPGA and the enable control circuit, and sends an RS422 output signal to the mounted device;

[0016] The RS422 differential input conversion circuit receives the RS422 input signal sent by the onboard device and outputs a single-ended signal to the FPGA;

[0017] The LVDS differential output conversion circuit receives signals from the FPGA and the enable control circuit, and sends an LVDS three-wire output signal to the LVDS receiving device;

[0018] The LVDS differential input conversion circuit receives the LVDS three-wire input signal of the mounted device and outputs a single-ended signal to the FPGA;

[0019] The RS422 differential output conversion circuit, the RS422 differential input conversion circuit, the LVDS differential output conversion circuit, and the LVDS differential input conversion circuit simultaneously forward the signal to the internal connector;

[0020] The power conversion circuit receives the 5V power supply output by the power management module to the internal connector and outputs +3.3V, +1.8V, and +1.5V power supplies to the FPGA.

[0021] Preferably, the 1553B bus interface circuit includes an isolation transformer, a bus controller, and a voltage conversion circuit. The 1553B bus is connected to the bus controller via an isolation transformer, and the signal output by the bus controller is converted into a voltage acceptable to the FPGA via the voltage conversion circuit.

[0022] Preferably, the communication interface of the mounted device adopts RS422 and LVDS communication, and the FPGA in the system control module converts the 1553B bus data into RS422 data and then transmits it to the mounted device, or the FPGA in the system control module converts the RS422 and LVDS data of the mounted device into 1553B bus data or other data, and then transmits it to the whole device, thereby realizing flexible conversion between different types of bus communication protocols between the platform and the mounted devices, and at the same time, performing priority and arbitration management on the communication of multiple channels of multiple mounted devices, and formulating different time slice communication strategies according to the characteristics of the mounted devices.

[0023] Preferably, after the device is powered on, the reset circuit resets the configuration refresh circuit, and after the configuration refresh circuit is reset, the FPGA chip begins to be configured. After the configuration is completed, the configuration refresh circuit outputs a reset signal to reset the FPGA, and at the same time, the power-on reset signal output by the reset circuit and the reset signal output by the configuration refresh circuit are output to the enable control circuit;

[0024] The enable control circuit is also connected to the RS422 differential output conversion circuit, outputs an enable control signal to it, performs enable control during power-on and FPGA configuration, and prevents the RS422 differential output conversion circuit from sending unexpected data during power-on and FPGA configuration; and is simultaneously connected to the LVDS differential output conversion circuit, outputs an enable control signal to it, performs enable control during power-on and FPGA configuration, and prevents the LVDS differential output conversion circuit from sending unexpected data during power-on and FPGA configuration.

[0025] Preferably, the power management module includes two categories:

[0026] The first category is: after the primary bus input passes through: primary protection circuit, surge suppression circuit, switch control circuit, filter and power conversion, it outputs the required 5V power to the system control module;

[0027] The second category is: after the primary bus input passes through: the first-level protection circuit, surge suppression circuit, switch control circuit, and second-level protection circuit in sequence, it supplies power to the onboard equipment and its thermal control equipment.

[0028] Preferably, in the power management module:

[0029] The surge suppression circuit includes MOS tube, resistor and capacitor, forming a resistance-capacitance circuit around the MOS tube. By adjusting the resistance and capacitance values, the surge can be suppressed within a safe range.

[0030] The switch control circuit uses a MOS tube combined with a small relay to complete the power distribution output and prohibit output by controlling the switch of the MOS tube;

[0031] The switch control circuit and the surge suppression circuit share the MOS tube.

[0032] Preferably, both the primary protection circuit and the secondary protection circuit adopt an unbalanced design to protect the busbar safety when the equipment is short-circuited. Specifically:

[0033] In the protection circuit, the fuse specifications and resistance values ​​are selected according to the current, and the fuse adopts a two-stage unbalanced design. In order to increase reliability, the rated current of the fuse is reduced: the second-stage fuse is selected to be a fuse that is twice greater than the bus current, and the rated current of the first-stage fuse is greater than the rated current of the second-stage fuse, so that when the onboard equipment is short-circuited, even if the second-stage fuse burns out, it will not affect the first-stage fuse.

[0034] Compared with the prior art, the present invention has the following advantages:

[0035] (1) The present invention designs an integrated design data conversion system, which integrates the control and power distribution functions into a single machine, reducing one single machine and solving the problem of limited layout space of the whole device;

[0036] (2) The present invention adopts a busbar multiple protection strategy design to solve the reliability and safety issues of the power supply interface between the mounted equipment and the whole device, and realizes a dual protection mechanism for the power supply of the model mounted equipment. If an abnormal short circuit occurs in the mounted equipment, it will not cause any impact on the busbar and other power supply equipment;

[0037] (3) The present invention adopts a communication interface conversion design. The whole device communicates using 1553B bus communication, while the onboard device interface communicates using RS422, LVDS, etc., which solves the reliability and safety issues of the communication interface between the onboard device and the whole device, and realizes the conversion of the communication interface of the onboard device. If an abnormality occurs in the communication interface of the onboard device, it will not cause any impact on other devices of the whole device.

[0038] (4) The present invention adopts a miniaturized design. Compared with the existing technology, the power distribution circuit power supply is improved from the traditional large relay power distribution to the MOS tube power distribution, which saves about 1 / 3 of the area compared with the traditional large relay power distribution; the communication uses FPGA to independently supervise the 1553B bus communication and system control, which effectively reduces the volume by 1 / 3 compared with the traditional CPU control architecture, realizing a lightweight and miniaturized design;

[0039] (5) The present invention can be used to cooperate with other mounted devices in the future to achieve dual protection of the interface between the mounted devices and data implementation management. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 Design block diagram for the integrated data conversion system of the present invention;

[0041] Figure 2 Design a block diagram for the system control module of the present invention;

[0042] Figure 3 A block diagram of the power management module design of the present invention. DETAILED DESCRIPTION

[0043] The technical solution of the present invention is:

[0044] The control function and power distribution function of the mounted equipment are integrated into a single machine, which is divided into a system control module and a power management module according to functional requirements. The system control module adopts a cold backup design to realize 1553B bus communication and data interaction, and realize RS422 communication and LVDS communication control of the mounted equipment. The main and backup control boards are exactly the same, and a signal backup relationship is formed through the bottom plate; the power management module realizes the power distribution of the mounted equipment and the power conversion function of the system control module.

[0045] The system control module consists of a 1553B bus interface circuit, an RS422 differential output conversion circuit, an RS422 differential input conversion circuit, an LVDS differential input conversion circuit, an LVDS differential output conversion circuit, an FPGA, a configuration refresh circuit, a program memory, a reset circuit, an enable control circuit, and a power conversion circuit. Figure 2 The specific implementation steps are as follows:

[0046] 1. 1553B bus interface circuit

[0047] The whole device adopts 1553B bus interface, and the 1553B bus interface circuit realizes the data transmission function between the whole device and the data conversion system.

[0048] 2. FPGA

[0049] FPGA is the core of the whole circuit, realizing 1553B bus management, RS422 bus management, LVDS bus management and communication control functions.

[0050] 3.Configure refresh circuit

[0051] The configuration refresh circuit is responsible for global configuration and dynamic refresh of the FPGA.

[0052] 4. Program memory

[0053] The program memory is used to store FPGA program files.

[0054] 5. Reset circuit

[0055] Generate a power-on reset signal to provide a reset signal for the configuration refresh circuit and the enable control circuit.

[0056] 6. Enable control circuit

[0057] Generate LVDS and RS422 transmit interface chip enable control signal.

[0058] 7. RS422 differential output conversion

[0059] Convert FPGA single-ended output signal into RS422 differential output signal.

[0060] 8. RS422 differential input conversion

[0061] Convert RS422 differential input signal to FPGA single-ended input signal.

[0062] 9. LVDS differential output conversion

[0063] Convert the FPGA single-ended output signal to a LVDS differential output signal.

[0064] 10. LVDS differential input conversion

[0065] Convert LVDS differential input signals to FPGA single-ended input signals.

[0066] 11. Power conversion circuit

[0067] The power conversion circuit converts the input 5V power supply into the +3.3V, +1.8V, and +1.5V power supplies required by the entire FPGA.

[0068] The power management module consists of two parts:

[0069] One part is to generate the required 5V power supply for the system control module, which consists of a primary protection circuit, a surge suppression circuit + switch control, a filter, and a DC / DC+5V circuit;

[0070] One part is to power the onboard equipment and its thermal control equipment. The onboard equipment and its thermal control power supply circuit consists of a primary protection circuit, a surge suppression circuit + switch control, and a secondary protection circuit. See the block diagram Figure 3 The specific implementation steps are as follows:

[0071] 1. Primary protection circuit

[0072] The primary protection circuit adopts an unbalanced design to protect the busbar safety when the equipment is short-circuited.

[0073] 2. Surge suppression + switch control

[0074] The primary bus input enters the surge suppression + switch control circuit after passing through the first-level protection circuit. The surge suppression circuit is composed of MOS tubes, resistors and capacitors. The switch control circuit abandons the traditional large relay control method and is improved to MOS tube + small switch. The switch control circuit and surge suppression circuit share the MOS tube.

[0075] 3. Filtering + power conversion

[0076] The filter + power conversion circuit converts the bus power into the +5V power required by the system control module.

[0077] 4. Secondary protection circuit

[0078] The secondary protection circuit adopts an unbalanced design to protect the busbar safety when the equipment is short-circuited.

[0079] The following is a further description with reference to the accompanying drawings.

[0080] By summarizing and analyzing the functional requirements, the integrated design data conversion system is divided into a system control module and a power management module. The functional block diagram is shown in Figure 1 Among them, the system control module adopts a cold backup design to realize 1553B bus communication and data interaction, RS422 communication and LVDS communication control. The two control boards are exactly the same, and a signal backup relationship is formed through the bottom plate. The power management module provides the required power for the data conversion system control circuit, and also provides primary power for the three onboard devices and the thermal control of the onboard devices.

[0081] First, the system control module design is explained.

[0082] The whole device adopts 1553B bus interface. The 1553B bus interface circuit includes isolation transformer, bus controller and voltage conversion circuit. The 1553B bus is connected to the bus controller through isolation transformer to reduce signal reflection, improve bus input impedance and common mode rejection ratio, and realize DC isolation. The bus controller realizes 1553B bus interface control, and the signal output by the bus controller is converted into acceptable voltage of FPGA through voltage conversion circuit.

[0083] FPGA is the core of the control system. The system control module cancels the commonly used CPU and its peripheral memory architecture, uses the design method of CPU controlling 1553B bus communication, and uses FPGA to independently supervise 1553B bus communication and data conversion. The functional block diagram is shown in Figure 2. The data conversion system needs to communicate with the whole device 1553B bus and multiple onboard devices for RS422 and LVDS communication. The CPU control 1553B bus technology is mature and has been applied to multiple models. However, if the CPU is used as the core of the control system, the CPU not only needs external SRAM, Flash and other memories, but also needs to use FPGA to realize RS422 and LVDS communication control with the onboard devices. Using FPGA alone as the core of the control system can also complete the 1553B bus communication function and data conversion function. Compared with the CPU as the core of the control system, the CPU system and the CPU system peripheral SRAM, Flash and other memories are reduced, and the volume is reduced by 1 / 3. The weight of the data conversion system is only 2.4kg, realizing a lightweight and miniaturized design. Data conversion between the 1553B bus interface circuit and the RS422 input-output conversion circuit and the LVDS input-output conversion circuit is realized through FPGA, and flexible conversion between different types of bus communication protocols between the platform and the mounted devices is realized. Priority and arbitration management is performed on the communications of multiple channels of multiple mounted devices. Different time-slice communication strategies are formulated according to the characteristics of the mounted devices. A series of reliability measures such as timeout and verification and data anti-collision design are adopted to improve the communication reliability and interface expansion between the mounted devices and the platform devices.

[0084] In order to deal with the single particle upset problem of SRAM-based FPGA in space, a global configuration and dynamic refresh circuit is designed. The configuration refresh circuit reads the configuration data from the program memory, performs global configuration and timed dynamic refresh on the FPGA, supports automatic reconfiguration on power-on and abnormal reconfiguration, resets the FPGA after loading is completed, and outputs a reset signal to the enable control circuit.

[0085] After the device is powered on, the reset circuit resets the configuration refresh circuit. After the configuration refresh circuit is reset, the FPGA chip begins to be configured. After the configuration is completed, the configuration refresh circuit outputs a reset signal to reset the FPGA. At the same time, the power-on reset signal and the reset signal output by the configuration refresh circuit are output to the enable control circuit. The enable control circuit performs enable control on the RS422 differential output conversion circuit and the LVDS differential output conversion circuit during power-on and FPGA configuration to prevent unexpected data from being sent out during power-on and FPGA configuration.

[0086] The communication of the mounted device is not directly connected to the whole device. The communication interface of the mounted device uses RS422, LVDS and other methods to communicate. The FPGA in the system control module converts the 1553B bus data into RS422 data and then transmits it to the mounted device, or the FPGA in the system control module converts the RS422 and LVDS data of the mounted device into 1553B bus data or other data, and then transmits it to the whole device, which not only realizes the data conversion bridge, but also plays the role of communication isolation. The RS422 and LVDS differential input and output conversion circuit is the RS422 and LVDS interface conversion circuit.

[0087] The power conversion converts the input 5V power supply into the +3.3V, +1.8V, and +1.5V power supplies required by the FPGA in the system control.

[0088] Then the power management module design is explained.

[0089] The power management module design block diagram is shown in Figure 3 , first explain the protection circuit design. The protection circuit design method is consistent, both use the unbalanced design method, the difference is that the fuse specifications and resistor values ​​are selected according to the current. Take the power supply design of the largest power-consuming device 1 as an example. The power consumption of the device 1 is about 35W, the bus voltage is 30V, and the bus current is 1.16A. The protection fuse adopts a two-stage unbalanced design. In order to increase reliability, the rated current of the fuse is reduced. The second-stage fuse uses a fuse that is twice the bus current, so a 3A fuse is selected, which can meet the reduction and effectively protect the bus; the first stage uses a 5A fuse. If there is a short circuit in the device 1, due to the large rated current capacity of the first-stage fuse and the small rated current capacity of the second-stage fuse, the second-stage fuse will burn out, which will not affect the first-stage fuse. At the same time, the first-stage fuse plays a role in protecting the entire power supply path. The double bus protection method of the data conversion system can effectively protect the safety of the entire bus power supply and provide power supply reliability.

[0090] In order to ensure the reliability of power on and off of the mounted equipment, a two-series and two-parallel redundant control method is required for the power supply of the mounted equipment. In order to ensure the reliability of the thermal control power supply of the mounted equipment, a two-parallel redundant control method is required for the thermal control power supply of the mounted equipment. There are 7 power distribution channels (5 primary bus power supply channels + 2 thermal control power supply channels), and a total of 20 large relays are required. Since the traditional large relays are too large, they obviously do not meet the requirements under such strict volume requirements. Therefore, the switch control circuit is improved to a MOS tube + small relay method. By controlling the switch of the MOS tube, the power distribution output and output prohibition are realized. The MOS tube greatly reduces the layout space of the printed circuit board. Compared with the traditional large relay power distribution, the area is saved by about 1 / 3, realizing a lightweight and miniaturized design; the small relay adopts the JMW-270M-027M / 1 / K relay with a TO-5 small package, with an area of ​​Ф8.51mm×7.11mm, and the occupied area is only 56.8mm 2 , while traditional large relays, such as the commonly used 2JB5-1-28B, have an area of ​​16.3mm × 20.6mm and occupy an area of ​​335.78mm 2 The small relay saves PCB layout space to a great extent; at the same time, a resistor-capacitor circuit is added around the MOS tube to realize circuit soft start, and the surge is suppressed within a safe range by adjusting the resistor-capacitor value.

[0091] The filter + power conversion circuit selects a matching filter and a power conversion module according to the current demand of the system control module to provide a 5V power supply for the system control module.

[0092] An integrated integrated design data conversion unit of the present invention realizes the reliability design of data transmission control and power supply and distribution of the mounted equipment, which mainly includes two aspects: first, the mounted power supply is not directly connected to the whole device, and the data conversion unit is used to realize the connection to the whole device power supply and indirectly output, and the bus multiple protection strategy design is adopted to solve the reliability and safety problems of the power supply interface between the mounted equipment and the whole device, and realize the model load power supply dual protection mechanism. If an abnormal short circuit occurs in the mounted equipment, it will not cause any impact on the bus and other power supply equipment; second, the mounted equipment communication is not directly connected to the whole device, the whole device adopts 1553B bus communication, and the mounted equipment communication interface adopts RS422, LVDS and other modes of communication. The data conversion unit converts the 1553B bus instruction into RS422 instruction and then transmits it to the mounted equipment. The data conversion unit converts the RS422 and LVDS data of the mounted equipment into 1553B bus data or other data, and then transmits it to the whole device, which not only realizes the data conversion bridge, but also plays the role of communication isolation.

[0093] The power supply and communication conversion design not only ensures the safety of the power supply and distribution of the whole device, but also ensures the safety of the communication line. No matter if there is a power supply short circuit or communication abnormality in the mounted device, it will not cause abnormality of the whole device. At the same time, abnormality of a single mounted device will not affect the normal operation of other mounted devices. It can be used for subsequent cooperation with other mounted devices to achieve dual protection of the interface between the mounted devices, data management protection, etc.

[0094] The contents not described in detail in the specification of the present invention belong to the prior art known to the professional and technical personnel in this field.

Claims

1. An integrated design data conversion system, characterized in that include: System control module and power management module, including: The system control module adopts cold backup design to realize 1553B bus communication and data interaction, RS422 communication and LVDS communication control of the mounted equipment. The main and backup control boards are exactly the same, and the signal backup relationship is formed through the bottom board. The power management module supplies power to the onboard equipment power distribution and system control module; The system control module and the power management module exchange information through the internal connector.

2. The integrated design data conversion system according to claim 1, characterized in that: The system control module includes: 1553B bus interface circuit, RS422 differential output conversion circuit, RS422 differential input conversion circuit, LVDS differential input conversion circuit, LVDS differential output conversion circuit, FPGA, configuration refresh circuit, program memory, reset circuit, enable control circuit, power conversion circuit; The configuration refresh circuit is connected to the program memory to read the configuration data therefrom, receives the power-on reset signal of the reset circuit, performs global configuration and timing dynamic refresh on the FPGA, and outputs the reset signal to the FPGA and the enable control circuit; the enable control circuit is also connected to the RS422 differential output conversion circuit and the LVDS differential output conversion circuit, and outputs the enable control signal to them; The 1553B bus interface circuit connects to the FPGA and exchanges information on the one hand, and sends 1553B bus signals to the 1553B bus device end on the other hand; The RS422 differential output conversion circuit receives signals from the FPGA and the enable control circuit, and sends an RS422 output signal to the mounted device; The RS422 differential input conversion circuit receives the RS422 input signal sent by the onboard device and outputs a single-ended signal to the FPGA; The LVDS differential output conversion circuit receives signals from the FPGA and the enable control circuit, and sends an LVDS three-wire output signal to the LVDS receiving device; The LVDS differential input conversion circuit receives the LVDS three-wire input signal of the mounted device and outputs a single-ended signal to the FPGA; The RS422 differential output conversion circuit, the RS422 differential input conversion circuit, the LVDS differential output conversion circuit, and the LVDS differential input conversion circuit simultaneously forward the signal to the internal connector; The power conversion circuit receives the 5V power supply output by the power management module to the internal connector and outputs +3.3V, +1.8V, and +1.5V power supplies to the FPGA.

3. The integrated design data conversion system according to claim 2, characterized in that: The 1553B bus interface circuit includes an isolation transformer, a bus controller, and a voltage conversion circuit. The 1553B bus is connected to the bus controller through an isolation transformer, and the signal output by the bus controller is converted into a voltage acceptable to the FPGA through a voltage conversion circuit.

4. The integrated design data conversion system according to claim 2, characterized in that: The communication interface of the mounted device adopts RS422 and LVDS communication. The FPGA in the system control module converts the 1553B bus data into RS422 data and then transmits it to the mounted device, or the FPGA in the system control module converts the RS422 and LVDS data of the mounted device into 1553B bus data or other data, and then transmits it to the whole device, so as to realize flexible conversion between different types of bus communication protocols between the platform and the mounted devices, and at the same time, perform priority and arbitration management on the communication of multiple channels of multiple mounted devices, and formulate different time slice communication strategies according to the characteristics of the mounted devices.

5. The integrated design data conversion system according to claim 2, characterized in that: After the device is powered on, the reset circuit resets the configuration refresh circuit. After the configuration refresh circuit is reset, the FPGA chip begins to be configured. After the configuration is completed, the configuration refresh circuit outputs a reset signal to reset the FPGA. At the same time, the power-on reset signal output by the reset circuit and the reset signal output by the configuration refresh circuit are output to the enable control circuit. The enable control circuit is also connected to the RS422 differential output conversion circuit, outputs an enable control signal to it, performs enable control during power-on and FPGA configuration, and prevents the RS422 differential output conversion circuit from sending unexpected data during power-on and FPGA configuration; and is simultaneously connected to the LVDS differential output conversion circuit, outputs an enable control signal to it, performs enable control during power-on and FPGA configuration, and prevents the LVDS differential output conversion circuit from sending unexpected data during power-on and FPGA configuration.

6. The integrated design data conversion system according to claim 1, characterized in that: The power management module includes two categories: The first category is: after the primary bus input passes through: primary protection circuit, surge suppression circuit, switch control circuit, filter and power conversion, it outputs the required 5V power to the system control module; The second category is: after the primary bus input passes through: the first-level protection circuit, surge suppression circuit, switch control circuit, and second-level protection circuit in sequence, it supplies power to the onboard equipment and its thermal control equipment.

7. The integrated design data conversion system according to claim 6, characterized in that: In the power management module: The surge suppression circuit includes MOS tube, resistor and capacitor, forming a resistance-capacitance circuit around the MOS tube. By adjusting the resistance and capacitance values, the surge can be suppressed within a safe range. The switch control circuit uses a MOS tube combined with a small relay to complete the power distribution output and prohibit output by controlling the switch of the MOS tube; The switch control circuit and the surge suppression circuit share the MOS tube.

8. The integrated design data conversion system according to claim 6, characterized in that: Both the primary protection circuit and the secondary protection circuit adopt an unbalanced design to protect the busbar safety when the equipment is short-circuited. Specifically: In the protection circuit, the fuse specifications and resistance values ​​are selected according to the current, and the fuse adopts a two-stage unbalanced design. In order to increase reliability, the rated current of the fuse is reduced: the second-stage fuse is selected to be a fuse that is twice greater than the bus current, and the rated current of the first-stage fuse is greater than the rated current of the second-stage fuse, so that when the onboard equipment is short-circuited, even if the second-stage fuse burns out, it will not affect the first-stage fuse.

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