Method for rapidly testing digital quantity IO (input / output) point of programmable logic controller

Abstract

The invention discloses a method for quickly testing a digital IO (input / output) point of a programmable logic controller, which comprises the following steps of: writing a test program to write an output mapping area K4Y0 by enabling digital input ports X0 to X17 to correspond to output ports Y0 to Y17 one by one, reading a numerical value in an input mapping area K4X0 to verify, and then writing the digital IO point of the programmable logic controller. According to the invention, each digital quantity input port and each digital quantity output port can correctly receive and feed back signals, so that no external test equipment is needed in the test process, the test can be completed by using the input and output points of the programmable logic controller body, the test method is simple and efficient, and the test method is simple in step and low in cost. The terminal of the movable programmable logic controller, which is easy to connect, can be copied quickly and can be plugged, is connected with a wire, and the test can be started after the programmable logic controller is plugged, so that the test efficiency is high, the test can be completed in an extremely short time through a PLC program, and the test device can be suitable for batch production and test operation of the programmable logic controller.

Description

Technical Field

[0001] The invention relates to the technical field of industrial automation, in particular to a method for quickly testing digital quantity IO points of a programmable logic controller. Background Art

[0002] Programmable Logic Controller (PLC) uses a programmable memory to store instructions for performing logical operations, sequential control, timing, counting and arithmetic operations, and controls various types of mechanical equipment or production processes through digital or analog input and output. The application scope of PLC is very wide, covering almost all industrial fields that require automated control, such as transportation, petrochemicals, power systems, etc., and plays an irreplaceable role in modern industrial production. With the continuous development of technology, the functions of PLC will be richer and the scope of application will be further expanded.

[0003] During the mass production of programmable logic controllers, due to the limitations of electronic circuit manufacturing technology, it is inevitable that some PLC products will have short circuits or cold solder joints, which are specifically manifested in the following four phenomena in the functions of PLC IO points: 1. The connection and disconnection of the PLC input port cannot be detected by the PLC system; 2. The connection and disconnection of input port 1 affects the input detection of input port 2; 3. The output state of the PLC system cannot be correctly given to the corresponding output port; 4. The output state of the PLC system affects irrelevant output ports. Therefore, PLC mass production requires detection of whether each digital input and output point can be correctly connected and disconnected.

[0004] Based on the above reasons, the present invention proposes a method for quickly testing the digital IO points of a programmable logic controller, aiming to solve the problem that IO point function abnormalities are difficult to troubleshoot due to manufacturing process limitations in PLC mass production, and to ensure that each digital input and output point can correctly implement the on-off function. Summary of the invention

[0005] 1. Technical issues to be resolved

[0006] In view of the deficiencies in the prior art, the present invention arranges digital quantity input ports X0 to X17 in one-to-one correspondence with output ports Y0 to Y17, writes a test program to perform a write operation on the output image area K4Y0, and reads the value in the input image area K4X0 for verification, so as to ensure that each digital quantity input and output port can correctly receive and feedback signals, so that no external test equipment is required during the test process, and the test can be completed using the input and output points of the programmable logic controller body, so that the test method is simple and efficient. At the same time, the test method on this side has simple steps, is easy to wire, can be quickly copied, and the pluggable active programmable logic controller terminals are connected, and the test can be started by plugging in the programmable logic controller. The test efficiency is high, and the test can be completed in a very short time through the PLC program, which can adapt to the mass production and test operations of programmable logic controllers.

[0007] (II) Technical solution

[0008] To achieve the above object, the present invention provides the following technical solution: a method for quickly testing digital quantity IO points of a programmable logic controller, comprising the following steps:

[0009] Step 1: representation of the digital input port and digital output port of the programmable logic controller, representation of the programmable logic controller memory image area corresponding to the digital input port, and representation of the programmable logic controller memory image area corresponding to the digital output port;

[0010] Step 2: Connect the output port and input port of the programmable logic controller one by one to complete the preparation work;

[0011] Step 3: The program writes to the output image area and reads the corresponding input image area;

[0012] Step 4: Read the input image area. If it is not equal to the written value, the test is abnormal, otherwise continue testing;

[0013] Step 5: Follow the steps 3 and 4 above to complete the test. If there is no abnormality, the test passes.

[0014] Preferably, the digital input ports of the programmable logic controller are represented by X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16 and X17, and the digital output ports are represented by Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8, Y9, Y10, Y11, Y12, Y13, Y14, Y15, Y16 and Y17; the programmable logic controller memory image area corresponding to the digital input ports X0-X17 is represented by K4X0, and the programmable logic controller memory image area corresponding to the digital output ports Y0-Y17 is represented by K4Y0.

[0015] Preferably, the one-to-one docking mode of the output port and the input port of the programmable logic controller is: X0 docking Y0, X1 docking Y1, X2 docking Y2, X3 docking Y3, X4 docking Y4, X5 docking Y5, X6 docking Y6, X7 docking Y7, X8 docking Y8, X9 docking Y9, X10 docking Y10, X11 docking Y11, X12 docking Y12, X13 docking Y13, X14 docking Y14, X15 docking Y15, X16 docking Y16 and X17 docking Y17.

[0016] Preferably, the one-to-one sampling of the output port and the input port of the programmable logic controller is achieved by physical connection, and the output port Y0 of the PLC to be tested is connected to the input port X0, Y1 to X1, and finally Y17 to X17 in a one-to-one correspondence using connecting cables to construct a closed-loop test circuit.

[0017] Preferably, the test data writing and reading verification operation includes the following steps:

[0018] S11: Under the control of the test host control module, the test program initially writes the hexadecimal value 16#1 to the output image area K4Y0, and reads the data of the input image area K4X0 after a short delay. If it is not equal to 16#1, the corresponding test is determined to be abnormal and the fault information is recorded. Otherwise, the next test process is continued;

[0019] S12: Write hexadecimal values ​​16#2, 16#4, and 16#8 to the output image area K4Y0 in sequence, wait for the same stable delay after each write, read K4X0 and compare, if inconsistent, it is judged to be abnormal, and continue until the verification of the written value 16#8000 is completed, realize the input detection and verification of the single output point under the activation drive in turn, and check the independent output and input conduction function of each point;

[0020] S13: Then carry out combination verification, write 16#FFFE to the output image area K4Y0, read and verify K4X0 according to the process, if it does not match, it is abnormal; subsequently write 16#FFFD, 16#FFFB, etc. in sequence to gradually decrease the binary bit combination value, comprehensively covering the input reception accuracy under the scenario of multiple output bit combination activation, so as to deeply detect the coordinated work and anti-interference and anti-crosstalk capabilities of the input and output points, and ensure the normal operation of the IO points under complex signal conditions.

[0021] Preferably, the short delay is set to a duration sufficient to ensure stable signal transmission and adequate response of the programmable logic controller system, and the value range is 5-20 milliseconds.

[0022] Preferably, the recorded fault information includes the suspected location of the error port and the error type.

[0023] Preferably, the test passes when all the above-mentioned test steps are completed, and each time the data read from the input image area matches the corresponding data written to the output image area, the on / off function test of the digital input and output points of the PLC sample to be tested is judged to have passed. If any verification mismatch occurs during the period, it indicates that the test is abnormal.

[0024] Preferably, after the programmable logic controller completes the test, the programmable logic controller that passes the test directly enters the next production process, and the programmable logic controller that tests abnormally generates a test report and is extracted and processed separately.

[0025] Preferably, the programmable logic controller test operation is implemented using a 24 volt power supply.

[0026] (III) Beneficial effects

[0027] Compared with the prior art, the present invention provides a method for quickly testing the digital quantity IO points of a programmable logic controller, which has the following beneficial effects: the present invention arranges a one-to-one correspondence between digital quantity input ports X0 to X17 and output ports Y0 to Y17, writes a test program to perform a write operation on the output image area K4Y0, and reads the value in the input image area K4X0 for verification, so as to ensure that each digital quantity input and output port can correctly receive and feedback signals, so that no external test equipment is required during the test process, and the test can be completed using the input and output points of the programmable logic controller body, so that the test method is simple and efficient. At the same time, the test method on this side has simple steps, is easy to wire, can be quickly copied, and the pluggable active programmable logic controller terminal is connected, and the test can be started by plugging in the programmable logic controller. The test efficiency is high, and the test can be completed in a very short time through the PLC program, which can adapt to the mass production and test operation of the programmable logic controller. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a flow chart of the testing method of the present invention;

[0029] Figure 2 It is a port connection diagram of the programmable logic controller of the present invention;

[0030] Figure 3 This is a flow chart of the test data writing and reading verification operation of the present invention;

[0031] Figure 4 A port docking table of a programmable logic controller of the present invention;

[0032] Figure 5 This is a flow chart of Embodiment 1 of the present invention;

[0033] Figure 6 4 is a structural diagram of the output image area K4Y0 in the first embodiment of the present invention;

[0034] Figure 7 This is a flow chart of Embodiment 2 of the present invention;

[0035] Figure 8 It is a structural diagram of the output image area K4Y0 in the second embodiment of the present invention. DETAILED DESCRIPTION

[0036] In order to better understand the purpose, structure and function of the present invention, in order to achieve efficient and convenient testing operation of programmable logic controller, the present invention makes digital quantity input ports X0 to X17 correspond to output ports Y0 to Y17 one by one, writes a test program to write to the output image area K4Y0, and reads the value in the input image area K4X0 for verification, so as to ensure that each digital quantity input and output port can correctly receive and feedback the signal, so that no external test equipment is required during the test, and the test can be completed with the input and output points of the programmable logic controller body, so that the test method is simple and efficient, and at the same time, the test method of this side has simple steps, is easy to wire, can be quickly copied, and the pluggable active programmable logic controller terminal is connected, and the test can be started by plugging in the programmable logic controller, the test efficiency is high, and the test can be completed in a very short time through the PLC program, which can adapt to the batch production and test operation of the programmable logic controller. A method for quickly testing the digital quantity IO points of a programmable logic controller of the present invention is further described in detail.

[0037] refer to Figure 1-4 The present invention provides a method for quickly testing digital IO points of a programmable logic controller, comprising the following steps:

[0038] Step 1: representation of the digital input port and digital output port of the programmable logic controller, representation of the programmable logic controller memory image area corresponding to the digital input port, and representation of the programmable logic controller memory image area corresponding to the digital output port;

[0039] Specifically, the digital input ports of the programmable logic controller are represented by X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16 and X17, and the digital output ports are represented by Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8, Y9, Y10, Y11, Y12, Y13, Y14, Y15, Y16 and Y17; the programmable logic controller memory image area corresponding to the digital input ports X0-X17 is represented by K4X0, and the programmable logic controller memory image area corresponding to the digital output ports Y0-Y17 is represented by K4Y0.

[0040] Step 2: Connect the output port and input port of the programmable logic controller one by one to complete the preparation work;

[0041] Specifically, the one-to-one docking method between the output port and the input port of the programmable logic controller is: X0 docks with Y0, X1 docks with Y1, X2 docks with Y2, X3 docks with Y3, X4 docks with Y4, X5 docks with Y5, X6 docks with Y6, X7 docks with Y7, X8 docks with Y8, X9 docks with Y9, X10 docks with Y10, X11 docks with Y11, X12 docks with Y12, X13 docks with Y13, X14 docks with Y14, X15 docks with Y15, X16 docks with Y16 and X17 docks with Y17.

[0042] Furthermore, the one-to-one sampling of the output port and the input port of the programmable logic controller is achieved by physical connection, and the output port Y0 of the PLC to be tested is connected to the input port X0, Y1 to X1, and finally Y17 to X17 in a one-to-one correspondence using connecting cables to construct a closed-loop test circuit.

[0043] Step 3: The program writes to the output image area and reads the corresponding input image area;

[0044] Specifically, the test data writing and reading verification operation includes the following steps:

[0045] S11: Under the control of the test host control module, the test program initially writes the hexadecimal value 16#1 to the output image area K4Y0, and reads the input image area K4X0 data after a short delay. If it is not equal to 16#1, the corresponding test is determined to be abnormal and the fault information is recorded. Otherwise, the next test process is continued. The short delay is set to ensure the duration of stable signal transmission and sufficient response of the programmable logic controller system, and the value range is 10 milliseconds;

[0046] Furthermore, the recorded fault information includes the suspected position of the error port and the error type;

[0047] S12: Write hexadecimal values ​​16#2, 16#4, and 16#8 to the output image area K4Y0 in sequence, wait for the same stable delay after each write, read K4X0 and compare, if inconsistent, it is judged to be abnormal, and continue until the verification of the written value 16#8000 is completed, realize the input detection and verification of the single output point under the activation drive in turn, and check the independent output and input conduction function of each point;

[0048] S13: Then carry out combination verification, write 16#FFFE to the output image area K4Y0, read and verify K4X0 according to the process, if it does not match, it is abnormal; subsequently write 16#FFFD, 16#FFFB, etc. in sequence to gradually decrease the binary bit combination value, comprehensively covering the input reception accuracy under the scenario of multiple output bit combination activation, so as to deeply detect the coordinated work and anti-interference and anti-crosstalk capabilities of the input and output points, and ensure the normal operation of the IO points under complex signal conditions.

[0049] Step 4: Read the input image area. If it is not equal to the written value, the test is abnormal, otherwise continue testing;

[0050] Step 5: Follow the steps 3 and 4 above to complete the test. If there is no abnormality, the test passes.

[0051] Specifically, the test passed means that the above-mentioned test process has been completely completed, and each time the data read from the input image area matches the corresponding data written to the output image area, it is determined that the on-off function test of the digital input and output points of the PLC sample to be tested has passed. If any verification mismatch occurs during the period, it indicates that the test is abnormal. After the programmable logic controller completes the test, the programmable logic controller that passes the test directly enters the next production process, and the programmable logic controller with an abnormal test generates a test report and is extracted and processed separately.

[0052] During the test, a 24 volt power supply is used to implement the programmable logic controller test operation.

[0053] Example 1: Reference Figure 5 and 6, taking the PLC with 16-point digital input and 16-point digital output as an example;

[0054] 1) Connect the output and input points of the PLC one by one, connect the Y0 output to the X0 input, the Y1 output to the X1 input, and so on: connect the Y17 output to the X17 input;

[0055] 2) The program writes 16#1 to the output image area K4Y0 and reads the input image area K4X0. If it is not equal to 16#1, the test is abnormal; otherwise, the test continues;

[0056] 3) The program writes 16#2 to the output image area K4Y0 and reads the input image area K4X0. If it is not equal to 16#2, the test is abnormal; otherwise, the test continues;

[0057] 4) As above, the program continues to write 16#4, 16#8, 16#10, 16#20, 16#40, 16#80, 16#100, 16#200, 16#400, 16#800, 16#1000, 16#2000, 16#4000, and 16#8000 to the output image area K4Y0; read the input image area K4X0. If it is not equal to the written value, the test is abnormal; otherwise, continue the test;

[0058] 5) The program writes 16#FFFE to the output image area K4Y0 and reads the input image area K4X0. If it is not equal to 16#FFFE, the test is abnormal; otherwise, the test continues;

[0059] 6) The program writes 16#FFFD to the output image area K4Y0 and reads the input image area K4X0. If it is not equal to 16#FFFD, the test is abnormal; otherwise, the test continues;

[0060] 7) As above, the program continues to write 16#FFFB, 16#FFF7, 16#FFEF, 16#FFDF, 16#FFBF, 16#FF7F, 16#FEFF, 16#1FDFF, 16#FBFF, 16#F7FF, 16#EFFF, 16#DFFF, 16#BFFF, and 16#7FFF to the output image area K4Y0 respectively; read the input image area K4X0, if it is not equal to the written value, the test is abnormal; otherwise, continue testing.

[0061] If the tests 1-7 above are completed without any exception, the test passes.

[0062] Example 2: Reference Figure 7 and 8 In general digital IO circuit design, adjacent IO points are prone to mutual influence, such as short circuit; the probability of short circuit of non-adjacent IO points is extremely low. Based on this assumption, the detection process includes:

[0063] 1) The wiring of PLC output and input points is the same as above;

[0064] 2) The program writes 16#0 to the output image area K4Y0 and reads the input image area K4X0. If it is not equal to 16#0, the test is abnormal; otherwise, the test continues;

[0065] 3) The program writes 16#FFFF to the output image area K4Y0 and reads the input image area K4X0. If it is not equal to 16#FFFF, the test is abnormal; otherwise, the test continues;

[0066] 4) The program writes 16#AAAA to the output image area K4Y0 and reads the input image area K4X0. If it is not equal to 16#AAAA, the test is abnormal; otherwise, the test continues;

[0067] 5) The program writes 16#5555 to the output image area K4Y0 and reads the input image area K4X0. If it is not equal to 16#5555, the test is abnormal; otherwise, the test continues;

[0068] If the tests 1-5 above are completed without any exception, the test passes.

[0069] The above programmable logic controller uses the Rui Te RX8U-32MT PLC to complete the wiring in the manner described above in the patent of the present invention, uses the programming software to write the ladder diagram program according to the steps of the content of the present invention, downloads it to the PLC, simulates any IO point short circuit (adjacent IO point circuits stick together), simulates any IO point disconnection (any point is not connected);

[0070] In summary, defective products can be detected by following the above steps, and the defective product detection rate of digital IO points is 100%. It only takes 100 milliseconds to test each PLC (excluding the time for manually downloading the PLC program), and no external auxiliary equipment is required for testing. It is low-cost and easy to implement.

[0071] It is to be understood that the present invention is described by some embodiments, and it is known to those skilled in the art that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. In addition, under the teachings of the present invention, these features and embodiments may be modified to adapt to specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the scope of protection of the present invention.

Claims

1. A method for quickly testing digital IO points of a programmable logic controller, characterized in that: The following steps are involved: Step 1: representation of the digital input port and digital output port of the programmable logic controller, representation of the programmable logic controller memory image area corresponding to the digital input port, and representation of the programmable logic controller memory image area corresponding to the digital output port; Step 2: Connect the output port and input port of the programmable logic controller one by one to complete the preparation work; Step 3: The program writes to the output image area and reads the corresponding input image area; Step 4: Read the input image area. If it is not equal to the written value, the test is abnormal, otherwise continue testing; Step 5: Follow the steps 3 and 4 above to complete the test. If there is no abnormality, the test passes.

2. A method for quickly testing digital IO points of a programmable logic controller according to claim 1, characterized in that: The digital input ports of the programmable logic controller are represented by X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16 and X17, and the digital output ports are represented by Y0, Y1, Y2, Y3, Y4, Y5, Y6, Y7, Y8, Y9, Y10, Y11, Y12, Y13, Y14, Y15, Y16 and Y17. The programmable logic controller memory image area corresponding to the digital input ports X0-X17 is represented by K4X0, and the programmable logic controller memory image area corresponding to the digital output ports Y0-Y17 is represented by K4Y0.

3. A method for quickly testing digital IO points of a programmable logic controller according to claim 2, characterized in that: The one-to-one docking mode between the output port and the input port of the programmable logic controller is: X0 docks with Y0, X1 docks with Y1, X2 docks with Y2, X3 docks with Y3, X4 docks with Y4, X5 docks with Y5, X6 docks with Y6, X7 docks with Y7, X8 docks with Y8, X9 docks with Y9, X10 docks with Y10, X11 docks with Y11, X12 docks with Y12, X13 docks with Y13, X14 docks with Y14, X15 docks with Y15, X16 docks with Y16 and X17 docks with Y17.

4. A method for quickly testing digital IO points of a programmable logic controller according to claim 3, characterized in that: The one-to-one sampling of the output port and the input port of the programmable logic controller is achieved by physical connection. The output port Y0 of the PLC to be tested is connected to the input port X0, Y1 to X1, and finally Y17 to X17 in a one-to-one correspondence using connecting cables to construct a closed-loop test circuit.

5. A method for quickly testing digital IO points of a programmable logic controller according to claim 4, characterized in that: The test data writing and reading verification operation includes the following steps: S11: Under the control of the test host control module, the test program initially writes the hexadecimal value 16#1 to the output image area K4Y0, and reads the data of the input image area K4X0 after a short delay. If it is not equal to 16#1, the corresponding test is determined to be abnormal and the fault information is recorded. Otherwise, the next test process is continued; S12: Write hexadecimal values ​​16#2, 16#4, and 16#8 to the output image area K4Y0 in sequence, wait for the same stable delay after each write, read K4X0 and compare, if inconsistent, it is judged to be abnormal, and continue until the verification of the written value 16#8000 is completed, realize the input detection and verification of the single output point under the activation drive in turn, and check the independent output and input conduction function of each point; S13: Then carry out combination verification, write 16#FFFE to the output image area K4Y0, read and verify K4X0 according to the process, if it does not match, it is abnormal; subsequently write 16#FFFD, 16#FFFB, etc. in sequence to gradually decrease the binary bit combination value, comprehensively covering the input reception accuracy under the scenario of multiple output bit combination activation, so as to deeply detect the coordinated work and anti-interference and anti-crosstalk capabilities of the input and output points, and ensure the normal operation of the IO points under complex signal conditions.

6. A method for quickly testing digital IO points of a programmable logic controller according to claim 5, characterized in that: The short delay is set to ensure the duration of stable signal transmission and sufficient response of the programmable logic controller system, and the value range is 5-20 milliseconds.

7. A method for quickly testing digital IO points of a programmable logic controller according to claim 6, characterized in that: The recorded fault information includes the suspected position of the error port and the error type.

8. A method for quickly testing digital IO points of a programmable logic controller according to claim 7, characterized in that: The test passed means that the above-mentioned test process has been completely completed, and each time the data read from the input image area matches the corresponding data written to the output image area, the on-off function test of the digital input and output points of the PLC sample to be tested is judged to have passed. If any verification mismatch occurs during the period, it indicates that the test is abnormal.

9. A method for quickly testing digital IO points of a programmable logic controller according to claim 8, characterized in that: After the programmable logic controller completes the test, the programmable logic controller that passes the test directly enters the next production process, and the programmable logic controller that fails the test generates a test report and is extracted and processed separately.

10. A method for quickly testing digital IO points of a programmable logic controller according to claim 9, characterized in that: The programmable logic controller test operation is implemented using a 24 volt power supply.

Images