40Gbps high-speed storage system and method applied to SAR satellite
Through the FPGA+NVMe hard disk architecture, combined with GTY and LVDS interfaces, a 40Gbps high-speed storage system is realized, solving the problems of complex and low efficiency of storage system design in the existing technology, improving storage efficiency and reducing costs.
Patent Information
- Application Number
- CN202411689435.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-25
- Publication Date
- 2025-03-11
AI Technical Summary
The existing remote sensing satellite storage system is complex in design and low in efficiency, making it difficult to meet the needs of high-speed data storage, especially image data storage under high resolution, multi-mode, and multi-channel.
Using the FPGA+NVMe hard disk architecture, the 40Gbps high-speed storage system is realized through the four-channel GTY high-speed serial serdes interface and the LVDS low-speed serial interface, which simplifies the system structure and reduces the number of controllers and Flash arrays.
It realizes stable and reliable data storage at high data rates, improves storage efficiency, reduces system complexity, weight and cost, and is suitable for ultra-high-speed remote sensing satellites and low-speed remote sensing satellites.
Smart Images
Figure CN119597217A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of remote sensing satellites, and in particular to a 40Gbps high-speed storage system and method applied to SAR satellites. Background Art
[0002] The storage system is an important part of the remote sensing satellite data link. Traditional remote sensing satellite storage systems generally use multiple SATA disks or flash array distributed storage systems, which require multiple controllers and flash stacking. As the satellite resolution continues to increase, in order to meet the high rate indicators of the payload, this method needs to continuously expand the capacity, which makes the installed weight continue to increase, increasing costs, and the system is too complex, inefficient, and has reduced reliability, making it difficult to meet the requirements.
[0003] This patent proposes a 40Gbps high-speed storage device and method for SAR satellites, which enables the image data output by the SAR satellite payload under high resolution, multi-mode, and multi-channel to still stably and reliably store complete data. Using the FPGA+nvme hard disk architecture, four hard disks work simultaneously, and the storage rate can reach 40Gbps. This architecture does not require multiple controllers or stacking multiple Flash chips. It ensures that data can still be stably stored at high data rates, improves storage efficiency, and reduces system complexity, weight, and cost.
[0004] When designing a remote sensing satellite, it is necessary to design on-board storage based on the input parameters such as the type of payload, payload rate and quantity. Currently, there are generally two types of on-board storage system designs. One is FPGA+SATA disk architecture storage. This method has a low storage rate, and generally a single disk can reach 400Mbps. It is suitable for small satellites with low payload rates and small numbers. The other is large-capacity storage based on FLASH arrays. This method requires continuous additions of FLASH arrays to achieve the ideal rate, which greatly increases the volume and weight, resulting in higher costs. In addition, the design is complex and often requires multiple controllers. The above two methods cannot take into account both the high performance and low cost of satellites, and are not suitable for commercial high-rate remote sensing satellite storage systems. Summary of the invention
[0005] The present invention aims to solve the problems of complex design, low efficiency and customization of existing satellite high-speed storage.
[0006] To solve the above technical problems, the present invention is achieved through the following technical solutions:
[0007] Solution 1: The present invention proposes a 40Gbps high-speed storage system applied to SAR satellites, the system comprising a control module, a storage module, and a power module;
[0008] The control module is used to use the FPGA module as the core controller, one side of which is connected to the SAR payload electric box through a four-channel GTY high-speed serial serdes interface, and the LVDS low-speed serial interface is connected to the navigation electric box;
[0009] The data transmission interface is connected to the data transmission terminal through the TLK2711 interface;
[0010] The CAN interface is connected to the central computer via the CAN bus;
[0011] The storage module is used to store multiple NVMe solid-state hard drives and peripheral circuits;
[0012] The power supply module is used to supply power to the control module and the storage module.
[0013] Furthermore, a preferred implementation is provided, wherein the four-channel GTY high-speed serial serdes interface includes a GTY driver and data conversion, and the GTY driver uses an AXI-stream interface to complete data interaction; the data conversion performs clock and data bit width conversion through 4 groups of asynchronous fifos.
[0014] Furthermore, a preferred embodiment is provided, wherein the LVDS low-speed serial interface includes an LVDS driver and data conversion, wherein the LVDS driver shifts single-bit data according to a timing sequence and converts the data into 8-bit wide data output; the data conversion performs clock and data width conversion based on 4 groups of asynchronous FIFOs and then outputs four groups of 256-bit wide data to the FPGA module for processing.
[0015] Furthermore, a preferred implementation is provided, which includes a step of uram data caching before outputting four groups of 256-bit wide data to the FPGA module for processing.
[0016] Further, a preferred embodiment is provided, wherein the method for storing by the NVMe solid state drive and the peripheral circuit is:
[0017] S1, control 4 NVMe solid-state drives to power on, the 4 NVMe solid-state drives are SSD1, SSD2, SSD3, and SSD4;
[0018] S2, through the nvme protocol driver and PCIE IP control 4 NVMe solid state drives initialization, so that the NVMe solid state drives into the ready state;
[0019] S3. According to the file management unit, four groups of 256-bit wide data are written into four groups of NVME solid state drives for storage.
[0020] Furthermore, a preferred implementation is provided, in which the method for controlling the power-on of four NVMe solid-state drives in S1 is based on the principle of staggered power-on.
[0021] Furthermore, a preferred embodiment is provided, wherein the power module includes a primary bus power processing unit and an isolated DC-DC module, which are used to convert a 28V voltage into 12V to power the storage module and the control module respectively.
[0022] Solution 2: A 40 Gbps high-speed storage method applied to a SAR satellite, the method comprising the following steps:
[0023] S1, receiving the control instructions sent by the central computer through the CAN interface and processing the instructions;
[0024] S2, four-channel GTY high-speed serdes interface receives SAR payload data and one LVDS low-speed serial interface receives navigation data, and processes the received high-speed data;
[0025] S3, the FPGA module stores the received high-speed data into the storage module according to the control instruction;
[0026] S4. Read the data from the storage module according to the control instruction and send it to the data transmission terminal through the data transmission interface.
[0027] Solution three: A computer device includes a memory and a processor, wherein the memory stores a computer program, and when the processor runs the computer program stored in the memory, the processor executes any one of the methods described in Solution two.
[0028] Solution 4: A computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the method described in any one of Solution 2 are implemented.
[0029] The present invention is beneficial in that:
[0030] The 40Gbps high-speed storage system and method for SAR satellites described in the present invention are composed of three independent hardware units: a control module, a storage module, and a power module. The stand-alone hardware structure is simple, the function of each module is clearly divided, and the maintainability and replaceability are strong.
[0031] The present invention adopts FPGA module + NVME hard disk architecture, which can achieve 15Gbps high-speed storage on a single disk, and the storage rate is much higher than SATA architecture storage or flash array storage.
[0032] Four-channel GTY high-speed 40Gbps serdes data reception and LVDS low-speed 50Mbps serial data reception, storage rate coverage from 50Mbps to 40Gbps bandwidth, four NVMe hard drives simultaneously store in parallel. Compared with other satellite storage architectures, the present invention has very high versatility.
[0033] The 40Gbps high-speed storage system and method for SAR satellites described in the present invention solve the problems of complex, low-efficiency and customization of existing satellite high-speed storage designs, can take into account both storage performance and cost, improve the storage rate, and significantly reduce manufacturing costs and design workload.
[0034] The present invention is also applicable to the fields of ultra-high-speed remote sensing satellites and low-speed remote sensing satellites. BRIEF DESCRIPTION OF THE DRAWINGS
[0035] Figure 1 This is a principle block diagram of a 40 Gbps high-speed storage system applied to a SAR satellite as described in Implementation Method 1.
[0036] Figure 2 This is a schematic diagram of a GTY and LVDS interface data receiving data stream module in a 40 Gbps high-speed storage system applied to a SAR satellite as described in Implementation Example 1.
[0037] Figure 3 This is a schematic diagram of a data source selection module according to the eleventh embodiment.
[0038] Figure 4 This is a schematic diagram of the URAM cache module described in the eleventh embodiment.
[0039] Figure 5 This is a schematic diagram of the NVME solid-state hard drive control module described in Implementation Example 11. DETAILED DESCRIPTION
[0040] In order to make the purpose, technical solutions and advantages of the implementation methods of the present application clearer, the technical solutions in the implementation methods of the present application will be clearly and completely described below in conjunction with the drawings in the implementation methods of the present application. Obviously, the described implementation methods are only part of the implementation methods of the present application, not all of the implementation methods.
[0041] Embodiment 1: This embodiment provides a 40Gbps high-speed storage system applied to a SAR satellite, the system comprising a control module, a storage module, and a power module;
[0042] The control module is used to use the FPGA module as the core controller, one side of which is connected to the SAR payload electric box through a four-channel GTY high-speed serial serdes interface, and the LVDS low-speed serial interface is connected to the navigation electric box;
[0043] The data transmission interface is connected to the data transmission terminal through the TLK2711 interface;
[0044] The CAN interface is connected to the central computer via the CAN bus;
[0045] The storage module is used to store multiple NVMe solid-state hard drives and peripheral circuits;
[0046] The power supply module is used to supply power to the control module and the storage module.
[0047] Implementation method 2. This implementation method further limits the 40Gbps high-speed storage system applied to SAR satellites described in implementation method 1. The four-channel GTY high-speed serial serdes interface includes a GTY driver and data conversion. The GTY driver uses an AXI-stream interface to complete data interaction. The data conversion performs clock and data bit width conversion through 4 groups of asynchronous fifos.
[0048] Implementation method three. This implementation method is a further limitation of the 40Gbps high-speed storage system applied to SAR satellites described in implementation method one. The LVDS low-speed serial interface includes an LVDS driver and data conversion. The LVDS driver shifts single-bit data according to the timing and converts it into 8-bit wide data output; the data conversion performs clock and data bit width conversion based on 4 groups of asynchronous fifos and outputs four groups of 256-bit wide data to the FPGA module for processing.
[0049] Implementation method 4: This implementation method further limits the 40Gbps high-speed storage system applied to SAR satellites described in implementation method 3, and also includes a step of uram data caching before outputting four groups of 256-bit wide data to the FPGA module for processing.
[0050] Implementation mode 5: This implementation mode further limits the 40Gbps high-speed storage system applied to SAR satellites described in implementation mode 1. The storage method of the NVMe solid-state drive and the peripheral circuit is as follows:
[0051] S1, control 4 NVMe solid-state drives to power on, the 4 NVMe solid-state drives are SSD1, SSD2, SSD3, and SSD4;
[0052] S2, through the nvme protocol driver and PCIE IP control 4 NVMe solid state drives initialization, so that the NVMe solid state drives into the ready state;
[0053] S3. According to the file management unit, four groups of 256-bit wide data are written into four groups of NVME solid state drives for storage.
[0054] Implementation method six. This implementation method is a further limitation of the 40Gbps high-speed storage system applied to SAR satellites described in implementation method one. The method for controlling the power-on of four NVMe solid-state drives in S1 is the principle of staggered power-on.
[0055] Implementation method seven. This implementation method is a further limitation of the 40Gbps high-speed storage system applied to SAR satellites described in implementation method one. The power supply module includes a primary bus power supply processing unit and an isolated DC-DC module, which is used to convert 28V voltage into 12V to power the storage module and the control module respectively.
[0056] Embodiment 8: This embodiment proposes a 40 Gbps high-speed storage method applied to a SAR satellite, the method comprising the following steps:
[0057] S1, receiving the control instructions sent by the central computer through the CAN interface and processing the instructions;
[0058] S2, four-channel GTY high-speed serdes interface receives SAR payload data and one LVDS low-speed serial interface receives navigation data, and processes the received high-speed data;
[0059] S3, the FPGA module stores the received high-speed data into the storage module according to the control instruction;
[0060] S4. Read the data from the storage module according to the control instruction and send it to the data transmission terminal through the data transmission interface.
[0061] Embodiment 9: This embodiment proposes a computer device, including a memory and a processor, wherein the memory stores a computer program, and when the processor runs the computer program stored in the memory, the processor executes the method described in embodiment 8.
[0062] Embodiment 10: This embodiment proposes a computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, the steps of the method described in embodiment 8 are implemented.
[0063] Implementation eleven: This implementation provides an example, which is used to explain the above implementations one to eight. The specific example is as follows:
[0064] This embodiment follows Figure 1 The overall hardware design is implemented in the architecture. The present embodiment proposes a 40Gbps high-speed storage system and method for SAR satellites. The system includes a control module, a storage module, and a power module.
[0065] The control module serves as the control core of the data storage box. It is mainly responsible for completing data reception, transmission, read and write control, file management, and external communication. It uses FPGA as the core controller and is connected to the SAR payload box through a 4-way GTY high-speed serial serdes interface and a LVDS interface to the navigation box.
[0066] The storage module is mainly composed of multiple storage media (NVMe solid-state drives) and peripheral circuits.
[0067] The power module is mainly composed of a primary bus power processing unit and an isolated DCDC module, which converts the entire satellite's 28V voltage into 12V to power the storage board and control board respectively.
[0068] Combination Figures 2 to 5 Describe the internal logic of the core FPGA processor of the control module, which is divided into the following parts:
[0069] 1. GTY and LVDS interface data reception,
[0070] Construct parallel multi-channel, multi-source data receiving units, such as Figure 2 As shown in the figure, it includes four channels of GTY high-speed serdes data reception and one channel of LVDS low-speed serial data reception.
[0071] Four-channel GTY high-speed serdes data reception is divided into two parts: GTY drive part and data conversion part:
[0072] (1) GTY driver uses the AXI-stream interface to complete data exchange. The user-side clock is 156.25Mhz and the data bit width is 256 bits.
[0073] (2) Data conversion: The received 256-bit aurora data is converted into clock and data bit width through four sets of asynchronous fifos. The write clock of each fifo is 156.25Mhz, the write data is 64-bit wide, and the read clock is 125Mhz, the read data is 256-bit wide. Finally, four sets of 256-bit wide data are output to the subsequent module for processing.
[0074] One LVDS low-speed serial data receiver is divided into two parts: LVDS driver and data converter:
[0075] (1) LVDS driver: shifts the input single-bit data according to the timing and converts it into 8-bit wide data output, with the high bit first and the low bit last.
[0076] (2) Data conversion: Since the first-level FIFO cannot achieve 8-fold bit width conversion, the 8-bit bit width is converted to 256 bits through two-level FIFOs, and then the clock and data bit width are converted through four groups of asynchronous FIFOs. The write clock of each group of FIFOs is 50Mhz, the write data is 64 bits wide, the read clock is 125Mhz, and the read data is 256 bits wide. Finally, four groups of 256-bit wide data are output to the subsequent module for processing.
[0077] 2. Data source selection
[0078] Both data sources in the above modules are fed into this level module, such as Figure 3 As shown, the data input has 4 groups of 256-bit wide GTY data and 4 groups of 256-bit wide LVDS data. Data selection is performed according to the mode selection instruction, 11H is the SAR payload GTY data, 22H is the navigation stand-alone LVDS data, and the state machine is used to control the selection and switching, and 4 groups of 256-bit wide data are output to the lower-level module.
[0079] 3. URAM data cache
[0080] The four groups of 256-bit wide data output from the above module are cached separately for uram data, such as Figure 4 As shown in the figure, the input and output interfaces of the four groups of caches need to call the FPGA primitive, set FIFO_MEMORY_TYPE to "ultra", set READ_MODE to "fwft", and the cache depth of each group is 131072, and the bit width is 256bit, that is, 32Mb. In order to prevent the loss of data during the bubble time of the subsequent storage, four groups of 256-bit wide data are fed into the nvme control module according to the subsequent ready signal.
[0081] 4. NVME solid state drive control
[0082] NVME solid state drive control is mainly used to drive the hard disk to keep it in normal working state, such as Figure 5 shown.
[0083] First, control the power-on of the four hard disks, adopt the staggered power-on principle, and power on each disk at an interval of 6 seconds. That is, SSD1 is powered on, and SSD2 is powered on 6 seconds later, and so on, to complete the power-on of the four hard disks.
[0084] Secondly, the 4 SSDs are initialized through the nvme protocol driver and PCIE IP control, so that the hard disk enters the ready state and is ready to receive data at any time.
[0085] Finally, the four groups of 256-bit wide data in step 3 are written into four groups of NVME hard disks respectively according to the file management unit.
[0086] Those skilled in the art will appreciate that the above are only preferred embodiments of the present invention, and the various embodiments of the present disclosure and / or the features described in the claims may be combined or combined in various ways, even if such combinations or combinations are not explicitly described in the present disclosure. It is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art may still modify the technical solutions described in the aforementioned embodiments, or perform equivalent substitutions on some of the technical features therein. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention shall be included in the protection scope of the present invention.
[0087] Although preferred embodiments of the present invention have been described, additional changes and modifications may be made to these embodiments by those skilled in the art once the basic inventive concepts are known. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention. Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.
Claims
1. A 40Gbps high-speed storage system for SAR satellites, characterized in that: The system includes a control module, a storage module, and a power module; The control module is used to use the FPGA module as the core controller, one side of which is connected to the SAR payload electric box through a four-channel GTY high-speed serial serdes interface, and the LVDS low-speed serial interface is connected to the navigation electric box; The data transmission interface is connected to the data transmission terminal through the TLK2711 interface; The CAN interface is connected to the central computer via the CAN bus; The storage module is used to store multiple NVMe solid-state hard drives and peripheral circuits; The power supply module is used to supply power to the control module and the storage module.
2. The 40Gbps high-speed storage system for SAR satellite according to claim 1, characterized in that: The four-channel GTY high-speed serial serdes interface includes a GTY driver and data conversion. The GTY driver uses an AXI-stream interface to complete data interaction. The data conversion performs clock and data bit width conversion through four groups of asynchronous fifos.
3. The 40Gbps high-speed storage system for SAR satellite according to claim 1, characterized in that: The LVDS low-speed serial interface includes LVDS drive and data conversion. The LVDS drive shifts single-bit data according to the timing and converts it into 8-bit wide data output; the data conversion performs clock and data width conversion based on 4 groups of asynchronous fifos and outputs four groups of 256-bit wide data to the FPGA module for processing.
4. The 40Gbps high-speed storage system for SAR satellite according to claim 3, characterized in that: Before outputting four groups of 256-bit wide data to the FPGA module for processing, the step of uram data caching is also included.
5. The 40Gbps high-speed storage system for SAR satellite according to claim 1, characterized in that: The method for storing by the NVMe solid state drive and the peripheral circuit is: S1, control 4 NVMe solid-state drives to power on, the 4 NVMe solid-state drives are SSD1, SSD2, SSD3, and SSD4; S2, through the nvme protocol driver and PCIE IP control 4 NVMe solid state drives initialization, so that the NVMe solid state drives into the ready state; S3. According to the file management unit, four groups of 256-bit wide data are written into four groups of NVME solid state drives for storage.
6. The 40Gbps high-speed storage system for SAR satellite according to claim 1, characterized in that: The method for controlling the power-on of the four NVMe solid-state drives in S1 is the principle of staggered power-on.
7. The 40Gbps high-speed storage system for SAR satellite according to claim 1, characterized in that: The power module includes a primary bus power processing unit and an isolated DC-DC module, which are used to convert 28V voltage into 12V to supply power to the storage module and the control module respectively.
8. A 40Gbps high-speed storage method applied to SAR satellites, characterized in that: The method comprises the following steps: S1, receiving the control instructions sent by the central computer through the CAN interface and processing the instructions; S2, four-channel GTY high-speed serdes interface receives SAR payload data and one LVDS low-speed serial interface receives navigation data, and processes the received high-speed data; S3, the FPGA module stores the received high-speed data into the storage module according to the control instruction; S4. Read the data from the storage module according to the control instruction and send it to the data transmission terminal through the data transmission interface.
9. A computer device comprising a memory and a processor, characterized in that A computer program is stored in the memory. When the processor runs the computer program stored in the memory, the processor executes the method according to claim 8.
10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the method according to claim 8 are implemented.
Citation Information
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