Storage design analysis method and device, medium and program product

Abstract

The invention relates to the technical field of integrated circuit design, and discloses a storage design analysis method and device, a medium and a program product. The method comprises the following steps: acquiring a hardware description language design file, and identifying each random access memory module in the hardware description language design file according to a preset grammar definition; abstracting each random access memory module into a structured model, wherein the structured model comprises a plurality of read-write port models; and obtaining target parameters matched with the read-write port models corresponding to the structured models, and obtaining memory classifications corresponding to the structured models according to the target parameters matched with the read-write port models. According to the scheme of the embodiment, efficient analysis of the storage design can be achieved in the RTL compiling stage, and the analysis efficiency of the storage design can be improved.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to an analysis method, device, medium and program product for storage design. Background Art

[0002] With the iteration of Field Programmable Gate Array (FPGA), the on-chip memory capacity is gradually increasing, and a large amount of external storage in the user's system-level chip design is realized by FPGA on-chip storage. Therefore, in the design of ultra-large multi-FPGA implementation, how to reasonably obtain and quickly parse the storage used in the design during the register transfer level (RTL) compilation stage, and reasonably allocate it to the corresponding FPGA device has become one of the key issues.

[0003] At present, the existing storage design analysis method usually uses logic synthesis tools to map the RTL-level hardware description language (HDL) code to the logic gate-level netlist or random access memory (RAM) and other macro units. However, for multi-dimensional array signals, the existing technology will generate additional decoders and data selectors, which will occupy a large amount of lookup table logic resources, resulting in low analysis efficiency. Summary of the invention

[0004] The present invention provides a storage design analysis method, device, medium and program product, which can realize efficient analysis of storage design in the RTL compilation stage and improve the analysis efficiency of storage design.

[0005] According to one aspect of the present invention, there is provided a storage design analysis method, comprising:

[0006] Obtaining a hardware description language design file, and identifying each random access memory module in the hardware description language design file according to a preset grammar definition;

[0007] Abstracting each random access memory module into a structured model, wherein the structured model includes a plurality of read-write port models;

[0008] The target parameters matched by each of the read / write port models corresponding to each of the structured models are obtained, and the memory classification corresponding to each of the structured models is obtained according to the target parameters matched by each of the read / write port models.

[0009] According to another aspect of the present invention, there is provided a storage design analysis device, comprising:

[0010] A storage identification module, used to obtain a hardware description language design file and identify each random access memory module in the hardware description language design file according to a preset grammar definition;

[0011] A storage abstraction module, used for abstracting each random access memory module into a structured model, wherein the structured model includes a plurality of read-write port models;

[0012] The parameter acquisition module is used to acquire the target parameters matched by each read / write port model corresponding to each structured model, and acquire the memory classification corresponding to each structured model according to the target parameters matched by each read / write port model.

[0013] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising:

[0014] at least one processor; and

[0015] a memory communicatively connected to the at least one processor; wherein,

[0016] The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the storage design analysis method described in any embodiment of the present invention.

[0017] According to another aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores a computer program, wherein the computer program is used to enable a processor to implement the storage design analysis method described in any embodiment of the present invention when executed.

[0018] According to another aspect of the present invention, a computer program product is provided, comprising a computer program, wherein when the computer program is executed by a processor, the storage design analysis method according to any one of the embodiments of the present invention is implemented.

[0019] The technical solution of the embodiment of the present invention is to obtain a hardware description language design file, and identify each random access memory module in the hardware description language design file according to a preset grammar definition; abstract each random access memory module into a structured model, the structured model includes multiple read-write port models; obtain the target parameters matched by each read-write port model corresponding to each structured model, and obtain the memory classification corresponding to each structured model according to the target parameters matched by the read-write port model; identify the RAM module in the HDL design file, and abstract the RAM module into a structured model composed of multiple read-write port models, and then identify the memory classification corresponding to each structured model according to the target parameters matched by each read-write port model, so that efficient analysis of the storage design can be achieved in the RTL compilation stage, and the analysis efficiency of the storage design can be improved.

[0020] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0022] Figure 1 is a flow chart of a storage design analysis method provided according to Embodiment 1 of the present invention;

[0023] Figure 2 is a schematic diagram of the structure of an analysis device for storage design provided according to Embodiment 2 of the present invention;

[0024] Figure 3 It is a schematic diagram of the structure of an electronic device for implementing the storage design analysis method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0025] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0026] It should be noted that the terms "first", "second", "target", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0027] Embodiment 1

[0028] Figure 1 A flowchart of a storage design analysis method is provided for the first embodiment of the present invention. This embodiment is applicable to the case where the storage used in the design is reasonably acquired and quickly parsed during the RTL compilation phase, and reasonably allocated to FPGA on-chip storage devices that conform to the behavioral logic. The method can be executed by a storage design analysis device, which can be implemented in the form of hardware and / or software. Typically, the storage design analysis device can be configured in an electronic device, such as a computer device or a server. Figure 1 As shown, the method includes:

[0029] S110, obtaining a hardware description language design file, and identifying each random access memory module in the hardware description language design file according to a preset grammar definition.

[0030] Among them, the hardware description language HDL design file can be a design file of FPGA, which can be based on the Verilog language and / or the System Verilog language. The Verilog language can be a language that describes the structure and behavior of digital system hardware in text form, and can be used to represent logic circuit diagrams, logic expressions, and logic functions performed by digital logic systems. The System Verilog language, based on the Verilog language, is more suitable for the design of reusable intellectual property cores and reusable intellectual property cores for verification, as well as the design and verification of very large system-level intellectual property cores. The preset syntax definition can be the syntax definition of RAM in the Verilog language or the System Verilog language.

[0031] In this embodiment, for the input HDL design file, the RAM module that meets the syntax definition can be automatically identified in the HDL design file according to the syntax definition of RAM in the preset Verilog and SystemVerilog languages, combined with the register behavior and description language. The RAM module can be the design code of the RAM.

[0032] Optionally, identifying each random access memory module in the hardware description language design file according to a preset grammar definition may include:

[0033] Parsing the hardware description language design file to obtain a hierarchical tree data structure;

[0034] The target pointer in the hierarchical tree data structure is traversed through a pre-registered callback function to obtain each random access memory module that complies with a preset grammar definition.

[0035] In this embodiment, the HDL design file can be parsed to obtain the FPGA design description, and a hierarchical tree data structure can be established based on the FPGA design description (such as the calling relationship between objects, etc.). The hierarchical tree data structure is used as an operation data base for further syntax processing, and may include a Module pointer, an Instance pointer, a ModuleItem pointer, a Parent pointer, a child pointer, a callback function pointer, etc. Then, the Net information under the Module pointer can be traversed through a pre-registered callback function to identify a data module that conforms to the syntax definition of RAM in the Verilog / SystemVerilog language defined by IEEE, and the data module is marked as a RAM module.

[0036] Optionally, parsing the hardware description language design file to obtain a hierarchical tree data structure may include:

[0037] According to the hardware description language design file, obtaining a syntax tree memory structure;

[0038] The syntax tree memory structure is iteratively traversed, and the hierarchical tree data structure is established according to the traversal result.

[0039] Specifically, the HDL design file can be input into a preset parser, and the syntax tree memory structure output by the parser is obtained and saved in the computer memory. Among them, the syntax tree memory structure is mainly used to store the logical relationship, logical hierarchy and specific syntax expression of the hardware integrated circuit design described in the input HDL design file. Then, the syntax tree memory structure in the computer memory can be traversed in an iterative traversal manner to obtain various types of pointer data and the logical relationship between the pointer data. Finally, a new hierarchical tree data structure can be established based on the data obtained by the iterative traversal.

[0040] The advantage of the above settings is that the hierarchical relationship of the data structure can be displayed more intuitively, which can improve the analysis efficiency of storage design.

[0041] S120, abstracting each of the random access memory modules into a structured model, wherein the structured model includes a plurality of read-write port models.

[0042] In this embodiment, the design description of each determined RAM module can be extracted, and the behavior logic of each RAM module can be identified based on the extracted design description. Then, each RAM module can be modeled based on the behavior logic of each RAM module to generate a structured model of RAM. Among them, the structured model can be composed of multiple read-write port models and a storage container model as a main body, and the read-write port model can include a read port model and a write port model.

[0043] Optionally, abstracting each random access memory module into a structured model may include:

[0044] A semantic behavior analysis is performed on each of the random access memory modules, and each of the random access memory modules is abstracted into a structured model according to the result of the semantic behavior analysis.

[0045] Specifically, when abstracting each RAM module, a semantic behavior analysis can be performed on each RAM module to analyze its read and write behaviors on the RAM net, including but not limited to syntax such as always block, always statement, and assignment. Then, a corresponding read and write port model can be established based on the corresponding read and write behaviors of each RAM module, and the read and write port model and the storage container model together form a structured model of the RAM.

[0046] The advantage of the above setting is that mathematical modeling of the RAM module can be realized, and the accuracy of the modeling can be improved.

[0047] S130, obtaining target parameters matched by each read / write port model corresponding to each structured model, and obtaining a memory classification corresponding to each structured model according to the target parameters matched by each read / write port model.

[0048] Among them, the target parameters may include at least one of upstream and downstream logic, read-write mode, behavior mode, fan-in and fan-out logic, and enable logic. In this embodiment, the established read-write port model can be further analyzed, and the target parameters such as clock information, enable signal, control signal, fan-out register, fan-in signal, etc. that each read-write port model matches can be searched from the HDL design file with the structured model as the target. Then, the memory classification corresponding to each structured model can be determined based on the target parameters matched by each read-write port model and the preset memory classification rules. This embodiment does not specifically limit the memory classification.

[0049] Specifically, according to the target parameters matched by each read-write port model, the memory classification corresponding to each structured model is obtained, which may include: according to the current number of clock domains, whether the read-write port models are in the same clock domain, whether the read-write port models are symmetrical, and whether the fan-out of the read port model and the fan-in of the write port model are sequential logic, the memory classification corresponding to each structured model is obtained. For example, the correspondence between various parameters and memory classifications can be preset, such as if the number of clock domains is in the numerical interval [a, b], the read-write port models are in the same clock domain, the read-write port models are symmetrical, and the fan-out of the read port model and the fan-in of the write port model are sequential logic, then the corresponding memory classification A; thus, after obtaining the current parameters, the current memory classification can be obtained by searching for the matching preset correspondence.

[0050] The technical solution of the embodiment of the present invention is to obtain a hardware description language design file, and identify each random access memory module in the hardware description language design file according to a preset grammar definition; abstract each random access memory module into a structured model, the structured model includes multiple read-write port models; obtain the target parameters matched by each read-write port model corresponding to each structured model, and obtain the memory classification corresponding to each structured model according to the target parameters matched by the read-write port model; identify the RAM module in the HDL design file, and abstract the RAM module into a structured model composed of multiple read-write port models, and then identify the memory classification corresponding to each structured model according to the target parameters matched by each read-write port model, so that efficient analysis of the storage design can be achieved in the RTL compilation stage, and the analysis efficiency of the storage design can be improved.

[0051] In an optional implementation of this embodiment, after acquiring the memory classification corresponding to each of the structured models according to the target parameters matched by each of the read / write port models, the following may also be included:

[0052] According to the memory classification corresponding to each of the structured models, each of the structured models is mapped to an on-chip memory device of a field programmable logic gate array.

[0053] In this embodiment, after determining the memory classification corresponding to the structured model of each RAM, a mapping relationship between the structured model and the on-chip memory device of the FPGA can be established according to the memory classification. Typically, the current structured model can be mapped to an on-chip memory device belonging to the same memory classification as the current structured model.

[0054] The advantage of the above setting is that the correspondence between the structured model and the on-chip memory device can be clearly defined, which can provide support for understanding and modifying the FPGA design.

[0055] Optionally, after mapping each structured model to the on-chip memory device of the FPGA, resource calculation can be performed based on the mapping result, and the calculation result can be used to guide the prototype verification segmentation, and corresponding guidance information can be added to the corresponding Verilog / SystemVerilog description to guide the synthesis result.

[0056] In this embodiment, after completing the parsing and compilation of the RAM part module in the hardware description language Verilog / System Verilog, through RAM extraction, compilation, identification, classification and calculation, detailed and accurate RAM distribution and usage can be extracted from the Verilog / System Verilog design, thereby assisting users or tools to complete further modifications to the design, or providing support for prototype and simulation tools.

[0057] Embodiment 2

[0058] Figure 2 A schematic diagram of a storage design analysis device provided in the second embodiment of the present invention. Figure 2 As shown, the device includes: a storage identification module 210, a storage abstraction module 220 and a parameter acquisition module 230; wherein,

[0059] A storage identification module 210, used to obtain a hardware description language design file and identify each random access memory module in the hardware description language design file according to a preset grammar definition;

[0060] A storage abstraction module 220, used for abstracting each of the random access memory modules into a structured model, wherein the structured model includes a plurality of read-write port models;

[0061] The parameter acquisition module 230 is used to acquire the target parameters matched by each read / write port model corresponding to each structured model, and acquire the memory classification corresponding to each structured model according to the target parameters matched by each read / write port model.

[0062] The technical solution of the embodiment of the present invention is to obtain a hardware description language design file, and identify each random access memory module in the hardware description language design file according to a preset grammar definition; abstract each random access memory module into a structured model, the structured model includes multiple read-write port models; obtain the target parameters matched by each read-write port model corresponding to each structured model, and obtain the memory classification corresponding to each structured model according to the target parameters matched by the read-write port model; identify the RAM module in the HDL design file, and abstract the RAM module into a structured model composed of multiple read-write port models, and then identify the memory classification corresponding to each structured model according to the target parameters matched by each read-write port model, so that efficient analysis of the storage design can be achieved in the RTL compilation stage, and the analysis efficiency of the storage design can be improved.

[0063] Optionally, a storage identification module 210 is specifically used to parse the hardware description language design file to obtain a hierarchical tree data structure;

[0064] The target pointer in the hierarchical tree data structure is traversed through a pre-registered callback function to obtain each random access memory module that complies with a preset grammar definition.

[0065] Optionally, the storage identification module 210 is specifically used to obtain the syntax tree memory structure according to the hardware description language design file;

[0066] The syntax tree memory structure is iteratively traversed, and the hierarchical tree data structure is established according to the traversal result.

[0067] Optionally, the hardware description language design file is based on the Verilog language and / or the System Verilog language.

[0068] Optionally, the storage abstraction module 220 is specifically used to perform semantic behavior analysis on each of the random access memory modules, and abstract each of the random access memory modules into a structured model based on the semantic behavior analysis result.

[0069] Optionally, the storage design analysis device also includes:

[0070] The model mapping module is used to map each of the structured models to an on-chip memory device of a field programmable logic gate array according to the memory classification corresponding to each of the structured models.

[0071] Optionally, the target parameter may include at least one of upstream and downstream logic, read / write mode, behavior mode, fan-in and fan-out logic, and enable logic.

[0072] The storage design analysis device provided in the embodiment of the present invention can execute the storage design analysis method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0073] In the technical solution of the present disclosure, the collection, storage, use, processing, transmission, provision and disclosure of user personal information involved are in compliance with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0074] Embodiment 3

[0075] Figure 3 A schematic diagram of the structure of an electronic device 30 that can be used to implement an embodiment of the present invention is shown. The electronic device 30 is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device 30 can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein.

[0076] like Figure 3 As shown, the electronic device 30 includes at least one processor 31, and a memory connected to the at least one processor 31, such as a read-only memory (ROM) 32, a random access memory (RAM) 33, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 31 can perform various appropriate actions and processes according to the computer program stored in the read-only memory 32 or the computer program loaded from the storage unit 38 to the random access memory 33. In the RAM 33, various programs and data required for the operation of the electronic device 30 can also be stored. The processor 31, the ROM 32 and the RAM 33 are connected to each other through a bus 34. The input / output (I / O) interface 35 is also connected to the bus 34.

[0077] A number of components in the electronic device 30 are connected to the I / O interface 35, including: an input unit 36, such as a keyboard, a mouse, etc.; an output unit 37, such as various types of displays, speakers, etc.; a storage unit 38, such as a disk, an optical disk, etc.; and a communication unit 39, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 39 allows the electronic device 30 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0078] The processor 31 may be a variety of general and / or dedicated processing components with processing and computing capabilities. Some examples of the processor 31 include, but are not limited to, a central processing unit, a graphics processing unit, various dedicated artificial intelligence computing chips, various processors running machine learning model algorithms, digital signal processors, and any appropriate processors, controllers, microcontrollers, etc. The processor 31 executes the various methods and processes described above, such as the analysis method for storage design.

[0079] In some embodiments, the analysis method of storage design may be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit 38. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 30 via the ROM 32 and / or the communication unit 39. When the computer program is loaded into the RAM 33 and executed by the processor 31, one or more steps of the analysis method of storage design described above may be performed. Alternatively, in other embodiments, the processor 31 may be configured to execute the analysis method of storage design in any other appropriate manner (e.g., by means of firmware).

[0080] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays, application specific integrated circuits, application specific standard products, systems on a chip, load programmable logic devices, computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0081] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0082] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, device, or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory, a read-only memory, an erasable programmable read-only memory, an optical fiber, a portable compact disk read-only memory, an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0083] To provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device 30 having: a display device (e.g., a cathode ray tube or a liquid crystal display) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or a trackball) through which the user can provide input to the electronic device 30. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0084] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local area networks, wide area networks, blockchain networks, and the Internet.

[0085] A computing system may include clients and servers. Clients and servers are generally remote from each other and typically interact through a communication network. The relationship of client and server is generated by computer programs running on respective computers and having a client-server relationship to each other. The server may be a cloud server.

[0086] This embodiment may also include a computer program product, which includes a computer program. When the computer program is executed by a processor, it implements the storage design analysis method provided by any embodiment of the present invention.

[0087] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0088] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A storage design analysis method, characterized in that: include: Obtaining a hardware description language design file, and identifying each random access memory module in the hardware description language design file according to a preset grammar definition; Abstracting each random access memory module into a structured model, wherein the structured model includes a plurality of read-write port models; The target parameters matched by each of the read / write port models corresponding to each of the structured models are obtained, and the memory classification corresponding to each of the structured models is obtained according to the target parameters matched by each of the read / write port models.

2. The method according to claim 1, characterized in that: According to the preset grammar definition, each random access memory module is identified in the hardware description language design file, including: Parsing the hardware description language design file to obtain a hierarchical tree data structure; The target pointer in the hierarchical tree data structure is traversed through a pre-registered callback function to obtain each random access memory module that complies with a preset grammar definition.

3. The method according to claim 2, characterized in that The hardware description language design file is parsed to obtain a hierarchical tree data structure, including: According to the hardware description language design file, obtaining a syntax tree memory structure; The syntax tree memory structure is iteratively traversed, and the hierarchical tree data structure is established according to the traversal result.

4. The method according to any one of claims 1 to 3, characterized in that The hardware description language design files are based on the Verilog language and / or the System Verilog language.

5. The method according to claim 1, characterized in that: Each of the random access memory modules is abstracted into a structured model, including: A semantic behavior analysis is performed on each of the random access memory modules, and each of the random access memory modules is abstracted into a structured model according to the result of the semantic behavior analysis.

6. The method according to claim 1, characterized in that After obtaining the memory classification corresponding to each of the structured models according to the target parameters matched by each of the read / write port models, the method further includes: According to the memory classification corresponding to each of the structured models, each of the structured models is mapped to an on-chip memory device of a field programmable logic gate array.

7. The method according to claim 1 or 6, characterized in that: The target parameter includes at least one of upstream and downstream logic, read / write mode, behavior mode, fan-in and fan-out logic, and enable logic.

8. An electronic device, characterized in that: The electronic device comprises: at least one processor, and a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can perform the storage design analysis method according to any one of claims 1 to 7.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and the computer program is used to enable a processor to implement the storage design analysis method according to any one of claims 1 to 7 when the computer program is executed.

10. A computer program product, characterized in that The invention comprises a computer program, which, when executed by a processor, implements the storage design analysis method according to any one of claims 1 to 7.

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