Method, device and equipment for determining thread calling information

Abstract

The invention provides a method, device and equipment for determining thread calling information, and the method comprises the steps: determining the thread state of a target thread, the thread state comprising a kernel state and a user state; determining a target processor CPU core corresponding to the target thread, wherein the target CPU core is used for executing the target thread; according to the thread state and the target CPU core, call information of the target thread is determined, and the call information comprises function identifiers of the multi-layer functions called by the target thread and a call sequence among the multi-layer functions. And the flexibility of determining the thread calling information is improved.

Description

Technical Field

[0001] The present application relates to the computer field, and in particular to a method, device and equipment for determining thread call information. Background Art

[0002] In a computer, an application can be executed through multiple threads. When an exception occurs in any thread, the thread call information of the thread can be obtained to find the cause of the exception.

[0003] In the related art, when an exception occurs in a thread, the thread is usually interrupted and a preset code is executed to obtain the thread call information of the thread. However, in the above method, the preset code is usually written in the development stage of the application. If an unexpected exception occurs in the thread, the preset code cannot be executed to obtain the thread call information of the thread, resulting in poor flexibility in determining the thread call information. Summary of the invention

[0004] Multiple aspects of the present application provide a method, apparatus, and device for determining thread call information, so as to improve the flexibility of determining thread call information.

[0005] In a first aspect, an embodiment of the present application provides a method for determining thread call information, including:

[0006] Determine the thread state of the target thread, wherein the thread state includes a kernel state and a user state;

[0007] Determine a target processor CPU core corresponding to a target thread, wherein the target CPU core is used to execute the target thread;

[0008] The calling information of the target thread is determined according to the thread state and the target CPU core, wherein the calling information includes function identifiers of the multi-layer functions called by the target thread and a calling sequence between the multi-layer functions.

[0009] In a possible implementation manner, determining the call information of the target thread according to the thread state and the target CPU core includes:

[0010] If the thread state is the user state, obtaining values ​​of multiple MSR registers of specific models corresponding to the target CPU core, and determining the call information according to the values ​​of the multiple MSR registers;

[0011] If the thread state is the kernel state, the values ​​of multiple general registers of the target thread in the user state are obtained, and the call information is determined according to the values ​​of the multiple general registers of the target thread in the user state.

[0012] In a possible implementation manner, obtaining values ​​of multiple MSR registers corresponding to the target CPU core includes:

[0013] Determine an index register corresponding to the target CPU core, and determine at least one address register, wherein the index register and the address register are MSR registers respectively;

[0014] Obtaining a value of the index register and a value of the at least one address register;

[0015] Determining the values ​​of the plurality of MSR registers includes the value of the index register and the value of the at least one address register.

[0016] In a possible implementation manner, determining at least one address register includes:

[0017] determining a target register location in the index register;

[0018] According to the target register position, determining a first target register from a plurality of address registers corresponding to the target CPU core, wherein the first target register is an address register used by the target CPU core to record a function call relationship for the last time;

[0019] Determine M second target registers from a plurality of address registers used by the target CPU core, wherein the values ​​in the second target registers are non-zero values;

[0020] It is determined that the at least one address register includes the first target register and the M second target registers.

[0021] In a possible implementation manner, determining the call information according to the values ​​of the multiple MSR registers includes:

[0022] Determine a source address of the multi-layer function according to the value of the first target register and the values ​​of the M second target registers;

[0023] Determine a function identifier of the multi-layer function according to the source address of the multi-layer function;

[0024] Determining a calling order of the multi-layer function according to an arrangement order of the first target register and the M second target registers;

[0025] The calling information includes the function identifier of the multi-layer function and the calling order of the multi-layer function.

[0026] In a possible implementation manner, before obtaining the values ​​of multiple specific model MSR registers corresponding to the target CPU core, the method further includes:

[0027] After the target thread is started, a function call recording function of the target CPU core is enabled;

[0028] When the target CPU core executes the first-layer function call instruction, the source address of the first-layer function is stored in the address register with a register number of K, and the value in the index register is updated to K, where K is an integer greater than or equal to 0, and the address register with a register number of K is the first address register used by the target CPU core in the current function call recording process;

[0029] When the target CPU core executes the i+1th layer function call instruction, the source address of the i+1th layer function is stored in the address register with register number K+1, and the value in the index register is updated to K+1;

[0030] Here, the value of i is 1, 2, ... in sequence until the function call recording function of the target CPU core is turned off.

[0031] In a possible implementation manner, enabling the function call recording function of the target CPU core includes:

[0032] Setting the value in the flag register corresponding to the target CPU core to a first preset value to enable the function call recording function of the target CPU core, the flag register being an MSR register;

[0033] Disabling the function call recording function of the target CPU core includes:

[0034] The value in the flag MSR register is set to a second preset value to disable the function call recording function of the target CPU core.

[0035] In a possible implementation manner, for any one MRS register of the index register and the at least one address register; obtaining the value of the MSR register includes:

[0036] Obtain a first system file of the target CPU core, wherein the first system file includes a method for reading and writing the multiple MSR registers in user mode;

[0037] According to the first system file and the identifier of the MSR register, the value of the MSR register is obtained.

[0038] In a possible implementation manner, obtaining values ​​of a plurality of general registers of the target thread in user mode includes:

[0039] Determine the kernel stack corresponding to the target thread;

[0040] The values ​​of a plurality of general registers of the target thread in the user state are obtained in the kernel stack.

[0041] In a possible implementation manner, obtaining values ​​of a plurality of general registers of the target thread in the user state in the kernel stack includes:

[0042] Get the symbol table description file of the operating system kernel;

[0043] Determine an address calculation formula corresponding to the operating system kernel, where the address calculation formula is used to calculate the kernel stack address of the target thread;

[0044] According to the symbol table description file and the address calculation formula, the values ​​of multiple general registers of the target thread in the user state are obtained in the kernel stack.

[0045] In a possible implementation manner, obtaining values ​​of multiple general registers of the target thread in user mode in the kernel stack according to the symbol table description file and the address calculation formula includes:

[0046] Calculate the target memory address according to the symbol table description file and the address calculation formula;

[0047] According to the target memory address, a target memory is determined in the kernel stack, and values ​​of a plurality of general registers of the target thread in user mode are stored in the target memory.

[0048] In a possible implementation manner, determining the call information according to the values ​​of a plurality of general registers of the target thread in the user state includes:

[0049] Determine a user stack corresponding to the target thread;

[0050] Determining a function address of a latest function according to values ​​of a plurality of general registers of the target thread in user mode;

[0051] Determining a starting position in the user stack according to a function address of the latest function;

[0052] From the starting position, in the order of stack addresses from low to high, obtaining the return address of the multi-layer function in the user stack;

[0053] The calling information is determined according to the function address of the latest function and the return address of the multi-layer function.

[0054] In a second aspect, an embodiment of the present application provides a thread call information determination device, comprising: a first determination module, a second determination module and a third determination module, wherein:

[0055] The first determination module is used to determine the thread state of the target thread, and the thread state includes a kernel state and a user state;

[0056] The second determination module is used to determine a target processor CPU core corresponding to the target thread, and the target CPU core is used to execute the target thread;

[0057] The third determination module is used to determine the calling information of the target thread according to the thread state and the target CPU core, wherein the calling information includes the function identifiers of the multi-layer functions called by the target thread and the calling order between the multi-layer functions.

[0058] In a possible implementation manner, the third determining module is specifically configured to:

[0059] If the thread state is the user state, obtaining values ​​of multiple MSR registers of specific models corresponding to the target CPU core, and determining the call information according to the values ​​of the multiple MSR registers;

[0060] If the thread state is the kernel state, the values ​​of multiple general registers of the target thread in the user state are obtained, and the call information is determined according to the values ​​of the multiple general registers of the target thread in the user state.

[0061] In a possible implementation manner, the third determining module is specifically configured to:

[0062] Determine an index register corresponding to the target CPU core, and determine at least one address register, wherein the index register and the address register are MSR registers respectively;

[0063] Obtaining a value of the index register and a value of the at least one address register;

[0064] Determining the values ​​of the plurality of MSR registers includes the value of the index register and the value of the at least one address register.

[0065] In a possible implementation manner, the third determining module is specifically configured to:

[0066] determining a target register location in the index register;

[0067] According to the target register position, determining a first target register from a plurality of address registers corresponding to the target CPU core, wherein the first target register is an address register used by the target CPU core to record a function call relationship for the last time;

[0068] Determine M second target registers from a plurality of address registers used by the target CPU core, wherein the values ​​in the second target registers are non-zero values;

[0069] It is determined that the at least one address register includes the first target register and the M second target registers.

[0070] In a possible implementation manner, the third determining module is specifically configured to:

[0071] Determine a source address of the multi-layer function according to the value of the first target register and the values ​​of the M second target registers;

[0072] Determine a function identifier of the multi-layer function according to the source address of the multi-layer function;

[0073] Determining a calling order of the multi-layer function according to an arrangement order of the first target register and the M second target registers;

[0074] The calling information includes the function identifier of the multi-layer function and the calling order of the multi-layer function.

[0075] In a possible embodiment, the device further includes a setting module and a storage module, wherein:

[0076] The setting module is used to enable the function call recording function of the target CPU core after the target thread is started;

[0077] The storage module is used to, when the target CPU core executes the first-layer function call instruction, store the source address of the first-layer function in the address register with a register number of K, and update the value in the index register to K, where K is an integer greater than or equal to 0, and the address register with a register number of K is the first address register used by the target CPU core in the current function call recording process;

[0078] The storage module is used to store the source address of the i+1th layer function in the address register with register number K+1 when the target CPU core executes the i+1th layer function call instruction, and update the value in the index register to K+1;

[0079] Here, the value of i is 1, 2, ... in sequence until the function call recording function of the target CPU core is turned off.

[0080] In a possible implementation manner, the setting module is specifically used to:

[0081] Setting the value in the flag register corresponding to the target CPU core to a first preset value to enable the function call recording function of the target CPU core, the flag register being an MSR register;

[0082] To disable the function call recording function of the target CPU core, the setting module is specifically used to:

[0083] The value in the flag MSR register is set to a second preset value to disable the function call recording function of the target CPU core.

[0084] In a possible implementation manner, for any one MRS register among the index register and the at least one address register; the third determination module is specifically configured to:

[0085] Obtain a first system file of the target CPU core, wherein the first system file includes a method for reading and writing the multiple MSR registers in user mode;

[0086] According to the first system file and the identifier of the MSR register, the value of the MSR register is obtained.

[0087] In a possible implementation manner, the third determining module is specifically configured to:

[0088] Determine the kernel stack corresponding to the target thread;

[0089] The values ​​of a plurality of general registers of the target thread in the user state are obtained in the kernel stack.

[0090] In a possible implementation manner, the third determining module is specifically configured to:

[0091] Get the symbol table description file of the operating system kernel;

[0092] Determine an address calculation formula corresponding to the operating system kernel, where the address calculation formula is used to calculate the kernel stack address of the target thread;

[0093] According to the symbol table description file and the address calculation formula, the values ​​of multiple general registers of the target thread in the user state are obtained in the kernel stack.

[0094] In a possible implementation manner, the third determining module is specifically configured to:

[0095] Calculate the target memory address according to the symbol table description file and the address calculation formula;

[0096] According to the target memory address, a target memory is determined in the kernel stack, and values ​​of a plurality of general registers of the target thread in user mode are stored in the target memory.

[0097] In a possible implementation manner, the third determining module is specifically configured to:

[0098] Determine a user stack corresponding to the target thread;

[0099] Determining a function address of a latest function according to values ​​of a plurality of general registers of the target thread in user mode;

[0100] Determining a starting position in the user stack according to a function address of the latest function;

[0101] From the starting position, in the order of stack addresses from low to high, obtaining the return address of the multi-layer function in the user stack;

[0102] The calling information is determined according to the function address of the latest function and the return address of the multi-layer function.

[0103] In a third aspect, an embodiment of the present application provides an electronic device, including: a memory and a processor;

[0104] The memory stores computer-executable instructions;

[0105] The processor executes the computer-executable instructions stored in the memory, so that the processor executes the method for determining thread call information as described in any one of the first aspects.

[0106] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer execution instructions, and when the computer execution instructions are executed by a processor, they are used to implement the method for determining thread call information described in any one of the first aspects.

[0107] In a fifth aspect, an embodiment of the present application provides a computer program product, including a computer program, which, when executed by a processor, implements the method for determining thread call information shown in any one of the first aspects.

[0108] The embodiments of the present application provide a method, device and equipment for determining thread call information. The electronic device can determine the thread state of the target thread and the target CPU core corresponding to the target thread, and then determine the call information of the target thread according to the thread state and the target CPU core. Since the call information of the target thread can be determined in the event of any abnormality in the target thread, it is not limited to the preset code; and the stack backtrace can be performed using hardware characteristics or kernel design without interrupting the execution of the target thread, which comprehensively improves the flexibility of determining the thread call information; and achieves high-frequency and efficient tracking of the execution process of the target thread, determines the call information of the target thread and archives it. After an abnormal scenario occurs, the call information of the target thread during the abnormal period can be used to assist in finding the cause of the fault and eliminate the safety hazards of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0109] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0110] Figure 1 A schematic diagram of a scenario provided for an exemplary embodiment of the present application;

[0111] Figure 2 A flowchart of a method for determining thread call information provided by an exemplary embodiment of the present application;

[0112] Figure 3 A schematic diagram of the structure of a user stack provided for an exemplary embodiment of the present application;

[0113] Figure 4 A flowchart of another method for determining thread call information provided by an exemplary embodiment of the present application;

[0114] Figure 5 A process diagram of a method for determining thread call information provided by an exemplary embodiment of the present application;

[0115] Figure 6 A flowchart of another method for determining thread call information provided by an exemplary embodiment of the present application;

[0116] Figure 7 A process diagram of another method for determining thread call information provided by an exemplary embodiment of the present application;

[0117] Figure 8 A schematic diagram of the structure of a device for determining thread call information provided by an exemplary embodiment of the present application;

[0118] Fig. 9A schematic structural diagram of an electronic device provided for an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0119] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant laws, regulations and standards, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0120] In order to make the purpose, technical solution and advantages of the present application clearer, the technical solution of the present application will be clearly and completely described below in combination with the specific embodiments of the present application and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application.

[0121] Figure 1 A schematic diagram of a scenario provided for an exemplary embodiment of the present application. Figure 1 The processor (Central Processing Unit, CPU) may include multiple CPU cores. For example, the multiple CPU cores may be CPU core 1, CPU core 2, ..., CPU core n, (n is an integer greater than or equal to 1).

[0122] Different CPU cores can execute different threads. For example, CPU core 1 can execute thread 1, and CPU core 2 can execute thread 2.

[0123] Threads can have corresponding thread states, including user state and kernel state. User state is a running state with a lower privilege level; kernel state is a running state with a higher privilege level. For example, the thread state of thread 1 can be kernel state, and the thread state of thread 2 can be user state.

[0124] When it is necessary to obtain the call information of the target thread, the thread state of the target thread and the target CPU core executing the target thread can be determined, and then the call information of the target thread can be determined according to the thread state of the target thread and the target CPU core. For example, if the target thread is thread 1, if it is determined that the thread state of thread 1 is kernel state, and if the target CPU core executing thread 1 is CPU core 1, the call information of thread 1 can be determined by accessing the kernel state memory.

[0125] In the related art, when an exception occurs in a thread, the thread is usually interrupted and a preset code is executed to obtain the thread call information of the thread. However, in the above method, the preset code is usually written in the development stage of the application. If an unexpected exception occurs in the thread, the preset code cannot be executed to obtain the thread call information of the thread, resulting in poor flexibility in determining the thread call information.

[0126] In the embodiment of the present application, the thread state of the target thread and the target CPU core corresponding to the target thread can be determined, and the call information of the target thread can be determined according to the thread state and the target CPU core. Since the call information of the target thread can be determined in the event of any abnormality of the target thread, it is not limited to the preset code, thereby improving the flexibility of determining the thread call information.

[0127] The technical solutions shown in the present application are described in detail below through specific embodiments. It should be noted that the following embodiments can exist independently or in combination with each other, and the same or similar contents will not be described repeatedly in different embodiments.

[0128] Figure 2 A flowchart of a method for determining thread call information provided by an exemplary embodiment of the present application. Figure 2 , the method may include:

[0129] S201: Determine the thread state of the target thread.

[0130] The execution subject of the embodiment of the present application may be an electronic device, or a device for determining thread call information set in the electronic device. The device for determining thread call information may be implemented by software, or by a combination of software and hardware. The device for determining thread call information may be a processor in the electronic device. For ease of understanding, the following description is made by taking the execution subject as an electronic device as an example.

[0131] It should be noted that the technical solution in this application can also be executed by a monitoring thread in the process where the target thread is located.

[0132] A process may include multiple threads. A thread is the smallest unit for executing an application program. For example, a process may include 10 threads, namely thread 1, thread 2, ..., thread 10. Among them, thread 10 may be a monitoring thread, and the monitoring thread may execute the technical solution of the present application on any other thread in the process.

[0133] Optionally, the thread state may include kernel state and user state.

[0134] Kernel state refers to the state of a thread after it enters kernel state to perform specific operations or is scheduled by the operating system, and has a higher level of privileges; user state refers to the state of a thread when it is executed in user state, and has a lower level of privileges.

[0135] Optionally, if the thread is executed in user state, the thread state of the thread can be determined to be user state; if the thread is executed in kernel state or is scheduled by the operating system to enter a dormant state, the thread state of the thread can be determined to be kernel state.

[0136] For example, if thread 1 is executed in user state, the thread state of thread 1 is user state; if thread 2 is executed in kernel state, the thread state of thread 2 is kernel state.

[0137] For any thread, the thread can have a corresponding user stack or kernel stack.

[0138] Next, combine Figure 3 , describe the user stack.

[0139] Figure 3 A schematic diagram of the structure of a user stack provided for an exemplary embodiment of the present application. Figure 3 , the user stack may include stack frames corresponding to multiple layers of functions. For example, thread 1 is a 3-layer function call, namely function 1, function 2 and function 3, then the user stack corresponding to thread 1 may include stack frames corresponding to function 1, function 2 and function 3 respectively.

[0140] The stack is the memory space opened in the user state during the function call process. It can be divided into multiple stack frames according to the calling relationship. Each stack frame includes the address returned to the previous stack frame, local variables, etc. For example, the stack frame corresponding to function 2 can store the address returned to function 1, local variables of function 2, etc.

[0141] The user stack grows from the bottom to the top, with the stack address at the bottom being the high address and the stack address at the top being the low address. For example, the target thread has the following calling relationship: function 1 calls function 2, function 2 calls function 3, then function 3 is the top of the user stack corresponding to the target thread.

[0142] It should be noted that the structure of the kernel stack is similar to that of the user stack.

[0143] S202: Determine the target processor CPU core corresponding to the target thread.

[0144] The target CPU core refers to a CPU core used to execute the target thread.

[0145] In an optional embodiment, the target CPU core corresponding to the target thread may be determined in the following manner: obtaining a target thread state description file corresponding to the target thread; and determining the target CPU core corresponding to the target thread according to the target thread state description file.

[0146] The target thread state description file may include the running information of the target thread. For example, the running information may include the running time of the target thread, the CPU core executing the target thread, etc.

[0147] For example, if the thread identification (Identity document, ID) of the target thread is t, the corresponding target thread status description file under Linux is the / proc / t / stat file. If the target thread is running on CPU core 1, the target thread status description file can be read and parsed, and the target CPU core corresponding to thread t can be determined in the target thread status description file as CPU core 1.

[0148] S203: Determine the call information of the target thread according to the thread state and the target CPU core.

[0149] The target thread can be a multi-layer function call. For example, the target thread can call function main, function main calls function A, and function A calls function B.

[0150] The call information may include the function identifiers of the multi-layer functions called by the target thread, and the calling order between the multi-layer functions. For example, the call information may include the identifiers of the first layer function, the second layer function, and the third layer function, and the calling relationship is: the first layer function calls the second layer function, and the second layer function calls the third layer function.

[0151] Optionally, the calling information of the target thread is determined according to the thread state and the target CPU core, which may include the following two cases:

[0152] Case 1: The thread state is user mode.

[0153] In this case, values ​​of multiple model specific registers (MSR) corresponding to the target CPU core may be obtained, and the calling information may be determined according to the values ​​of the multiple MSR registers.

[0154] The MSR register refers to the register in the x86 architecture processor that is used to control CPU operation, function switches, debugging, tracking program execution, monitoring CPU performance, etc.

[0155] For any CPU core, a plurality of MSR registers may be configured in the CPU core. For example, 64 MSR registers may be configured in CPU core 1.

[0156] For example, if the target thread is thread t, the state of thread t is user state, and the target CPU core is CPU core 1, the values ​​of multiple MSR registers corresponding to CPU core 1 can be determined, and the calling information of thread t can be determined based on the values ​​of the multiple MSR registers.

[0157] Case 2: The thread state is kernel state.

[0158] In this case, the values ​​of multiple general registers of the target thread in the user state may be obtained, and the call information may be determined according to the values ​​of the multiple general registers of the target thread in the user state.

[0159] For example, if the target thread is thread t and the state of thread t is kernel state, the values ​​of multiple general registers of thread t in user state can be obtained, and the calling information of thread t can be determined according to the values ​​of multiple general registers of thread t in user state.

[0160] For any thread, the technical solution of this application can be executed to track the execution process of the thread with high frequency and high efficiency, determine the call information of the thread and archive it. After an abnormal scenario occurs, the call information of the thread during the abnormal period can be used to assist in finding the cause of the fault and eliminate the safety risks of the system.

[0161] In the embodiment of the present application, the electronic device can determine the thread state of the target thread and the target CPU core corresponding to the target thread, and then can determine the call information of the target thread according to the thread state and the target CPU core. Since the call information of the target thread can be determined in the event of any abnormality of the target thread, it is not limited to the preset code, thereby improving the flexibility of determining the thread call information.

[0162] Below, in Figure 2 Based on the embodiment shown, combined Figure 4 , a method for determining the calling information of a thread when the thread state is in user state is described in detail; combined with Figure 6 , a method for determining the calling information of a thread when the thread state of the thread is in kernel state is described in detail.

[0163] Figure 4 A flowchart of another method for determining thread call information provided by an exemplary embodiment of the present application. Figure 4 , the method comprising:

[0164] S401: Determine the thread state of the target thread.

[0165] S402: Determine the target processor CPU core corresponding to the target thread.

[0166] It should be noted that for the execution processes of steps S401 to S402, reference can be made to the execution processes of steps S201 to S202, and no further elaboration will be provided here.

[0167] S403. After the target thread is started, enable the function call recording function of the target CPU core.

[0168] In an optional embodiment, the value in the flag register of the target CPU core can be set to a first preset value to enable the function call recording function of the target CPU core.

[0169] Optionally, the flag register can be an MSR register. For example, the flag register can be an IA32_DEBUGCTL register.

[0170] Optionally, the first preset value can be 1, which is used to indicate enabling the function call recording function.

[0171] In an optional embodiment, the identifier of the flag register can be obtained from the CPU hardware manual, and based on the identifier of the flag register, the way to read and write the flag register in the user state can be determined in the first system file of the target CPU core. Furthermore, based on the way to read and write the flag register, the value of the flag register can be set to the first preset value.

[0172] The CPU hardware manual can include the identifiers of multiple MSR registers. For example, if there are 64 MSR registers, the CPU hardware manual can include the identifiers of these 64 MSR registers.

[0173] The first system file can be a file used to operate multiple MSR registers in the user state. The first system file can include the ways to read and write multiple MSR registers in the user state. For example, the first system file can be / dev / cpu / <CPU core> / msr file.

[0174] For example, if the flag register is an IA32_DEBUGCTL register, assuming that the register identifier of IA32_DEBUGCTL obtained from the CPU hardware manual is 01D9H, and if the target CPU core is CPU core 1, then in the first system file 1 of CPU core 1, 64-bit integer 1 can be written with 01D9H as the offset of the written file, that is, the value of the IA32_DEBUGCTL register is set to 1 to enable the function call recording function of CPU core 1.

[0175] S404. When the target CPU core executes the first-layer function call instruction, store the source address of the first-layer function into the address register with register number K, and update the value in the index register to K.

[0176] Optionally, the multiple MSR registers may include an index register and multiple address registers.

[0177] The index register may be a MSR_LBR_TOS register, which may be used to store a target register position. The target register position may be a cursor position P. For example, if the target register position in the index register is 4, it means that the address register most recently used is address register 4.

[0178] The address register may be an MSR_LASTBRANCH_X_FROM_IP register, where X represents a register number. The numbers of the multiple address registers may start from 0. For example, the multiple address registers may be an MSR_LASTBRANCH_0_FROM_IP register, an MSR_LASTBRANCH_1_FROM_IP register, ..., an MSR_LASTBRANCH_X_FROM_IP register.

[0179] The address register with register serial number K may be the first address register used by the target CPU core in the current function call recording process, and K may be an integer greater than or equal to 0. For example, if the first address register used by the target CPU core in the current function call recording process is the MSR_LASTBRANCH_2_FROM_IP register, then K is 2.

[0180] When using multiple address registers, you can use them in order of sequence number starting from the first address register used by the target CPU in the current function call recording process. For example, if the first address register used by the target CPU core in the current function call recording process is the MSR_LASTBRANCH_2_FROM_IP register, if the target register position stored in the index register is 4, it means that the most recently used address register is the MSR_LASTBRANCH_4_FROM_IP register. Since the first address register is the MSR_LASTBRANCH_2_FROM_IP register, it means that the MSR_LASTBRANCH_2_FROM_IP register, the MSR_LASTBRANCH_3_FROM_IP register, and the MSR_LASTBRANCH_4_FROM_IP register have all been used.

[0181] The address register can be used to store the source address of the target thread calling a multi-layer function. For example, if the target thread is a 3-layer function call, the MSR_LASTBRANCH_1_FROM_IP register can be used to store the source address of the 1st layer function, the MSR_LASTBRANCH_2_FROM_IP register can be used to store the source address of the 2nd layer function, and the MSR_LASTBRANCH_3_FROM_IP register can be used to store the source address of the 3rd layer function.

[0182] For example, if the target thread is thread t, and thread t is a 3-level function call, if the first address register used in the function call recording process is the MSR_LASTBRANCH_2_FROM_IP register, that is, K is 2, then when the target CPU core executes the 1st-level function call instruction, it can store the source address of the 1st-level function to the address register with register number 2, that is, the MSR_LASTBRANCH_2_FROM_IP register, and update the value in the index register to 2.

[0183] S405. When the target CPU core executes the i+1th layer function call instruction, the source address of the i+1th layer function is stored in the address register with register number K+1, and the value in the index register is updated to the K+1.

[0184] Optionally, i may be 1, 2, ... in sequence until the function call recording function of the target CPU core is turned off.

[0185] For example, if the target thread is thread t, and thread t is a 3-layer function call, when the target CPU core executes the 1-layer function, the source address of the 1-layer function is stored in the MSR_LASTBRANCH_2_FROM_IP register, and K is 2. If i is 1, then i+1 is 2, and when the target CPU core executes the 2-layer function call instruction, the source address of the 2-layer function can be stored in the address register with register number 3, that is, the MSR_LASTBRANCH_3_FROM_IP register, and the value in the index register is updated to 3; if i is 2, then i+1 is 3, and when the target CPU core executes the 3-layer function call instruction, the source address of the 3-layer function can be stored in the address register with register number 4, that is, the MSR_LASTBRANCH_4_FROM_IP register, and the value in the index register is updated to 4.

[0186] S406: After the target thread ends, disable the function call recording function of the target CPU core.

[0187] Optionally, the value in the flag register of the target CPU core may be set to a second preset value to disable the function call recording function of the target CPU core.

[0188] Optionally, the second preset value may be 0, which is used to instruct the target CPU core to turn off the function call recording function.

[0189] For example, if the flag register is the IA32_DEBUGCTL register, assuming that the register identifier of IA32_DEBUGCTL obtained in the CPU hardware manual is 01D9H, if the target CPU core is CPU core 1, then after the target thread ends, you can write a 64-bit integer 0 in the first system file 1 of CPU core 1 with 01D9H as the offset for writing the file, that is, set the value of the IA32_DEBUGCTL register to 0 to turn off the function call recording function of CPU core 1.

[0190] S407: Determine an index register corresponding to the target CPU core, and determine at least one address register.

[0191] Optionally, the target CPU core may correspond to a plurality of MSR registers. The plurality of MSR registers may include an index register and at least one address register. For example, if the target CPU core corresponds to 64 MSR registers, the 64 MSR registers may include 1 index register and 32 address registers.

[0192] In an optional embodiment, at least one address register can be determined in the following manner: determine the target register position in the index MSR register; determine a first target register from multiple address registers corresponding to the target CPU core based on the target register position; determine M second target registers from multiple address registers used by the target CPU core; determine at least one address register including the first target register and M second target registers.

[0193] The first target register may be the address register used by the target CPU core to record the function call relationship for the last time. For example, if the first target register is the MSR_LASTBRANCH_4_FROM_IP register, it means that the address register used by the target CPU core to record the function call relationship for the last time during this function call is the MSR_LASTBRANCH_4_FROM_IP register.

[0194] The serial number of the second target register is located before the first target register. The value in the second target register can be a non-zero value.

[0195] For example, if the first target register is the MSR_LASTBRANCH_4_FROM_IP register, the second target register may be the MSR_LASTBRANCH_2_FROM_IP register and the MSR_LASTBRANCH_3_FROM_IP register whose sequence numbers are located before the first target register, and the values ​​in the two registers are non-zero values.

[0196] For example, if the target register position in the index MSR register is 4, the first target register can be determined as the MSR_LASTBRANCH_4_FROM_IP register in the multiple address registers corresponding to the target CPU core according to the target register position 4. Since the MSR_LASTBRANCH_0_FROM_IP register, the MSR_LASTBRANCH_1_FROM_IP register, the MSR_LASTBRANCH_2_FROM_IP register, and the MSR_LASTBRANCH_3_FROM_IP register exist before the MSR_LASTBRANCH_4_FROM_IP register, if the values ​​of the MSR_LASTBRANCH_2_FROM_IP register and the MSR_LASTBRANCH_3_FROM_IP register are non-zero values, two second target registers, namely the MSR_LASTBRANCH_2_FROM_IP register and the MSR_LASTBRANCH_3_FROM_IP register, can be determined in the multiple address registers used by the target CPU core. It can be determined that the at least one address register includes an MSR_LASTBRANCH_2_FROM_IP register, an MSR_LASTBRANCH_2_FROM_IP register, and an MSR_LASTBRANCH_3_FROM_IP register.

[0197] S408, obtaining a value of an index register and a value of at least one address register, and determining that the values ​​of the multiple MRS registers include the value of the index register and the value of at least one address register.

[0198] Since the index register and at least one address register are all MSR registers, for any MSR register, the value of the MSR register can be obtained in the following manner: obtain the first system file of the target CPU core; and obtain the value of the MSR register based on the first system file and the identifier of the MSR register.

[0199] Optionally, for any MSR register, the identifier of the MSR register may be obtained from a CPU hardware manual.

[0200] Optionally, the first system file of the target CPU core can be obtained. The identifier of the index register can be determined in the CPU hardware manual, and the way to read and write the index register in the user state can be determined in the first system file according to the identifier of the index register, and then the value of the index register can be obtained according to the way to read and write the index register in the user state; the identifier of the address register can be determined in the CPU hardware manual, and the way to read and write the address register in the user state can be determined in the first system file according to the identifier of the address register, and then the value of the address register can be obtained according to the way to read and write the address register in the user state.

[0201] For example, if the target CPU core is CPU core 1, the first system file / dev / cpu / 1 / msr of CPU core 1 can be obtained. If the identifier of the index register is determined to be 0x4FD in the CPU hardware manual, the way to read and write the index register in user state can be determined in the first system file / dev / cpu / 1 / msr according to 0x4FD, and then the value of the index register can be obtained according to the way to read and write the index register in user state; if the identifier of address register 1 is determined to be 0x29A in the CPU hardware manual, the way to read and write address register 1 in user state can be determined in the first system file / dev / cpu / 1 / msr according to 0x29A, and then the value of address register 1 can be obtained according to the way to read and write address register 1 in user state.

[0202] The values ​​of the multiple MRS registers may include a value of an index register and a value of at least one address register.

[0203] For example, the values ​​of the multiple MRS registers may include the value of the index register and the values ​​of three address registers.

[0204] S409: Determine calling information according to the values ​​of multiple MSR registers.

[0205] Optionally, the calling information includes the function identifiers of the multi-layer functions called by the target thread and the calling sequence between the multi-layer functions. For example, the calling information may include the function identifiers of 3-layer functions and the calling sequence of the 3-layer functions.

[0206] In an optional embodiment, the calling information can be determined according to the values ​​of multiple MSR registers in the following manner: the source address of the multi-layer function is determined according to the value of the first target register and the values ​​of M second target registers; the function identifier of the multi-layer function is determined according to the source address of the multi-layer function; and the calling order of the multi-layer function is determined according to the arrangement order of the first target register and the M second target registers.

[0207] Since the first target register and the M second target registers are both address registers, and the address registers are used to store the source address of the target thread calling a multi-layer function, the value of the first target register and the values ​​of the M second target registers are both the source addresses of the function. The source address of the M+1 layer function can be determined based on the value of the first target register and the values ​​of the M second target registers.

[0208] Optionally, the source address of the M+1 layer function is processed by a preset instruction to determine the function identifier of the M+1 layer function, and the calling order of the M+1 layer function is determined according to the arrangement order of the first target register and the M second target registers.

[0209] For example, if the target thread is thread t, thread t is a 3-layer function call, the first target register is the MSR_LASTBRANCH_4_FROM_IP register, and the two second target registers are the MSR_LASTBRANCH_2_FROM_IP register and the MSR_LASTBRANCH_3_FROM_IP register, then the source address 3 of the 3rd layer function can be determined according to the value of the MSR_LASTBRANCH_4_FROM_IP register; the source address 2 of the 2nd layer function can be determined according to the value of the MSR_LASTBRANCH_3_FROM_IP register; and the source address 1 of the 1st layer function can be determined according to the value of the MSR_LASTBRANCH_2_FROM_IP register. Then, the source address 1 can be processed by the preset instruction to determine that the function identifier of the 1st layer function is main; the source address 2 can be processed by the preset instruction to determine that the function identifier of the 2nd layer function is A; and the source address 3 can be processed by the preset instruction to determine that the function identifier of the 3rd layer function is B. If the arrangement order of the three registers is: MSR_LASTBRANCH_2_FROM_IP register, MSR_LASTBRANCH_3_FROM_IP register, MSR_LASTBRANCH_4_FROM_IP register, it can be determined that the calling order between the three-layer functions is that the first-layer function calls the second-layer function, and the second-layer function calls the third-layer function. Since the first-layer function is identified as main, the second-layer function is identified as A, and the third-layer function is identified as B, the calling information can be determined as: function main calls function A, and function A calls function B.

[0210] It should be noted that in Figure 4 The various processing steps (S401 to S409) shown in the embodiment do not constitute a specific limitation on the process of determining thread call information. In other embodiments of the present application, the process of determining thread call information may include: Figure 4 The embodiment may have more or fewer steps. For example, the process of determining thread call information may include: Figure 4 Some steps in the embodiment, or, Figure 4 Some steps in the embodiments may be replaced by steps having the same functions, or Figure 4 Some steps in the embodiments may be split into multiple steps, etc.

[0211] In an embodiment of the present application, the electronic device can determine the thread state of the target thread and determine the target CPU core corresponding to the target thread. After the target thread is started, the function call recording function of the target CPU core can be turned on. When the target CPU core executes the first layer function call instruction, the source address of the first layer function is stored in the address register with the register number K, and the value in the index register is updated to K, K is an integer greater than or equal to 0, and the address register with the register number K is the first address register used by the target CPU core in this function call recording process; when the target CPU core executes the i+1 layer function call instruction, the source address of the i+1 layer function is stored in the address register with the register number K+1, and the value in the index register is updated to K+1. After the target thread ends, the function call recording function of the target CPU core is turned off. The electronic device can determine the index register corresponding to the target CPU core, and determine at least one address register, and obtain the value of the index register and the value of at least one address register, and determine the values ​​of multiple MRS registers including the value of the index register and the value of at least one address register. The electronic device can determine the call information according to the values ​​of multiple MSR registers. Since the calling information of the target thread can be determined in the event of any exception in the target thread without being restricted by preset codes, and since the calling information of the target thread can be determined by utilizing hardware characteristics without interrupting the execution of the target thread, the flexibility of determining the thread calling information is comprehensively improved.

[0212] Figure 5 A process diagram of a method for determining thread call information provided by an exemplary embodiment of the present application. Figure 5 , including steps ①②③④⑤.

[0213] The electronic device may determine the thread state of the target thread. For example, if the target thread is thread 1 and the thread is executed in a user state, it may be determined that the thread state is a user state.

[0214] For any thread, the thread may have a corresponding thread state description file. Since the thread state description file may include the running information of the thread, in step ①, the target CPU core for executing the thread may be determined according to the thread state description file. For example, if thread 1 has a corresponding thread state description file 1, and if thread state description file 1 includes CPU core 1, the target CPU core corresponding to thread 1 may be determined to be CPU core 1 according to thread state description file 1.

[0215] Optionally, the target CPU core is provided with a plurality of MSR registers, including an index register, 32 address registers, and a flag MSR register, wherein the value in the flag register is 0, indicating that the function call recording function of the CPU core 1 is not enabled.

[0216] In step ②, the value in the flag register may be set to a first preset value 1 to enable the function call recording function of CPU core 1.

[0217] In step ③, when the target CPU core executes the i+1th layer function call instruction, the source address of the i+1th layer function is stored in the address register with register number K+1, and the value in the index register is updated to K+1. i can be 1, 2, ... in sequence until the function call recording function of the target CPU core is turned off.

[0218] For example, if the target thread is thread 1, and thread 1 is a 3-level function call, if K is 2, it means that the first address register used in this function call recording process is address register 2. When the target CPU core executes the 1st-level function call instruction, it can store the source address of the 1st-level function to address register 2, and update the value in the index register to 2, that is, K is 2; when i is equal to 1, then i+1 is 2, when the target CPU core executes the 2nd-level function call instruction, it can store the source address of the 2nd-level function to address register 3, and update the value in the index register to 3; when i is equal to 2, then i+1 is 3, when the target CPU core executes the 3rd-level function call instruction, it can store the source address of the 3rd-level function to address register 4, and update the value in the index register to 4.

[0219] In step ④, after the target thread finishes running, the value in the flag register of the target CPU core can be set to a second preset value of 0 to disable the function call recording function of the target CPU core.

[0220] In step ⑤, the values ​​of multiple MSR registers are obtained, and the calling information is determined according to the values ​​of the multiple MSR registers.

[0221] Optionally, the target register position may be obtained in the index register, the first target register may be determined according to the target register position, and M second target registers may be determined, and then the value of the first target register and the values ​​of the M second target registers may be determined. The values ​​of the multiple MSR registers may include the value of the first target register and the values ​​of the M second target registers.

[0222] For example, if CPU core 1 includes 32 address registers, if the target register position obtained in the index register is 4, the first target register is determined to be address register 4 according to the target register position, and then the four address registers before address register 4 can be determined, and the two address registers storing non-zero values ​​in the four address registers can be determined as the second target registers, namely address register 2 and address register 3. Further, the values ​​in address register 4, address register 3, and address register 2 can be determined. For example, the values ​​in address register 4, address register 3, and address register 2 can be source address 3, source address 2, and source address 1, respectively.

[0223] Optionally, source address 1 can be processed by a preset instruction to determine that the function identifier of the first-layer function is main; source address 2 can be processed by a preset instruction to determine that the function identifier of the second-layer function is A; source address 3 can be processed by a preset instruction to determine that the function identifier of the third-layer function is B. If the arrangement order of the three registers is: address register 2, address register 3, address register 4, then it can be determined that the calling order between the three-layer functions is that the first-layer function calls the second-layer function, and the second-layer function calls the third-layer function. Since the identifier of the first-layer function is main, the identifier of the second-layer function is A, and the identifier of the third-layer function is B, the calling information can be determined as: function main calls function A, and function A calls function B.

[0224] In an embodiment of the present application, the electronic device can determine the thread state of the target thread and determine the target CPU core corresponding to the target thread. After the target thread is started, the function call recording function of the target CPU core can be turned on. When the target CPU core executes the first layer function call instruction, the source address of the first layer function can be stored in the address register with the register number K, and the value in the index register is updated to K; when the target CPU core executes the i+1 layer function call instruction, the source address of the i+1 layer function can be stored in the address register with the register number K+1, and the value in the index register is updated to K+1. After the target thread ends, the function call recording function of the target CPU core can be turned off. The electronic device can determine the index register corresponding to the target CPU core, and determine at least one address register, and obtain the value of the index register, and the value of at least one address register, and determine the values ​​of multiple MRS registers including the value of the index register and the value of at least one address register. The electronic device can determine the call information based on the values ​​of multiple MSR registers. Since the calling information of the target thread can be determined in the event of any exception in the target thread without being restricted by preset codes, and since the calling information of the target thread can be determined by utilizing hardware characteristics without interrupting the execution of the target thread, the flexibility of determining the thread calling information is comprehensively improved.

[0225] Figure 6 A flowchart of another method for determining thread call information provided by an exemplary embodiment of the present application. Figure 6 , the method comprising:

[0226] S601: Determine the thread state of the target thread.

[0227] S602: Determine the target processor CPU core corresponding to the target thread.

[0228] It should be noted that the execution process of steps S601 to S602 can refer to the execution process of steps S201 to S202, which will not be described in detail here.

[0229] S603: Determine the kernel stack corresponding to the target thread.

[0230] For any thread, when the thread is executed in kernel state, the thread can have a corresponding kernel stack.

[0231] For example, if the target thread is thread 1, kernel stack 1 corresponding to thread 1 may be determined.

[0232] S604: Obtain a symbol table description file of the operating system kernel.

[0233] The symbol table description file may be a file such as / boot / System.map-* or / proc / kallsyms. The symbol table description file may include fixed kernel symbols. For example, if the symbol table description file is a / proc / kallsyms file, then the / proc / kallsyms file may include multiple fixed kernel symbols, such as kernel symbol 1, kernel symbol 2, ..., etc.

[0234] The electronic device may be provided with a symbol table description file. Since different operating system kernels correspond to different symbol table description files, the symbol table description file of the operating system kernel may be obtained.

[0235] S605: Determine the address calculation formula corresponding to the operating system kernel.

[0236] The address calculation formula can be used to calculate the kernel stack address of the target thread.

[0237] Optionally, an address calculation formula corresponding to the operating system kernel may be constructed according to the specific data organization mode of the operating system kernel in combination with a symbol table description file.

[0238] For example, if the operating system installed in the electronic device is the 2012 version of System W, the specific data organization method of the 2012 version of System W can be obtained, and the address calculation formula corresponding to the 2012 version of System W can be constructed in combination with the symbol table description file.

[0239] S606: According to the symbol table description file and the address calculation formula, the values ​​of multiple general registers of the target thread in the user state are obtained in the kernel stack.

[0240] When the target thread is executed in the user state, the function instructions, function parameters and other values ​​of the latest function called by the target thread in the user state can be saved in multiple general registers. When the thread state of the target thread is switched from the user state to the kernel state, in order to prevent the values ​​of the multiple general registers in the user state from polluting the kernel state, the values ​​of the multiple general registers can be copied again and saved in the kernel stack corresponding to the target thread, and then the values ​​in the multiple general registers are cleared, so that the multiple general registers can be used by the target thread in the kernel state. Therefore, when the target thread is switched from the user state to the kernel state, the kernel stack corresponding to the target thread saves the values ​​of the multiple general registers of the target thread in the user state, and the values ​​of the multiple general registers of the target thread in the user state can be obtained in the kernel stack.

[0241] The latest function refers to the function currently being called by the target thread. For example, if the third-level function is currently being called, the third-level function is the latest function called by the target thread.

[0242] The function information may include at least one of a function pointer and a function parameter. For example, the function information may include an instruction pointer (RIP), a function parameter 1, and the like.

[0243] The rip pointer can be used to indicate the address of the code in the function of the topmost stack frame in the user state before entering the kernel state, that is, the function address of the latest function.

[0244] In an optional embodiment, the values ​​of multiple general registers of the target thread in user state can be obtained in the kernel stack according to the symbol table description file and the address calculation formula in the following manner: the target memory address is calculated according to the symbol table description file and the address calculation formula; according to the target memory address, the target memory is determined in the kernel stack, and the values ​​of multiple general registers of the target thread in user state are obtained in the target memory.

[0245] Optionally, a plurality of target kernel symbols may be determined in the symbol table description file, and the plurality of target kernel symbols may be calculated using an address calculation formula to obtain a target memory address.

[0246] For example, if the symbol table description file is the / proc / kallsyms file, the target kernel symbols are kernel symbol 1 and kernel symbol 2, and if the address calculation formula is calculation formula 1, kernel symbol 1 and kernel symbol 2 can be calculated using calculation formula 1 to obtain the target memory address. Assume that the obtained target memory address is 0X80000038.

[0247] Optionally, the target memory may be determined in the kernel stack according to the target memory address, and values ​​of multiple general registers of the target thread in the user state may be obtained in the target memory.

[0248] For example, if the target thread is thread 1 and the target memory address is 0X80000038, the target memory can be determined in the kernel stack according to 0X80000038, and the values ​​of multiple general registers of thread 1 in user state can be obtained in the target memory. Assume that the values ​​of multiple general registers of thread 1 in user state include rip pointer 1 and function parameter 1. If the latest function is a layer 3 function, rip pointer 1 can be used to indicate the function address of the layer 3 function.

[0249] S607: Determine the user stack corresponding to the target thread.

[0250] For any thread, the thread can have a corresponding user stack. The user stack can be used to store data such as the function address and function variables of the functions called by the thread.

[0251] For example, if the target thread is thread 1, user stack 1 corresponding to thread 1 may be determined.

[0252] S608: Determine the function address of the latest function according to the values ​​of multiple general registers of the target thread in the user state.

[0253] Optionally, the values ​​of multiple general registers of the target thread in the user state may be parsed using the code in the Libunwind code library to determine the function address of the latest function.

[0254] For example, if the latest function is a layer 3 function, and the function information of the latest function includes rip pointer 1 and function parameter 2, the function address 3 of the layer 3 function can be determined through the Libunwind code library according to the rip pointer 1 in the function information. Assume that the function address 3 of the layer 3 function can be 0X1008.

[0255] S609: Determine the starting position in the user stack according to the function address of the latest function.

[0256] Since the user stack includes multiple memory segments, the position corresponding to the function address of the latest function in the user stack can be determined as the starting position.

[0257] For example, if the latest function is a layer 3 function, function address 3 is 0X1008, and if the target thread is thread 1, corresponding to user stack 1, the position corresponding to function address 0X1008 can be determined as the starting position in user stack 1 according to function address 0X1008.

[0258] S610 . From the start position, in the order of stack addresses from low to high, obtain the return addresses of the multi-layer functions in the user stack.

[0259] Optionally, the callback function may be executed through the Libunwind code to obtain the function address of the multi-layer function in the user stack.

[0260] Optionally, starting from the starting position, in the order of stack addresses from low to high, with the assistance of other register values ​​and in combination with the debugging symbol information of the program, the return addresses of multiple layers of functions are obtained layer by layer in the user stack.

[0261] For example, if the user stack is Figure 3 As shown in , the callback function can be executed through the Libunwind code, starting from the starting position corresponding to the function address 3 in the user stack, with the help of other register values, combined with the debugging symbol information of the program, the return address 2 is obtained as "the address of the return function 2" in the stack frame corresponding to the third-level function, that is, function 3, and the return address 1 is obtained as "the address of the return function 1" in the stack frame corresponding to the second-level function, that is, function 2.

[0262] It should be noted that in the process of executing the callback function to obtain the function address according to the Libunwind code, the data in the user stack corresponding to the target thread may change with the execution of the target thread. Therefore, memory validity protection is required when executing the callback function to avoid segmentation errors caused by the application accessing illegal memory.

[0263] S611. Determine calling information according to the function address of the latest function and the return address of the multi-layer function.

[0264] The calling information may include function identifiers of multi-layer functions and the calling sequence between multi-layer functions.

[0265] Optionally, multiple function addresses are processed by preset instructions to determine function identifiers of multi-layer functions.

[0266] For example, if the function address 3 of function 3 is 0X1008, "0X1008" can be processed through the preset instructions to obtain the function identifier of function 3 as B; similarly, the return address 2 can be processed through the preset instructions to obtain the function identifier of function 2 as A; the return address 1 can be processed through the preset instructions to obtain the function identifier of function 1 as main.

[0267] Since the stack addresses in the user stack are generated from high to low, after obtaining the function address of the latest function and multiple return addresses, the multiple function addresses can be sorted from high to low to obtain the calling order between multi-layer functions.

[0268] For example, if there are three layers of function addresses, namely function address 3, return address 2, and return address 1, function address 3 is the function address of the latest function 3, return address 2 is "the address of return function 2", and return address 1 is "the address of return function 1", then the three function addresses can be sorted in descending order. Assuming that the sorting result is return address 1, return address 2, and function address 3, it can be determined that the calling order between the three layers of functions is that the first layer function calls the second layer function, and the second layer function calls the third layer function, that is, function 1 calls function 2, and function 2 calls function 3.

[0269] Optionally, the calling information may include the function identifiers of the multi-layer functions and the calling order between the multi-layer functions. For example, if the target thread is thread 1, thread 1 is a 3-layer function call, the function identifier of the 1st layer function is main, the function identifier of the 2nd layer function is A, and the function identifier of the 3rd layer function is B, and the calling order between the 3-layer functions is: the 1st layer function calls the 2nd layer function, and the 2nd layer function calls the 3rd layer function, then the calling information can be determined as: function main calls function A, and function A calls function B.

[0270] It should be noted that in Figure 6 The various processing steps (S601-S611) shown in the embodiment do not constitute a specific limitation on the process of determining thread call information. In other embodiments of the present application, the process of determining thread call information may include: Figure 6 The embodiment may have more or fewer steps. For example, the process of determining thread call information may include: Figure 6 Some steps in the embodiment, or, Figure 6 Some steps in the embodiments may be replaced by steps having the same functions, or Figure 6 Some steps in the embodiments may be split into multiple steps, etc.

[0271] In an embodiment of the present application, the electronic device can determine the thread state of the target thread and determine the target processor CPU core corresponding to the target thread. The electronic device can determine the kernel stack corresponding to the target thread. The electronic device can obtain the symbol table description file of the operating system kernel and determine the address calculation formula corresponding to the operating system kernel, and then obtain the values ​​of multiple general registers of the target thread in the user state in the kernel stack according to the symbol table description file and the address calculation formula. The electronic device can determine the user stack corresponding to the target thread, and determine the function address of the latest function according to the values ​​of multiple general registers of the target thread in the user state, and then determine the starting position in the user stack according to the function address of the latest function, and can obtain the return address of the multi-layer function in the user stack from the starting position in the order of the stack address from low to high, and determine the call information according to the return address of the multi-layer function. Since the call information of the target thread can be determined in any abnormal situation of the target thread, it is not limited to the preset code; and since the call information of the target thread can be determined by the kernel design, there is no need to interrupt the execution of the target thread, so the flexibility of determining the thread call information is comprehensively improved.

[0272] Figure 7 A process diagram of another method for determining thread call information provided by an exemplary embodiment of the present application. Figure 7 , including steps ①②③④⑤.

[0273] When the target thread is in the user state, the target thread can enter the kernel state through the system call interface to switch from the user state to the kernel state. The electronic device can determine the thread state of the target thread. For example, if the target thread is thread 1 and the thread is executed in the kernel state, it can be determined that the thread state is the kernel state.

[0274] For any thread, the thread may have a corresponding thread state description file. Since the thread state description file may include the running information of the thread, the target CPU core for executing the thread may be determined based on the thread state description file. For example, if thread 1 has a corresponding thread state description file 1, and if thread state description file 1 includes CPU core 1, the target CPU core corresponding to thread 1 may be determined to be CPU core 1 based on thread state description file 1.

[0275] In step ①, the kernel stack corresponding to the target thread can be determined. For example, if the target thread is thread 1, the kernel stack corresponding to thread 1 can be used.

[0276] When the target thread is executed in user state, the function information and other values ​​of the latest function called by the target thread can be saved in multiple general registers. When the target thread enters kernel state, the values ​​of multiple general registers in user state can be copied and saved in the target memory of the kernel stack. Therefore, the target memory of the kernel stack stores the values ​​of multiple general registers of the target thread in user state. Therefore, in step ②, the target memory address can be obtained, and the values ​​of multiple general registers of the target thread in user state can be obtained in the kernel stack according to the target memory address.

[0277] Optionally, the target memory address may be calculated based on the symbol table description file and the address calculation formula.

[0278] For example, if the symbol table description file is the / proc / kallsyms file, the target kernel symbols are kernel symbol 1 and kernel symbol 2, and if the address calculation formula is calculation formula 1, kernel symbol 1 and kernel symbol 2 can be calculated using calculation formula 1 to obtain the target memory address. Assume that the obtained target memory address is 0X80000038.

[0279] Optionally, the target memory can be determined in the kernel stack according to the target memory address, and the values ​​of multiple general registers of the target thread in the user state can be obtained in the target memory. For example, if the target thread is thread 1, assuming that the target memory address is 0X80000038, the corresponding target memory can be determined according to 0X80000038, and the values ​​of multiple general registers of thread 1 in the user state can be obtained in the target memory, assuming that the values ​​of multiple general registers of thread 1 in the user state include rip pointer 1 and function parameter 2.

[0280] Optionally, the values ​​of multiple general registers of the target thread in the user state may be parsed using the code in the Libunwind code library to determine the function address of the latest function.

[0281] For example, if the latest function is a layer 3 function, and the function information of the latest function includes rip pointer 1 and function parameter 2, the function address 3 of the layer 3 function can be determined through the Libunwind code library according to the rip pointer 1 in the function information. Assume that the function address 3 of the layer 3 function can be 0X1008.

[0282] In step ③, the user stack corresponding to the target thread may be determined. For example, if the target thread is thread 1, the user stack 1 corresponding to thread 1 may be determined.

[0283] In step ④, the starting position can be determined in the user stack according to the function address of the latest function. For example, if function address 3 is 0X1008, the address corresponding to function address 0X1008 can be determined as the starting position in user stack 1 according to function address 0X1008.

[0284] In step ⑤, the return address of the multi-layer function can be obtained in the user stack from the starting position in the order of the stack address from low to high. Optionally, the callback function can be executed through the Libunwind code to obtain the function address of the multi-layer function in the user stack from the starting position. For example, the callback function can be executed through the Libunwind code, and the return address 2 is obtained as the "return address of function 2" in the stack frame corresponding to the third-layer function, i.e., function 3 in the user stack, and the return address 1 is obtained as the "return address of function 1" in the stack frame corresponding to the second-layer function, i.e., function 2.

[0285] After obtaining the return address, multiple return addresses are processed by preset instructions to determine the function identifier of the multi-layer function, and multiple function addresses can be sorted in order from high to low stack addresses to obtain the calling order between the multi-layer functions, thereby determining the calling information. Among them, the multiple function addresses can include the function address of the latest function and the return address of the multi-layer function.

[0286] For example, if the target thread is thread 1, and thread 1 is a three-layer function call, if there are three function addresses, namely function address 3, return address 2, and return address 1, then function address 3 can be processed through a preset instruction to obtain a function identifier of function 3 as B; return address 2 can be processed through a preset instruction to obtain a function identifier of function 2 as A; return address 1 can be processed through a preset instruction to obtain a function identifier of function 1 as main. If the sorting result of the three function addresses is return address 1, return address 2, and function address 3, then it can be determined that the calling order between the three layers of functions is function 1 calling function 2, function 2 calling function 3, and the calling information can be determined as: function main calls function A, and function A calls function B.

[0287] In an embodiment of the present application, the electronic device can determine the thread state of the target thread and determine the target processor CPU core corresponding to the target thread. The electronic device can determine the kernel stack corresponding to the target thread. The electronic device can obtain the symbol table description file of the operating system kernel and determine the address calculation formula corresponding to the operating system kernel, and then obtain the values ​​of multiple general registers of the target thread in the user state in the kernel stack according to the symbol table description file and the address calculation formula. The electronic device can determine the user stack corresponding to the target thread, and determine the function address of the latest function according to the values ​​of multiple general registers of the target thread in the user state, and then determine the starting position in the user stack according to the function address of the latest function, and can obtain the return address of the multi-layer function in the user stack from the starting position in the order of the stack address from low to high, and determine the call information according to the return address of the multi-layer function. Since the call information of the target thread can be determined in any abnormal situation of the target thread, it is not limited to the preset code; and since the call information of the target thread can be determined by the kernel design, there is no need to interrupt the execution of the target thread, so the flexibility of determining the thread call information is comprehensively improved.

[0288] Figure 8 A schematic diagram of a structure of a device for determining thread call information provided by an exemplary embodiment of the present application. Figure 8 The thread call information determination device 10 includes: a first determination module 11, a second determination module 12 and a third determination module 13, wherein:

[0289] The first determination module 11 is used to determine the thread state of the target thread, and the thread state includes kernel state and user state;

[0290] The second determination module 12 is used to determine a target processor CPU core corresponding to a target thread, and the target CPU core is used to execute the target thread;

[0291] The third determination module 13 is used to determine the calling information of the target thread according to the thread state and the target CPU core, wherein the calling information includes the function identifiers of the multi-layer functions called by the target thread and the calling order between the multi-layer functions.

[0292] The thread call information determination device provided in the embodiment of the present application can execute the technical solution shown in the above method embodiment, and its implementation principle and beneficial effects are similar, which will not be repeated here.

[0293] In a possible implementation manner, the third determining module 13 is specifically configured to:

[0294] If the thread state is the user state, obtaining values ​​of multiple MSR registers of specific models corresponding to the target CPU core, and determining the call information according to the values ​​of the multiple MSR registers;

[0295] If the thread state is the kernel state, the values ​​of multiple general registers of the target thread in the user state are obtained, and the call information is determined according to the values ​​of the multiple general registers of the target thread in the user state.

[0296] In a possible implementation manner, the third determining module 13 is specifically configured to:

[0297] Determine an index register corresponding to the target CPU core, and determine at least one address register, wherein the index register and the address register are MSR registers respectively;

[0298] Obtaining a value of the index register and a value of the at least one address register;

[0299] Determining the values ​​of the plurality of MSR registers includes the value of the index register and the value of the at least one address register.

[0300] In a possible implementation manner, the third determining module 13 is specifically configured to:

[0301] determining a target register location in the index register;

[0302] According to the target register position, determining a first target register from a plurality of address registers corresponding to the target CPU core, wherein the first target register is an address register used by the target CPU core to record a function call relationship for the last time;

[0303] Determine M second target registers from a plurality of address registers used by the target CPU core, wherein the values ​​in the second target registers are non-zero values;

[0304] It is determined that the at least one address register includes the first target register and the M second target registers.

[0305] In a possible implementation manner, the third determining module 13 is specifically configured to:

[0306] Determine a source address of the multi-layer function according to the value of the first target register and the values ​​of the M second target registers;

[0307] Determine a function identifier of the multi-layer function according to the source address of the multi-layer function;

[0308] Determining a calling order of the multi-layer function according to an arrangement order of the first target register and the M second target registers;

[0309] The calling information includes the function identifier of the multi-layer function and the calling order of the multi-layer function.

[0310] In a possible embodiment, the device further includes a setting module 14 and a storage module 15, wherein:

[0311] The setting module 14 is used to enable the function call recording function of the target CPU core after the target thread is started;

[0312] The storage module 15 is used to store the source address of the first-layer function in the address register with a register number of K when the target CPU core executes the first-layer function call instruction, and update the value in the index register to K, where K is an integer greater than or equal to 0, and the address register with a register number of K is the first address register used by the target CPU core in the current function call recording process;

[0313] The storage module 15 is used to store the source address of the i+1th layer function in the address register with register number K+1 when the target CPU core executes the i+1th layer function call instruction, and update the value in the index register to K+1;

[0314] Here, the value of i is 1, 2, ... in sequence until the function call recording function of the target CPU core is turned off.

[0315] In a possible embodiment, the setting module 14 is specifically used for:

[0316] Setting the value in the flag register corresponding to the target CPU core to a first preset value to enable the function call recording function of the target CPU core, the flag register being an MSR register;

[0317] To disable the function call recording function of the target CPU core, the setting module 14 is specifically used to:

[0318] The value in the flag MSR register is set to a second preset value to disable the function call recording function of the target CPU core.

[0319] In a possible implementation manner, for any one of the index register and the at least one address register, the third determining module 13 is specifically configured to:

[0320] Obtain a first system file of the target CPU core, wherein the first system file includes a method for reading and writing the multiple MSR registers in user mode;

[0321] According to the first system file and the identifier of the MSR register, the value of the MSR register is obtained.

[0322] In a possible implementation manner, the third determining module 13 is specifically configured to:

[0323] Determine the kernel stack corresponding to the target thread;

[0324] The values ​​of a plurality of general registers of the target thread in the user state are obtained in the kernel stack.

[0325] In a possible implementation manner, the third determining module 13 is specifically configured to:

[0326] Get the symbol table description file of the operating system kernel;

[0327] Determine an address calculation formula corresponding to the operating system kernel, where the address calculation formula is used to calculate the kernel stack address of the target thread;

[0328] According to the symbol table description file and the address calculation formula, the values ​​of multiple general registers of the target thread in the user state are obtained in the kernel stack.

[0329] In a possible implementation manner, the third determining module 13 is specifically configured to:

[0330] Calculate the target memory address according to the symbol table description file and the address calculation formula;

[0331] According to the target memory address, a target memory is determined in the kernel stack, and values ​​of a plurality of general registers of the target thread in user mode are stored in the target memory.

[0332] In a possible implementation manner, the third determining module 13 is specifically configured to:

[0333] Determine a user stack corresponding to the target thread;

[0334] Determining a function address of a latest function according to values ​​of a plurality of general registers of the target thread in user mode;

[0335] Determining a starting position in the user stack according to a function address of the latest function;

[0336] From the starting position, in the order of stack addresses from low to high, obtaining the return address of the multi-layer function in the user stack;

[0337] The calling information is determined according to the function address of the latest function and the return address of the multi-layer function.

[0338] The thread call information determination device provided in the embodiment of the present application can execute the technical solution shown in the above method embodiment, and its implementation principle and beneficial effects are similar, which will not be repeated here.

[0339] The exemplary embodiment of the present application provides a structural diagram of an electronic device, see Fig. 9 The electronic device 20 may include a processor 21 and a memory 22. Exemplarily, the processor 21 and the memory 22 are interconnected via a bus 23.

[0340] The memory 22 stores computer-executable instructions;

[0341] The processor 21 executes the computer-executable instructions stored in the memory 22, so that the processor 21 executes the method shown in the above method embodiment.

[0342] Accordingly, an embodiment of the present application provides a computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, they are used to implement the method described in any of the above method embodiments.

[0343] Accordingly, an embodiment of the present application may also provide a computer program product, including a computer program, which, when executed by a processor, can implement the method shown in any of the above method embodiments.

[0344] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0345] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0346] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0347] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0348] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0349] The memory may include non-permanent storage in a computer-readable medium, random access memory (RAM) and / or non-volatile memory in the form of read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0350] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0351] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0352] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims

1. A method for determining thread call information, characterized in that: include: Determine the thread state of the target thread, wherein the thread state includes a kernel state and a user state; Determine a target processor CPU core corresponding to a target thread, wherein the target CPU core is used to execute the target thread; The calling information of the target thread is determined according to the thread state and the target CPU core, wherein the calling information includes function identifiers of the multi-layer functions called by the target thread and a calling sequence between the multi-layer functions.

2. The method according to claim 1, characterized in that: Determining the call information of the target thread according to the thread state and the target CPU core includes: If the thread state is the user state, obtaining values ​​of multiple MSR registers of specific models corresponding to the target CPU core, and determining the call information according to the values ​​of the multiple MSR registers; If the thread state is the kernel state, the values ​​of multiple general registers of the target thread in the user state are obtained, and the call information is determined according to the values ​​of the multiple general registers of the target thread in the user state.

3. The method according to claim 2, characterized in that Obtain the values ​​of multiple MSR registers corresponding to the target CPU core, including: Determine an index register corresponding to the target CPU core, and determine at least one address register, wherein the index register and the address register are MSR registers respectively; Obtaining a value of the index register and a value of the at least one address register; Determining the values ​​of the plurality of MSR registers includes the value of the index register and the value of the at least one address register.

4. The method according to claim 3, characterized in that Determining at least one address register, comprising: determining a target register location in the index register; According to the target register position, determining a first target register from a plurality of address registers corresponding to the target CPU core, wherein the first target register is an address register used by the target CPU core to record a function call relationship for the last time; Determine M second target registers from a plurality of address registers used by the target CPU core, wherein the values ​​in the second target registers are non-zero values; It is determined that the at least one address register includes the first target register and the M second target registers.

5. The method according to any one of claims 2 to 4, characterized in that: Determining the call information according to the values ​​of the multiple MSR registers includes: Determine a source address of the multi-layer function according to the value of the first target register and the values ​​of the M second target registers; Determine a function identifier of the multi-layer function according to the source address of the multi-layer function; Determining a calling order of the multi-layer function according to an arrangement order of the first target register and the M second target registers; The calling information includes the function identifier of the multi-layer function and the calling order of the multi-layer function.

6. The method according to any one of claims 3 to 5, characterized in that: Before obtaining the values ​​of multiple specific model MSR registers corresponding to the target CPU core, the method further includes: After the target thread is started, a function call recording function of the target CPU core is enabled; When the target CPU core executes the first-layer function call instruction, the source address of the first-layer function is stored in the address register with a register number of K, and the value in the index register is updated to K, where K is an integer greater than or equal to 0, and the address register with a register number of K is the first address register used by the target CPU core in the current function call recording process; When the target CPU core executes the i+1th layer function call instruction, the source address of the i+1th layer function is stored in the address register with register number K+1, and the value in the index register is updated to K+1; Here, the value of i is 1, 2, ... in sequence until the function call recording function of the target CPU core is turned off.

7. The method according to claim 6, characterized in that Enable the function call recording function of the target CPU core, including: Setting the value in the flag register corresponding to the target CPU core to a first preset value to enable the function call recording function of the target CPU core, the flag register being an MSR register; Disabling the function call recording function of the target CPU core includes: The value in the flag MSR register is set to a second preset value to disable the function call recording function of the target CPU core.

8. The method according to any one of claims 2 to 7, characterized in that: For any one MRS register of the index register and the at least one address register; obtaining the value of the MSR register includes: Obtain a first system file of the target CPU core, wherein the first system file includes a method for reading and writing the multiple MSR registers in user mode; According to the first system file and the identifier of the MSR register, the value of the MSR register is obtained.

9. The method according to claim 2, characterized in that: Obtaining values ​​of multiple general registers of the target thread in user mode, including: Determine the kernel stack corresponding to the target thread; The values ​​of a plurality of general registers of the target thread in the user state are obtained in the kernel stack.

10. The method according to claim 9, characterized in that Obtaining values ​​of a plurality of general registers of the target thread in the user state in the kernel stack includes: Get the symbol table description file of the operating system kernel; Determine an address calculation formula corresponding to the operating system kernel, where the address calculation formula is used to calculate the kernel stack address of the target thread; According to the symbol table description file and the address calculation formula, the values ​​of multiple general registers of the target thread in the user state are obtained in the kernel stack.

11. The method according to claim 10, characterized in that According to the symbol table description file and the address calculation formula, obtaining values ​​of multiple general registers of the target thread in the user state in the kernel stack includes: Calculate the target memory address according to the symbol table description file and the address calculation formula; According to the target memory address, a target memory is determined in the kernel stack, and values ​​of a plurality of general registers of the target thread in user mode are stored in the target memory.

12. The method according to any one of claims 2, 9 to 11, characterized in that: Determining the call information according to the values ​​of a plurality of general registers of the target thread in the user state includes: Determine a user stack corresponding to the target thread; Determining a function address of a latest function according to values ​​of a plurality of general registers of the target thread in user mode; Determining a starting position in the user stack according to a function address of the latest function; From the starting position, in the order of stack addresses from low to high, obtaining the return address of the multi-layer function in the user stack; The calling information is determined according to the function address of the latest function and the return address of the multi-layer function.

13. An electronic device, characterized in that: include: at least one processor; as well as a memory communicatively coupled to the at least one processor; The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the electronic device to perform the method described in any one of claims 1 to 12.

14. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer-executable instructions, and when the processor executes the computer-executable instructions, the method according to any one of claims 1 to 12 is implemented.

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