Digital-analog hybrid circuit segmentation method based on excitation control

Abstract

The invention discloses a digital-analog hybrid circuit segmentation method based on excitation control, and the method comprises the steps: carrying out the modeling of a digital-analog hybrid circuit, obtaining a directed dependency graph, dividing all power supplies in the digital-analog hybrid circuit into digital power supplies and analog power supplies, and obtaining different power supply value modes; performing digital channel identification sensitization under each power supply value mode to obtain a controlled blocked MOS set, disconnecting one-way edges represented by all MOS grid edges in the controlled blocked MOS set in a directed dependency graph for each power supply value mode to obtain a corresponding directed dependency graph, identifying a great strong connection block as a circuit block, and performing digital channel identification sensitization on the circuit block; therefore, a circuit segmentation result under each power supply value mode is obtained. According to the method, a controlled blocked MOS set is obtained based on a directed dependency graph and signal flow analysis, and the digital-analog hybrid circuit is segmented according to the controlled blocked MOS set, so that circuit defect simulation is facilitated.

Description

Technical Field

[0001] The present invention belongs to the technical field of digital-analog hybrid circuits, and more specifically, relates to a digital-analog hybrid circuit segmentation method based on excitation control. Background Art

[0002] Comprehensive defect simulation in the integrated circuit design stage is the basic guarantee for improving testability. At present, analog / hybrid integrated circuits are widely used in critical systems related to life safety, such as automobiles and aircraft. Such safety-critical systems usually require a defect rate of less than one part per million (0DPPM) as a quality target, which makes defect testability analysis of integrated circuits urgently needed. There are 6 types of basic defect models for a single MOS tube in the circuit. The defect set of analog / hybrid integrated circuits containing thousands of devices is extremely large. It is very time-consuming to inject a large number of defects one by one and perform large-scale matrix calculations and solutions. In fact, complete defect simulation often takes months or even years. Reducing the time consumption of defect simulation is a bottleneck hot issue in the research of hybrid circuit defect diagnosis. The academic community has a series of existing research methods for this problem, which can be roughly divided into two categories: the first category is to reduce the total number of simulated defects, and the second category is to use circuit segmentation to reduce the circuit scale to reduce the time loss of simulating each defect. The disadvantage of the first method is that it only simulates representative defects, which cannot meet the requirements of automotive-grade chips that must simulate all defects to ensure safety. The second method usually requires changes to the physical circuit. Summary of the invention

[0003] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a method for segmenting a mixed digital-analog circuit based on excitation control. Based on a directed dependency graph and signal flow analysis, a controlled blocked MOS set is obtained, and the mixed digital-analog circuit is segmented accordingly to facilitate circuit defect simulation.

[0004] In order to achieve the above-mentioned object of the invention, the digital-analog hybrid circuit segmentation method based on excitation control of the present invention comprises the following steps:

[0005] S1: Modeling the digital-analog mixed circuit with a directed dependency graph according to the SPICE netlist of the digital-analog mixed circuit to obtain a directed dependency graph G;

[0006] S2: Divide all the power supplies in the mixed digital-analog circuit into digital power supplies and analog power supplies. The number of digital power supplies is K. Then set the voltage value of the digital power supply to high or low, and the voltage value of the analog power supply to the default value in the SPICE netlist. M power supply value modes are obtained, where M = 2 K; Perform digital path identification sensitization in each power value mode, and use the MOS tube that is cut off due to digital power control in the power value mode as the controlled blocked MOS, so as to obtain the controlled blocked MOS set Block_MOS in each power value mode m , m=1,2,…,M;

[0007] S3: For the mth power value mode, disconnect the controlled blocked MOS set Block_MOS in the directed dependency graph m The unidirectional edges represented by all MOS gate edges in the graph are used to obtain the directed dependency graph g. m ; Then the preset strongly connected component algorithm is used to identify the directed dependency graph g m The maximal strongly connected block is used as the circuit block SCC m,n , where n = 1, 2, ..., N m , N m Represents a directed dependency graph g m The number of identified circuit blocks is used to obtain the circuit segmentation results under each power supply value mode.

[0008] The invention discloses a method for segmenting a digital-analog hybrid circuit based on excitation control, models the digital-analog hybrid circuit to obtain a directed dependency graph, divides all power supplies in the digital-analog hybrid circuit into digital power supplies and analog power supplies to obtain different power supply value modes, performs digital path identification sensitization under each power supply value mode to obtain a controlled blocked MOS set, disconnects all MOS gate edges in the controlled blocked MOS set in the directed dependency graph for each power supply value mode to obtain a corresponding directed dependency graph, identifies a maximal strongly connected block as a circuit block, and thereby obtains a circuit segmentation result under each power supply value mode.

[0009] The present invention has the following beneficial effects:

[0010] 1) The method of the present invention realizes SCC splitting by exciting and controlling the MOS tube to be cut off, and no modification of the physical circuit is required;

[0011] 2) The circuit blocks obtained by segmentation in the present invention are weakly connected, that is, there are no loops between the circuit blocks, which facilitates the industry to conduct parallel simulation of circuit defects and greatly accelerates the circuit testability analysis and design process. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a flowchart of a specific implementation method of the digital-analog hybrid circuit segmentation method based on excitation control of the present invention;

[0013] Figure 2 This is an example diagram of a directed dependency graph model of commonly used circuit elements;

[0014] Figure 3is a flow chart of a digital path identification sensitization method based on breadth-first search in this embodiment;

[0015] Figure 4 is a flow chart for identifying a set of contribution controlled blocked MOS in this embodiment;

[0016] Figure 5 is an example diagram for identifying a set of contributing controlled blocked MOS in this embodiment;

[0017] Figure 6 is a flow chart of circuit block merging in this embodiment;

[0018] Figure 7 is a flow chart of circuit block sequencing in this embodiment;

[0019] Figure 8 is an example diagram of circuit block merging in this embodiment;

[0020] Fig. 9 : is the bandgap circuit diagram in this embodiment;

[0021] Fig.10 It is a circuit block signal flow diagram in the power supply value mode of this embodiment. DETAILED DESCRIPTION

[0022] The specific implementation of the present invention is described below in conjunction with the accompanying drawings so that those skilled in the art can better understand the present invention. It should be noted that in the following description, when the detailed description of known functions and designs may dilute the main content of the present invention, these descriptions will be omitted here.

[0023] Example

[0024] Figure 1 FIG. 1 is a flow chart of a specific implementation of the method for segmenting a digital-analog hybrid circuit based on excitation control of the present invention. Figure 1 As shown, the specific steps of the digital-analog hybrid circuit segmentation method based on excitation control of the present invention include:

[0025] S101: Directed Dependency Graph Modeling:

[0026] A directed dependency graph is constructed for the mixed digital-analog circuit according to the SPICE netlist of the mixed digital-analog circuit to obtain a directed dependency graph G. Figure 2 This is an example diagram of a directed dependency graph model for commonly used circuit elements.

[0027] S102: Digital Pathway Identification Sensitization:

[0028] Divide all the power supplies in the mixed digital-analog circuit into digital power supplies and analog power supplies, and record the number of digital power supplies as K. Then set the voltage value of the digital power supply to high or low, and the voltage value of the analog power supply to the default value in the SPICE netlist, and obtain M power supply value patterns, where M = 2 K Digital path identification and sensitization are performed in each power value mode, and the MOS tube that is cut off due to digital power control in the power value mode is regarded as a controlled blocked MOS, so as to obtain a controlled blocked MOS set Block_MOS in each power value mode. m , m=1,2,…,M.

[0029] The specific algorithm for digital path identification and sensitization can be selected according to actual needs. In this embodiment, a digital path identification and sensitization method based on breadth-first search is proposed. Figure 3 FIG. 4 is a flow chart of the digital path identification sensitization method based on breadth-first search in this embodiment. Figure 3 As shown, the specific steps of the digital path identification sensitization method based on breadth-first search in this embodiment include:

[0030] S301: Initialization data:

[0031] Initialize access collection Voltage Node Queue Path Queue Then, K digital power supplies are added to the access set A and the voltage node queue B, and then K paths are added to the path queue C, where the starting voltage node of the kth path is the kth digital power supply, k=1,2,…,K.

[0032] S302: Get voltage node:

[0033] The voltage node i is taken out from the voltage node queue B and deleted from the node queue B, and then the neighbor voltage node set N(i) of the voltage node i is obtained according to the directed dependency graph.

[0034] S303: Get neighbor voltage nodes:

[0035] The neighbor voltage node j is taken out from the neighbor voltage node set N(i) and deleted from the neighbor voltage node set N(i).

[0036] S304: Determine whether the neighbor voltage node j∈A, that is, whether the neighbor voltage node j has been visited. If yes, proceed to step S310, otherwise proceed to step S305.

[0037] S305: Determine whether the neighbor voltage node j corresponds to a MOS gate, if yes, proceed to step S306, otherwise proceed to step S308.

[0038] S306: Determine the on / off state of the MOS gate:

[0039] If the voltage node i is at a high level and the neighboring voltage node j corresponds to the NMOS gate, or the voltage node i is at a low level and the neighboring voltage node j corresponds to the PMOS gate, the MOS gate state is determined to be on, otherwise the MOS gate state is determined to be off.

[0040] S307: Determine whether the MOS gate state is on, if yes, proceed to step S308, otherwise proceed to step S310.

[0041] S308: Update data:

[0042] Add the neighbor voltage node j to the access set A and the voltage node queue B, and add the neighbor voltage node j to the path queue C behind the path where the voltage node i is located.

[0043] S309: Update neighbor voltage node voltage:

[0044] Traverse the starting point and ending point dictionary of the directed dependency graph. If voltage node i is not the starting point and neighbor voltage node j is the ending point, update the voltage of neighbor voltage node j to the voltage of the starting point of the corresponding path, that is, if the starting point is a high voltage, set the neighbor voltage node j to a high voltage; if the starting point is a low voltage, set the neighbor voltage node j to a low voltage; if it is other cases, update the voltage of neighbor voltage node j to the voltage of voltage node i.

[0045] S310: Determine whether the neighbor node set N(i) is empty. If so, proceed to step S311; otherwise, return to step S303.

[0046] S311: Determine whether the voltage node queue B is empty. If so, identification sensitization is completed and the process goes to step S312; otherwise, the process returns to step S302.

[0047] S312: Output recognition sensitization result:

[0048] The voltage state of each voltage node or the gate state of the MOS tube corresponding to the voltage node is output to obtain the identification sensitization result.

[0049] According to the above description, in each power value selection mode, the present embodiment propagates each digital power signal along the signal flow direction according to the breadth-first strategy. If the signal flow encounters an analog device, a MOS tube source or a drain during active propagation, the signal flow stops propagating on the path, that is, only circuit devices with digital characteristics are sensitized, and finally the voltage level of each voltage node on the digital path and the gate-controlled on-off status of each MOS tube are obtained.

[0050] according to Figure 2From the analysis of the commonly used components directed dependency graph model recognized by the academic community, it can be known that within a maximum strongly connected block (Strongly Connected Components, SCC), it is possible to achieve SCC splitting by disconnecting the unidirectional edge represented by the MOS tube gate or the bidirectional edge of the device, but the on and off of the bidirectional edge of the device is difficult to be accurately controlled by excitation. In order to achieve excitation control circuit splitting, the unidirectional edge corresponding to the MOS tube gate edge in the controlled and blocked MOS set in a certain power value mode in the directed graph can be disconnected to achieve circuit splitting in the power value mode. It has been found through research that not all controlled blocked MOS in the controlled and blocked MOS set contribute to SCC splitting. By disconnecting the unidirectional edges inside the SCC and identifying the SCC shrinkage points, it is possible to analyze which unidirectional edges that are disconnected are useful for SCC splitting. If the MOS tube gates represented by these unidirectional edges appear in the controlled and blocked MOS set of a certain power value mode, these MOS are called contributing controlled and blocked MOS in the power value mode.

[0051] In a directed graph, the block effect achieved by disconnecting only the gate edge of the contributing controlled blocked MOS is consistent with that achieved by disconnecting the gate edge of the entire controlled blocked MOS set. The purpose of doing this is: first, it can help to further understand the contribution of controlled blocked MOS in SCC splitting (for example, which controlled blocked MOS realizes the splitting of which SCC); second, in the defect block parallel simulation stage, it is only necessary to ensure that the injected defects do not cause the contributing controlled blocked MOS to remain cut off, which will not affect the circuit block results and thus will not affect the defect parallel simulation. Therefore, identifying the contributing controlled blocked MOS is helpful for simulating and analyzing the testability of more defects during simulation. Therefore, in this embodiment, the controlled blocked MOS set Block_MOS can also be identified. m Further optimization is performed to identify and retain the contributing controlled obstructed MOS, and delete the remaining controlled obstructed MOS. Figure 4 FIG. 4 is a flow chart of identifying a set of contribution controlled blocked MOS in this embodiment. Figure 4 As shown, the specific steps of identifying the contribution controlled blocked MOS set in this embodiment include:

[0052] S401: Preliminary identification of circuit blocks:

[0053] The preset strongly connected component algorithm is used to preliminarily identify the maximum strongly connected block of the directed dependency graph G as the circuit block SCC d , where d = 1, 2, …, D, and D represents the number of circuit blocks initially identified.

[0054] A strongly connected component refers to a set of nodes in a graph, where any two nodes can reach each other. In this embodiment, the strongly connected component algorithm adopts the Tarjan algorithm, which is a classic algorithm for finding strongly connected components in a graph and is widely used in graph theory and network analysis.

[0055] S402: Identify candidate contributing MOS tubes:

[0056] In the directed dependency graph G, disconnect all circuit blocks SCC d The internal unidirectional edges of , get the directed dependency graph G′, and use the same strongly connected component algorithm to identify the maximum strongly connected block as the circuit block again. At this time, some circuit blocks may be split into more than two sub-circuit blocks, so for the original circuit block SCC d , determine whether it is split into two or more sub-circuit blocks in the re-identification result. If not, do nothing. If yes, record its sub-circuit block as SCC d,r ,r=1,2,…,R d , R d Indicates circuit block SCC d The number of sub-circuit blocks is obtained after re-identification, and then each sub-circuit block SCC d,r As the circuit block shrink point, search for the circuit block SCC in the directed dependency graph G d The one-way edge between any two contraction points in the circuit is used to determine whether there is a MOS transistor gate on the one-way edge. If so, the corresponding MOS transistor is used as a candidate contributing MOS transistor. Otherwise, no operation is performed. The candidate contributing MOS transistors of the entire circuit form a candidate contributing MOS set Key_MOS m .

[0057] S403: Determine the contributing MOS tube:

[0058] Traverse the candidate contributing MOS set Key_MOS m Each MOS tube in, if it belongs to the controlled blocked MOS set Block_MOS m , it is treated as a contributing controlled obstructed MOS, otherwise no action is taken.

[0059] Figure 5 ] is an example diagram for identifying a set of contribution controlled obstructed MOS in this embodiment. Figure 5As shown in the figure, taking the Widlar bias generator as an example, the Tarjan algorithm can identify three maximal strongly connected components, that is, three circuit blocks. The circuit block SCC2 is used to illustrate the process of identifying the set of contributing controlled obstructed MOS. First, the unidirectional edge inside SCC2 is disconnected, which will disconnect V3->I4 and V2->I7. Then, the Tarjan algorithm is used to identify two maximal strongly connected components S1 and S2, that is, two circuit block contractions are obtained, which are also the target of splitting SCC2. According to V3->I4 and V2->I7, the directions of contractions S1 and S2 can be restored. Because once the directions between contractions are restored, these contractions will become a large SCC, so the directions between contractions must be on the loop between contractions, so disconnecting any direction between contractions can achieve the disconnection of a certain loop. Because the direction relationship between contractions S1 and S2 is S1->S2, S2->S1, it is only necessary to disconnect S1->S2 or S2->S1 to achieve the splitting of SCC. The path included in S1->S2 is V3->I4, and the path included in S2->S1 is V2->I7. Therefore, the MOS gate represented by V3->I4 is a group of contributing MOS, and the MOS gate represented by V2->I7 is a group of contributing MOS. It is worth noting that the direction between the shrinking points may not only contain one MOS gate edge. In some circuits, it is possible that the path included in S1->S2 is n MOS gate edges. In this case, these n MOS gate edges are a group of contributing MOS. Only when this group of contributing MOS gate edges is disconnected at the same time can S1->S2 be disconnected.

[0060] S103: Determine the circuit segmentation result:

[0061] For the mth power value mode, disconnect the controlled blocked MOS set Block_MOS in the directed dependency graph m The unidirectional edges represented by all MOS gate edges in the graph are used to obtain the directed dependency graph g. m Then the preset strongly connected component algorithm is used to identify the directed dependency graph g m The maximal strongly connected block is used as the circuit block SCC m,n , where n = 1, 2, ..., N m , N m Represents a directed dependency graph g m The number of identified circuit blocks is used to obtain the circuit segmentation results under each power supply value mode.

[0062] Since the invention directly disconnects the gate edge of the MOS tube in the controlled blocked MOS set before identifying the strongly connected components, the granularity of the circuit block may be too small, that is, each sub-circuit block is a component circuit contained in an SCC, and such a sub-circuit block may have too few components, resulting in uneven block division or too many blocks, which increases the complexity of the simulation operation. In view of such a situation, this embodiment proposes a circuit block merging method, which takes the number of devices Q of the circuit block with the largest number of devices as the upper limit, and continuously merges multiple circuit blocks into one block in topological order. In this way, under the premise of ensuring the correctness of the order of defect transfer simulation, it gives priority to minimizing the defect parallel simulation time while making the number of blocks as uniform as possible, thereby obtaining a better block simulation effect. Figure 6 is a flow chart of circuit block merging in this embodiment. Figure 6 As shown, the specific steps of merging circuit blocks in this embodiment include:

[0063] S601: Circuit block topology sorting:

[0064] For the mth power supply mode N m Circuit Block SCC m,n Perform topological sorting to obtain the circuit block topological sequence List m . Figure 7 is a flowchart of circuit block sequencing in this embodiment. Figure 7 As shown, the specific steps of topological sorting of circuit blocks in this embodiment include:

[0065] S701: Initialize circuit block topology sequence List m Is empty.

[0066] S702: Calculate the in-degree of each circuit block:

[0067] Calculate N m Circuit Block SCC m,n IN m,n .

[0068] S703: Obtain zero-in-degree circuit block sequence:

[0069] All current in-degree IN m,n = 0 circuit block SCC m,n Construct a zero-indegree circuit block sequence Z m .

[0070] S704: Zero-in-degree circuit block sorting:

[0071] The current zero-indegree circuit block sequence Z m All circuit blocks in are sorted from large to small according to their out-degree.

[0072] S705: Add circuit block:

[0073] From the zero-indegree circuit block sequence Z m Take out the first circuit block Add to circuit block topology sequence List m The end of .

[0074] S706: Update the neighbor circuit block in-degree:

[0075] The circuit block The in-degree of each neighbor circuit block is reduced by 1, and then the neighbor circuit blocks with in-degree 0 after the update are added to the zero-in-degree circuit block sequence Z m .

[0076] S707: Determine the zero-in-degree circuit block sequence Z m Is it empty? If so, the topological sorting ends; otherwise, return to step S704.

[0077] Only after topological sorting can adjacent circuit blocks be combined into one, so as to ensure that the weak connectivity relationship between the merged circuit blocks is correct.

[0078] S602: Locate the circuit block with the largest number of components:

[0079] Traverse the circuit block topology sequence List m Each circuit block where n v Represents the circuit block topology sequence List m The original serial number of the vth circuit block in the figure, v = 1, 2, ..., N, locates the circuit block with the largest number of devices The number of devices is recorded as H.

[0080] S603: Merge circuit blocks:

[0081] Separate circuit blocks The two circuit blocks before and after the starting point are used as the starting point to search forward or backward. If the cumulative number of devices of the circuit block before or after the starting point and the starting point circuit block does not exceed H, it will be merged with the starting point circuit block, and then the merged circuit block will be used as the new starting point circuit block. If the cumulative number of devices of the circuit block before or after the starting point and the starting point circuit block exceeds H, the circuit block before or after the starting point will be used as the new starting point circuit block until all circuit blocks are searched.

[0082] Figure 8 is an example diagram of circuit block merging in this embodiment. Figure 8As shown in the figure, each circle node represents a circuit block, and the number represents the number of components contained in the circuit block. If the split circuit is directly simulated in blocks, the maximum number of devices reaches 100 and the minimum number of sub-module components is only 10, resulting in uneven block division or too many blocks. Therefore, these circuit blocks can be sorted in topological order, and circuit blocks with continuous topological order can be merged. The upper limit of the number of devices contained in the merged circuit block is 100. The result after merging is shown in the dotted box. In this way, so many circuit blocks can be merged into 3 weakly connected circuit blocks with 100 devices each, which is conducive to subsequent defect parallel simulation.

[0083] In order to better illustrate the technical effect of the present invention, a specific example is used to experimentally verify the present invention. In this embodiment, a bandgap circuit in a Benchmark reference circuit is used as an example for explanation. Fig. 9 : is the bandgap circuit diagram in this embodiment. Fig. 9 As shown, the maximum voltage available for the bandgap circuit is 2.5 V and the minimum voltage is 0 V. The method of the present invention is used to segment the bandgap circuit to obtain circuit blocks, namely, each maximally connected block SCC and its weakly connected relationship. The segmented circuit blocks are all weakly connected without loops, and defect parallel simulation can be realized.

[0084] The digital power supply of the bandgap circuit is V3, so it has two power supply value modes: V3 is a high voltage or V3 is a low voltage, which are respectively recorded as V3_high and V3_low. All the identified controlled blocked MOS sets in each power supply value mode are used to perform circuit segmentation. Table 1 is a list of the results of circuit segmentation using all controlled blocked MOS sets in this embodiment.

[0085]

[0086] Table 1

[0087] Then, only the controlled blocked MOS sets that contribute to the split SCC identified by the contributing controlled blocked MOS identification algorithm are used for circuit segmentation. Table 2 is a list of results of circuit segmentation using the contributing controlled blocked MOS sets in this embodiment.

[0088]

[0089] Table 2

[0090] Comparing Table 1 and Table 2, it can be seen that compared with directly identifying each circuit block of the circuit, whether all the controlled blocked MOS in each power supply value mode mentioned in the present invention are used for circuit segmentation or only the controlled blocked MOS that contributes to the split SCC is used for circuit segmentation, more SCCs can be split, thereby reducing the number of devices of the maximum SCC and reducing the time for defect parallel simulation. In addition, the final results of the circuit segmentation in Table 1 and Table 2 are consistent, proving that the controlled blocked MOS that contributes to the split SCC identified by the present invention has high accuracy. Compared with using all controlled blocked MOS in the pattern to achieve circuit segmentation, the biggest advantage of using only the controlled blocked MOS that contributes to the split SCC in the pattern is that it is convenient for subsequent defect parallel simulation, so that the situation of injecting a defect to turn on the controlled blocked MOS and thus destroying the block result is minimized (this situation is originally an occasional situation, but using fewer controlled blocked MOS in the block can further reduce the occurrence of this situation).

[0091] By comparing the situations before and after the circuit blocks are merged, it can be seen that the number of components contained in the circuit blocks is more uniform after the circuit blocks are merged, which is conducive to the subsequent parallel simulation of circuit defects.

[0092] After the mixed digital-analog circuit is segmented by the present invention, a netlist of defective parallel simulation circuit blocks and their IO ports under various power supply value modes will eventually be obtained. Before performing defective parallel simulation, it is necessary to first perform overall simulation of the non-defective circuit to know the voltage value of the IO port of each circuit block, and use the I port voltage value of each circuit block as the power supply of each circuit block during parallel simulation. Fig.10 It is a circuit block signal flow diagram in the power supply value mode of this embodiment. Fig.10 The number of devices in each divided circuit block and the connectivity between the circuit blocks are shown. Fig.10 As shown, by using the present invention to segment the digital-analog hybrid circuit, the circuit segmentation results under various power supply value modes can be obtained without changing the physical circuit design. The segmented circuit blocks show a loop-free weak connectivity relationship, and defect parallel simulation can be performed, which greatly accelerates the testability analysis speed of large-scale digital-analog hybrid integrated circuits.

[0093] Although the above describes the illustrative specific embodiments of the present invention to facilitate those skilled in the art to understand the present invention, it should be clear that the present invention is not limited to the scope of the specific embodiments. For those of ordinary skill in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the attached claims, these changes are obvious, and all inventions and creations using the concept of the present invention are protected.

Claims

1. A method for segmenting a digital-analog hybrid circuit based on excitation control, characterized in that: The following steps are involved: S1: Modeling the digital-analog mixed circuit with a directed dependency graph according to the SPICE netlist of the digital-analog mixed circuit to obtain a directed dependency graph G; S2: Divide all the power supplies in the mixed digital-analog circuit into digital power supplies and analog power supplies. The number of digital power supplies is K. Then set the voltage value of the digital power supply to high or low, and the voltage value of the analog power supply to the default value in the SPICE netlist. M power supply value modes are obtained, where M = 2 K ; Perform digital path identification sensitization in each power value mode, and use the MOS tube that is cut off due to digital power control in the power value mode as the controlled blocked MOS, so as to obtain the controlled blocked MOS set Block_MOS in each power value mode m , m=1,2,…,M; S3: For the mth power value mode, disconnect the controlled blocked MOS set Block_MOS in the directed dependency graph m The unidirectional edges represented by all MOS gate edges in the graph are used to obtain the directed dependency graph g. m ; Then the preset strongly connected component algorithm is used to identify the directed dependency graph g m The maximal strongly connected block is used as the circuit block SCC m,n , where n = 1, 2, ..., N m , N m Represents a directed dependency graph g m The number of identified circuit blocks is used to obtain the circuit segmentation results under each power supply value mode.

2. The method for dividing a digital-analog hybrid circuit according to claim 1, characterized in that: The digital path identification sensitization method in step S2 comprises the following steps: 1) Initialize access collection Voltage Node Queue Path Queue Then, K digital power supplies are added to the access set A and the voltage node queue B, and then K paths are added to the path queue C, where the starting voltage node of the kth path is the kth digital power supply, k = 1, 2, ..., K; 2) taking out voltage node i from voltage node queue B and deleting it from voltage node queue B, and then obtaining neighboring voltage node set N(i) of voltage node i according to the directed dependency graph; 3) taking out neighbor voltage node j from the neighbor voltage node set N(i) and deleting it from the neighbor voltage node set N(i); 4) Determine whether the neighbor voltage node j∈A, that is, whether the neighbor voltage node j has been visited, if yes, proceed to step 10), otherwise proceed to step 5); 5) Determine whether the neighbor voltage node j corresponds to a MOS gate, if yes, proceed to step 6), otherwise proceed to step 8); 6) If the voltage node i is at a high level and the neighboring voltage node j corresponds to the NMOS gate, or the voltage node i is at a low level and the neighboring voltage node j corresponds to the PMOS gate, the MOS gate state is determined to be on, otherwise the MOS gate state is determined to be off; 7) Determine whether the MOS gate state is on, if yes, proceed to step 8), otherwise proceed to step 10); 8) Add the neighbor voltage node j to the access set A and the voltage node queue B, and add the neighbor voltage node j to the path queue C after the path where the voltage node i is located; 9) Traverse the start-end dictionary of the directed dependency graph. If the voltage node i is not the start point and the neighbor voltage node j is the end point, update the voltage of the neighbor voltage node j to the voltage of the corresponding path start point, that is, if the start point is a high voltage, set the neighbor voltage node j to a high voltage; if the start point is a low voltage, set the neighbor voltage node j to a low voltage; if it is other cases, update the voltage of the neighbor voltage node j to the voltage of the voltage node i; 10) Determine whether the neighbor node set N(i) is empty, if so, proceed to step 11), otherwise return to step 3); 11): Determine whether the voltage node queue B is empty. If so, identification sensitization is completed and go to step 12), otherwise return to step 2); 12) Output the voltage state of each voltage node or the gate state of the MOS tube corresponding to the voltage node to obtain the identification sensitization result.

3. The method for dividing a digital-analog hybrid circuit according to claim 1, characterized in that: In step S2, from the controlled blocked MOS set Block_MOS m Identify the contributing controlled blocked MOS and retain them, and delete the remaining controlled blocked MOS. The specific method for identifying the contributing controlled blocked MOS is: 1) Use the preset strongly connected component algorithm to preliminarily identify the maximum strongly connected block of the directed dependency graph G as the circuit block SCC d , where d = 1, 2, ..., D, D represents the number of circuit blocks initially identified; 2) In the directed dependency graph G, disconnect all circuit blocks SCC d The internal unidirectional edges of , get the directed dependency graph G′, use the same strongly connected component algorithm to identify the maximum strongly connected block as the circuit block again; for the original circuit block SCC d , determine whether it is split into two or more sub-circuit blocks in the re-identification result. If not, do nothing. If yes, record its sub-circuit block as SCC d,r ,r=1,2,…,R d , R d Indicates circuit block SCC d The number of sub-circuit blocks is obtained after re-identification, and then each sub-circuit block SCC d,r As the circuit block shrink point, search for the circuit block SCC in the directed dependency graph G d The one-way edge between any two contraction points in the circuit is used to determine whether there is a MOS tube gate on the one-way edge. If so, the corresponding MOS tube is used as a candidate contributing MOS tube, otherwise no operation is performed; the candidate contributing MOS tubes of the entire circuit are used to form a candidate contributing MOS set Key_MOS m ; 3) Traverse the candidate contributing MOS set Key_MOS m Each MOS tube in, if it belongs to the controlled blocked MOS set Block_MOS m , it is treated as a contributing controlled obstructed MOS, otherwise no action is taken.

4. The method for dividing a digital-analog hybrid circuit according to claim 1, characterized in that: In step S3, each directed dependency graph g m The maximal strongly connected block SCC m,n To merge, the specific method is: 1) For the mth power supply mode N m Circuit Block SCC m,n Perform topological sorting to obtain the circuit block topological sequence List m ; The specific method of topological sorting is: a) Initialize the circuit block topology sequence List m is empty; b) Calculate N m Circuit Block SCC m,n IN m,n ; c) All current in-degree IN m,n = 0 circuit block SCC m,n Construct a zero-indegree circuit block sequence Z m ; d) The current zero-in-degree circuit block sequence Z m All circuit blocks in are sorted from large to small according to their out-degree; e) From the zero-indegree circuit block sequence Z m Take out the first circuit block Add to circuit block topology sequence List m The end of f) The circuit block The in-degree of each neighbor circuit block is reduced by 1, and then the neighbor circuit blocks with in-degree 0 after the update are added to the zero-in-degree circuit block sequence Z m ; g) Determine the zero-in-degree circuit block sequence Z m Is it empty? If so, the topological sorting ends, otherwise return to step d); 2) Traverse the circuit block topology sequence List m Each circuit block where n v Represents the circuit block topology sequence List m The original serial number of the vth circuit block in the figure, v = 1, 2, ..., N, locates the circuit block with the largest number of devices The number of devices is recorded as H; 3) Separate the circuit blocks The two circuit blocks before and after the starting point are used as the starting point to search forward or backward. If the cumulative number of devices of the circuit block before or after the starting point and the starting point circuit block does not exceed H, it will be merged with the starting point circuit block, and then the merged circuit block will be used as the new starting point circuit block. If the cumulative number of devices of the circuit block before or after the starting point and the starting point circuit block exceeds H, the circuit block before or after the starting point will be used as the new starting point circuit block until all circuit blocks are searched.

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