Method for partitioning digital-analog hybrid circuits based on excitation control

Abstract

The application discloses a digital-analog mixed circuit segmentation method based on excitation control, models the digital-analog mixed circuit to obtain a directed dependency graph, divides all power supplies in the digital-analog mixed circuit into digital power supplies and analog power supplies to obtain different power supply value modes, identifies sensitization of a digital channel under each power supply value mode to obtain a controlled and blocked MOS set, breaks all one-way edges represented by MOS gate edges in the controlled and blocked MOS set in the directed dependency graph for each power supply value mode to obtain a corresponding directed dependency graph, identifies a maximum strong connected block as a circuit block, and thus obtains circuit segmentation results under each power supply value mode. The application is based on the directed dependency graph and signal flow analysis, obtains the controlled and blocked MOS set, and segments the digital-analog mixed circuit according to the controlled and blocked MOS set, so that circuit defect simulation is facilitated.

Description

Technical Field

[0001] This invention belongs to the field of mixed-signal circuit technology, and more specifically, relates to a method for segmenting mixed-signal circuits based on excitation control. Background Technology

[0002] Comprehensive defect simulation during the integrated circuit design phase is fundamental to improving testability. Currently, analog / hybrid integrated circuits are widely used in critical systems related to life safety, such as automobiles and aircraft. These safety-critical systems typically require a defect rate of less than one part per million (0DPPM) as a quality target, making defect testability analysis of integrated circuits urgently needed. There are six basic defect models for a single MOSFET in a circuit, and the defect set of analog / hybrid integrated circuits containing tens of thousands of devices is extremely large. Successively injecting a large number of defects and performing large-scale matrix operations is very time-consuming; in fact, complete defect simulation often takes months or even years. Reducing the time consumption of defect simulation is a bottleneck and hot topic in hybrid circuit defect diagnosis research. The academic community has developed a series of research methods to address this problem, broadly divided into two categories: the first is to reduce the total number of defects simulated, and the second is to use circuit partitioning to reduce the circuit size and thus reduce the time consumption for simulating each defect. The drawback of the first method is that it only simulates representative defects, which cannot meet the requirement of simulating all defects to ensure safety for automotive-grade chips. The second method usually requires changes to the physical circuit. Summary of the Invention

[0003] The purpose of this invention is to overcome the shortcomings of the prior art and provide a method for segmenting mixed-signal circuits based on excitation control. Based on directed dependency graphs and signal flow analysis, a controlled and resisted MOS set is obtained, and the mixed-signal circuit is segmented accordingly to facilitate circuit defect simulation.

[0004] To achieve the above-mentioned objective, the present invention provides a mixed-signal circuit segmentation method based on excitation control, comprising the following steps:

[0005] S1: Based on the SPICE netlist of the mixed-signal circuit, perform directed dependency graph modeling on the mixed-signal circuit to obtain the directed dependency graph G;

[0006] S2: Divide all power supplies in the mixed-signal circuit into digital power supplies and analog power supplies. Let K be the number of digital power supplies. Then, set the voltage values ​​of the digital power supplies to high or low, and the voltage values ​​of the analog power supplies to the default values ​​in the SPICE netlist, resulting in M ​​power supply value modes, where M = 2. KDigital path identification sensitization is performed for each power supply mode. The MOSFETs that are turned off due to digital power supply control in that power supply mode are identified as controlled-resistance MOSFETs, thus obtaining the controlled-resistance MOSFET set Block_MOS for each power supply mode. m m = 1, 2, ..., M;

[0007] S3: For the m-th power supply mode, disconnect the controlled and hindered MOS set Block_MOS in the directed dependency graph. m The directed dependency graph g is obtained by taking the unidirectional edges represented by all MOS gate edges. m Then, a pre-defined strongly connected component algorithm is used to identify the directed dependency graph g. m The maximally strongly connected component as a circuit block SCC m,n where n = 1, 2, ..., N m N m Represents a directed dependency graph g m The number of identified circuit blocks is used to obtain the circuit segmentation results under each power supply value mode.

[0008] This invention relates to a mixed-signal circuit segmentation method based on excitation control. The mixed-signal circuit is modeled to obtain a directed dependency graph. All power supplies in the mixed-signal circuit are divided into digital power supplies and analog power supplies, resulting in different power supply value modes. For each power supply value mode, digital path identification and sensitization are performed to obtain a controlled-resistance MOS set. For each power supply value mode, all unidirectional edges represented by the gate edges of the controlled-resistance MOS set are disconnected in the directed dependency graph to obtain the corresponding directed dependency graph. Maximum strongly connected components are identified as circuit blocks, thereby obtaining the circuit segmentation results for each power supply value mode.

[0009] The present invention has the following beneficial effects:

[0010] 1) The present invention achieves SCC splitting by excitation control of MOS transistor cutoff, which eliminates the need for any modification to the physical circuitry;

[0011] 2) The circuit blocks obtained by the present invention exhibit weak connectivity, that is, there are no loops between the circuit blocks, which facilitates parallel simulation of circuit defects in the industry and greatly accelerates the circuit testability analysis and design process. Attached Figure Description

[0012] Figure 1 This is a flowchart illustrating a specific implementation of the mixed-signal circuit segmentation method based on excitation control according to the present invention.

[0013] Figure 2 This is an example diagram of a directed dependency graph model of commonly used circuit elements;

[0014] Figure 3This is a flowchart of the digital pathway identification sensitization method based on breadth-first search in this embodiment;

[0015] Figure 4 This is a flowchart for identifying the MOS set with controlled and hindered contribution in this embodiment;

[0016] Figure 5 This is an example diagram illustrating the identification of the controlled-resistance MOS set in this embodiment;

[0017] Figure 6 This is a flowchart of the circuit block merging process in this embodiment;

[0018] Figure 7 This is a flowchart of the circuit block sorting in this embodiment;

[0019] Figure 8 This is an example diagram of the merging of circuit blocks in this embodiment;

[0020] Figure 9 This is the bandgap circuit diagram in this embodiment;

[0021] Figure 10 This is the circuit block signal flow diagram in the power supply value mode of this embodiment. Detailed Implementation

[0022] The specific embodiments of the present invention will now be described with reference to the accompanying drawings to enable those skilled in the art to better understand the invention. It should be particularly noted that in the following description, detailed descriptions of known functions and designs that might obscure the main content of the invention will be omitted here.

[0023] Example

[0024] Figure 1 This is a flowchart illustrating a specific implementation of the mixed-signal circuit segmentation method based on excitation control according to the present invention. Figure 1 As shown, the specific steps of the excitation control-based mixed-signal circuit segmentation method of the present invention include:

[0025] S101: Directed Dependency Graph Modeling:

[0026] Based on the SPICE netlist of the mixed-signal circuit, a directed dependency graph model is performed on the mixed-signal circuit to obtain the directed dependency graph G. Figure 2 This is an example diagram of a directed dependency graph model for commonly used circuit elements.

[0027] S102: Digital Pathway Recognition Sensitization:

[0028] All power supplies in the mixed-signal circuit are divided into digital power supplies and analog power supplies. The number of digital power supplies is denoted as K. The voltage values ​​of the digital power supplies are set to high or low, and the voltage values ​​of the analog power supplies are set to default values ​​in the SPICE netlist, resulting in M ​​power supply value patterns, where M = 2. K Digital path identification sensitization is performed for each power supply mode. The MOSFETs that are turned off due to digital power supply control in that power supply mode are identified as controlled-resistance MOSFETs, thus obtaining the controlled-resistance MOSFET set Block_MOS for each power supply mode. m , m=1,2,…,M.

[0029] The specific algorithm for digital pathway identification sensitization can be selected according to actual needs. In this embodiment, a digital pathway identification sensitization method based on breadth-first search is proposed. Figure 3 This is a flowchart of the digital path identification sensitization method based on breadth-first search in this embodiment. For example... Figure 3 As shown, the specific steps of the digital path identification sensitization method based on breadth-first search in this embodiment include:

[0030] S301: Initialize data:

[0031] Initialize access collection Voltage node queue Path queue Then, add the K digital power sources to the access set A and the voltage node queue B, and then add K paths to the path queue C. The starting voltage node of the k-th path is the k-th digital power source, k = 1, 2, ..., K.

[0032] S302: Extract voltage node:

[0033] Take voltage node i from voltage node queue B and remove it from node queue B. Then obtain the set N(i) of neighboring voltage nodes of voltage node i according to the directed dependency graph.

[0034] S303: Extract neighboring voltage node:

[0035] Remove neighbor voltage node j from the neighbor voltage node set N(i) and delete it from the neighbor voltage node set N(i).

[0036] S304: Determine whether the neighboring voltage node j∈A has been visited. If yes, proceed to step S310; otherwise, proceed to step S305.

[0037] S305: Determine whether the neighboring voltage node j corresponds to the MOS gate. If yes, proceed to step S306; otherwise, proceed to step S308.

[0038] S306: Determine the MOS gate on / off state:

[0039] If voltage node i is high and the neighboring voltage node j corresponds to the NMOS gate, or if voltage node i is low and the neighboring voltage node j corresponds to the PMOS gate, then the MOS gate state is determined to be on; otherwise, the MOS gate state is determined to be off.

[0040] S307: Determine whether the MOS gate state is on. If yes, proceed to step S308; otherwise, proceed to step S310.

[0041] S308: Updated data:

[0042] Add the neighbor voltage node j to the access set A and the voltage node queue B. Add the neighbor voltage node j to the path queue C after the path where voltage node i is located.

[0043] S309: Update neighboring node voltages:

[0044] Traverse the start and end point dictionaries of the directed dependency graph. If voltage node i is not the start point and its neighboring voltage node j is the end point, then update the voltage of the neighboring voltage node j to the voltage of the corresponding path start point. That is, if the start point is high voltage, then set the neighboring voltage node j to high voltage; if the start point is low voltage, then set the neighboring voltage node j to low voltage. Otherwise, update the voltage of the neighboring voltage node j to the voltage of voltage node i.

[0045] S310: Determine if the neighbor node set N(i) is empty. If it is, proceed to step S311; otherwise, return to step S303.

[0046] S311: Determine whether voltage node queue B is empty. If it is, the identification sensitization ends and proceeds to step S312; otherwise, return to step S302.

[0047] S312: Output the recognition sensitization result:

[0048] Output the voltage state of each voltage node or the gate state of the corresponding MOS transistor to obtain the identification and sensitization results.

[0049] As described above, in this embodiment, each digital power signal is propagated along the signal flow direction according to the breadth-first strategy under each power value mode. When the signal flow actively propagates, it encounters analog devices, the source or drain of MOS transistors, and stops propagating on that path. That is, only circuit devices with digital characteristics are sensitized, and finally the voltage level of each voltage node on the digital path and the gate control on / off status of each MOS transistor are obtained.

[0050] according to Figure 2Analysis of commonly used directed dependency graph models for electronic components, as shown in the diagram, reveals that within a maximally strongly connected component (SCC), SCC splitting can be achieved by disconnecting either the unidirectional edge represented by the gate of a MOS transistor or the bidirectional edge of the device. However, the on / off state of the bidirectional edge is difficult to precisely control using excitation. To achieve excitation-controlled circuit splitting, the unidirectional edge corresponding to the gate edge of the MOS transistor in the controlled-resistance MOS set under a certain power supply mode in the directed graph can be disconnected to achieve circuit splitting under that power supply mode. Research has found that not all controlled-resistance MOS transistors in the controlled-resistance MOS set contribute to SCC splitting. By disconnecting the unidirectional edges within the SCC and identifying the SCC contraction points, it is possible to analyze which disconnected unidirectional edges are useful for SCC splitting. If the gates of the MOS transistors represented by these unidirectional edges appear in the controlled-resistance MOS set under a certain power supply mode, these MOS transistors are called contributing controlled-resistance MOS transistors under that power supply mode.

[0051] In a directed graph, disconnecting only the gate side of a contributing controlled-resistance MOS (SCR) and disconnecting the gate side of the entire SCR set achieve the same segmentation effect. The purpose of this is twofold: first, it helps to further understand the contribution of SCRs to SCC splitting (e.g., which SCRs implemented which SCC splitting); second, in the defect segmentation parallel simulation stage, as long as the injected defects do not cause the contributing SCRs to remain off, the circuit segmentation result will not be affected, thus not affecting the defect parallel simulation. Therefore, identifying the contributing SCRs helps to perform simulation analysis and testability analysis on more defects during simulation. Therefore, in this embodiment, the controlled-resistance MOS set Block_MOS can also be segmented. m Further optimization involves identifying and retaining contributing controlled-resistance MOS transistors, while deleting the remaining controlled-resistance MOS transistors. Figure 4 This is a flowchart illustrating the identification of the controlled-resistance MOS set in this embodiment. For example... Figure 4 As shown, the specific steps for identifying the contributing controlled-resistance MOS set in this embodiment include:

[0052] S401: Preliminary identification of circuit blocks:

[0053] Using a pre-defined strongly connected component algorithm, maximal strongly connected components of the directed dependency graph G are initially identified as circuit blocks SCC. d , where d = 1, 2, ..., D, and D represents the number of circuit blocks initially identified.

[0054] Strongly connected components are sets of nodes in a graph where any two nodes can reach each other. This embodiment uses Tarjan's algorithm, a classic algorithm for finding strongly connected components in graphs, widely used in graph theory and network analysis.

[0055] S402: Identify potential contributing MOSFETs:

[0056] In the directed dependency graph G, disconnect all circuit blocks SCC. d The internal unidirectional edges are used to obtain a directed dependency graph G′. The same strongly connected component algorithm is then used to identify maximal strongly connected components as circuit blocks. At this point, some circuit blocks may be split into more than two sub-circuit blocks. Therefore, for the original circuit block SCC... d Determine whether the circuit is split into more than two sub-circuit blocks in the re-identification result. If not, do nothing; if so, record the sub-circuit block as SCC. d,r r = 1, 2, ..., R d R d Indicates circuit block SCC d The number of sub-circuit blocks obtained after re-identification is then SCCed for each sub-circuit block. d,r As a circuit block shrinking point, the circuit block SCC is searched in the directed dependency graph G. d For any two contracted points in the circuit, determine if a MOS transistor gate exists on the unidirectional edge. If it does, designate the corresponding MOS transistor as a candidate contributing MOS transistor; otherwise, do nothing. Construct a candidate contributing MOS set Key_MOS from the candidate contributing MOS transistors of the entire circuit. m .

[0057] S403: Determine the contributing MOSFET:

[0058] Traverse the set of contributing candidate MOS Key_MOS m Each MOSFET in the set belongs to the controlled and resisted MOSFET set Block_MOS. m If it does, it is treated as a contributing controlled-resistance MOS; otherwise, no operation is performed.

[0059] Figure 5 This is an example diagram illustrating the identification of the controlled-resistance MOS set in this embodiment. For example... Figure 5As shown, taking the Widlar bias generator as an example, the Tarjan algorithm can identify three maximal strongly connected components, resulting in three circuit blocks. The process of identifying the contributing controlled-resistance MOS set is illustrated using circuit block SCC2. First, the unidirectional edges inside SCC2 are disconnected, breaking V3->I4 and V2->I7. Then, the Tarjan algorithm is used again to identify two maximal strongly connected components, S1 and S2, resulting in two circuit block shrinkage points, which are the targets for splitting SCC2. The pointers of shrinkage points S1 and S2 can be recovered based on V3->I4 and V2->I7. Because once the pointers between shrinkage points are recovered, these shrinkage points become a large SCC, the pointers between shrinkage points must be on the loop between them. Therefore, disconnecting any pointer between shrinkage points will break a loop. Since the pointer relationship between shrinkage points S1 and S2 is S1->S2 and S2->S1, it is only necessary to disconnect S1->S2 or S2->S1 to split the SCC. The path from S1 to S2 includes V3 to I4, and the path from S2 to S1 includes V2 to I7. Therefore, the MOS gates represented by V3 to I4 constitute a group of contributing MOS gates, and the MOS gates represented by V2 to I7 constitute a group of contributing MOS gates. It is worth noting that the direction between the contractions may not only include one MOS gate edge. In some circuits, the path from S1 to S2 may contain n MOS gate edges. In this case, these n MOS gate edges constitute a group of contributing MOS gates, and S1 to S2 can only be disconnected when all of these contributing MOS gate edges are simultaneously disconnected.

[0060] S103: Determine the circuit segmentation result:

[0061] For the m-th power supply mode, disconnect the controlled and restricted MOS set Block_MOS in the directed dependency graph. m The directed dependency graph g is obtained by taking the unidirectional edges represented by all MOS gate edges. m Then, a pre-defined strongly connected component algorithm is used to identify the directed dependency graph g. m The maximally strongly connected component as a circuit block SCC m,n where n = 1, 2, ..., N m N m Represents a directed dependency graph g m The number of identified circuit blocks is used to obtain the circuit segmentation results under each power supply value mode.

[0062] Because the direct disconnection of the gate side of the MOS transistor in the controlled and resisted MOS array before identifying strongly connected components in this invention may result in excessively small granularity of circuit blocks, where each sub-circuit block is a component circuit contained in a single SCC. Such sub-circuit blocks may have too few components, leading to uneven block distribution or an excessive number of blocks, thus increasing the complexity of the simulation operation. To address this issue, this embodiment proposes a circuit block merging method. Using the number of components Q of the circuit block with the most components as the upper bound, multiple circuit blocks are merged consecutively into one block according to topological order. This ensures the correctness of the defect propagation simulation sequence while prioritizing the minimization of parallel defect simulation time and making the number of blocks as uniform as possible, thereby achieving better block simulation results. Figure 6 This is a flowchart of the circuit block merging process in this embodiment. For example... Figure 6 As shown, the specific steps for merging circuit blocks in this embodiment include:

[0063] S601: Circuit block topology sorting:

[0064] N for the m-th power supply value mode m SCC circuit block m,n Perform topological sorting to obtain a List of circuit block topology sequences. m . Figure 7 This is a flowchart illustrating the circuit block arrangement in this embodiment. For example... Figure 7 As shown, the specific steps for circuit block topology sorting in this embodiment include:

[0065] S701: Initialize the circuit block topology sequence List m Empty.

[0066] S702: Calculate the in-degree of each circuit block:

[0067] Calculate N m SCC circuit block m,n in degree IN m,n .

[0068] S703: Obtain the zero-in-degree circuit block sequence:

[0069] All current in-degrees IN m,n =0 circuit block SCC m,n Constructing the zero-in-degree circuit block sequence Z m .

[0070] S704: Zero-in-degree circuit block sorting:

[0071] The current zero-in-degree circuit block sequence Z m All circuit blocks are sorted in descending order of their outgoing degree.

[0072] S705: Adding a circuit block:

[0073] From the zero-in-degree circuit block sequence Z m Take the first circuit block from the middle Add to circuit block topology sequence List m The end of.

[0074] S706: Update the in-degree of neighboring circuit blocks:

[0075] circuit block Decrement the in-degree of each neighboring circuit block by 1, and then add the neighboring circuit blocks with an in-degree of 0 after the update to the zero-in-degree circuit block sequence Z. m .

[0076] S707: Determine the zero-in-degree circuit block sequence Z m Is it empty? If yes, the topological sorting ends; otherwise, return to step S704.

[0077] Only after topological sorting can adjacent circuit blocks be combined into one, thus ensuring the correct weak connectivity between the merged circuit blocks.

[0078] S602: Circuit block for locating the maximum number of components:

[0079] Traversing the circuit block topology sequence List m Each circuit block Where n v List representing the circuit block topology sequence m Given the original index of the v-th circuit block, v = 1, 2, ..., N, locate the circuit block with the most components. Let H be the number of its components.

[0080] S603: Merging circuit block:

[0081] Separate circuit blocks The search proceeds forward or backward using the two circuit blocks before and after the starting point. If the cumulative number of devices between the circuit blocks before or after the starting point and the starting circuit block does not exceed H, then the circuit blocks before or after the starting point are merged with the starting circuit block, and the merged circuit block is used as the new starting circuit block. If the cumulative number of devices between the circuit blocks before or after the starting point and the starting circuit block exceeds H, then the circuit blocks before or after the starting point are used as the new starting circuit block, until all circuit blocks have been searched.

[0082] Figure 8 This is an example diagram of circuit block merging in this embodiment. For example... Figure 8As shown, each circle node represents a circuit block, and the number in the circle represents the number of components in the circuit block. If the circuit is directly simulated in blocks, the number of components in the largest sub-module is 100, while the number of components in the smallest sub-module is only 10, resulting in uneven block distribution or too many blocks. Therefore, these circuit blocks can be sorted according to the topological order, and the circuit blocks with consecutive topological order can be merged. The number of components in the merged circuit block is capped at 100. The result after merging is shown in the dashed box. This way, so many circuit blocks can be merged into 3 weakly connected circuit blocks, each with 100 components, which is beneficial for subsequent parallel simulation of defects.

[0083] To better illustrate the technical effects of the present invention, specific examples are used to experimentally verify the invention. This embodiment uses the bandgap reference circuit in a benchmark circuit as an example. Figure 9 This is the bandgap circuit diagram in this embodiment. Figure 9 As shown, the bandgap circuit can be used with a maximum voltage of 2.5V and a minimum voltage of 0V. Using the method of this invention, the bandgap circuit is divided into circuit blocks, namely each maximal connected component (SCC) and its weak connectivity relationships. The divided circuit blocks are all acyclic and weakly connected, enabling parallel simulation of defects.

[0084] The digital power supply for the bandgap circuit is V3, so it has two power supply modes: V3 high voltage or V3 low voltage, denoted as V3_high and V3_low respectively. Circuit segmentation is performed using all identified controlled-resistance MOS sets under each power supply mode. Table 1 shows the results of circuit segmentation using all controlled-resistance MOS sets in this embodiment.

[0085]

[0086] Table 1

[0087] Then, circuit segmentation is performed only on the controlled-resistance MOS set that contributes to the splitting of SCC, as identified by the contributing controlled-resistance MOS identification algorithm. Table 2 is a list of the circuit segmentation results using the contributing controlled-resistance MOS set in this embodiment.

[0088]

[0089] Table 2

[0090] Comparing Tables 1 and 2, it can be seen that compared to directly identifying each circuit block, whether using all controlled-resistance MOS devices under each power supply mode as described in this invention for circuit segmentation or using only the identified controlled-resistance MOS devices that contribute to the splitting of SCC, more SCCs can be segmented, thereby reducing the number of devices with the largest SCC and reducing the time required for parallel defect simulation. Furthermore, the final circuit segmentation results in Tables 1 and 2 are consistent, proving that the controlled-resistance MOS devices that contribute to the splitting of SCC identified in this invention are highly accurate. Using only the controlled-resistance MOS devices that contribute to the splitting of SCC in the pattern, compared to using all controlled-resistance MOS devices in the pattern for circuit segmentation, has the greatest advantage in facilitating subsequent parallel defect simulation by minimizing the occurrence of situations where injecting a defect causes the controlled-resistance MOS devices to conduct, thus disrupting the segmentation results (this situation is inherently sporadic, but using fewer controlled-resistance MOS devices during segmentation further reduces its occurrence).

[0091] Comparing the circuit blocks before and after merging, it can be seen that the number of components contained in the circuit blocks after merging is more uniform, which is beneficial for subsequent parallel simulation of circuit defects.

[0092] After the mixed-signal circuit is partitioned using this invention, a netlist of defective parallel simulation circuit blocks and their I / O ports will be obtained under each power supply value mode. Before performing defective parallel simulation, it is necessary to perform overall simulation of the defect-free circuit to know the voltage values ​​of the I / O ports of each circuit block, and use the I / O port voltage values ​​of each circuit block as the power supply for each circuit block during parallel simulation. Figure 10 This is the circuit block signal flow diagram in the power supply value mode of this embodiment. Figure 10 It shows the number of components in each segmented circuit block, as well as the connectivity between the circuit blocks. For example... Figure 10 As shown, by using this invention to partition mixed-signal circuits, circuit partitioning results under various power supply value modes can be obtained without changing the physical circuit design. The partitioned circuit blocks exhibit a loop-free weak connectivity relationship, enabling parallel simulation of defects and greatly accelerating the testability analysis speed of large-scale mixed-signal integrated circuits.

[0093] Although the illustrative specific embodiments of the present invention have been described above to enable those skilled in the art to understand the invention, it should be understood that the invention is not limited to the scope of the specific embodiments. For those skilled in the art, various changes are obvious as long as they are within the spirit and scope of the invention as defined and determined by the appended claims, and all inventions utilizing the concept of the present invention are protected.

Claims

1. A method for partitioning mixed-signal circuits based on excitation control, characterized in that, Includes the following steps: S1: Based on the SPICE netlist of the mixed-signal circuit, perform directed dependency graph modeling on the mixed-signal circuit to obtain the directed dependency graph. ; S2: Divide all power supplies in the mixed-signal circuit into digital power supplies and analog power supplies, and denote the number of digital power supplies as... Then, set the voltage of the digital power supply to high or low, and the voltage of the analog power supply to the default value in the SPICE netlist, to obtain... There are several power value selection modes, among which Digital path identification sensitization is performed for each power supply mode. The MOSFETs that are turned off due to digital power supply control in that power supply mode are identified as controlled-resistance MOSFETs, thus obtaining the set of controlled-resistance MOSFETs for each power supply mode. , Then from the controlled-resistance MOS assembly Identify and retain contributing controlled-resistance MOS transistors, and delete the remaining controlled-resistance MOS transistors. The specific method for identifying contributing controlled-resistance MOS transistors is as follows: 1) The pre-defined strongly connected component algorithm is used to initially identify the directed dependency graph. maximally strongly connected components as circuit blocks ,in , This indicates the number of circuit blocks initially identified; 2) In directed dependency graphs In the middle, disconnect all circuit blocks. The internal unidirectional edges are used to obtain a directed dependency graph. The same strongly connected component algorithm is used again to identify maximally strongly connected components as circuit blocks; for the original circuit blocks The system determines whether the circuit has been split into more than two sub-circuit blocks in the re-identification result. If not, no action is taken; if so, the sub-circuit block is recorded as... , , Represents circuit block The number of sub-circuit blocks obtained after re-identification is then used to determine the number of each sub-circuit block. As a circuit block contraction point, in the directed dependency graph Search circuit block For any two contracted points in the circuit, determine if a MOS transistor gate exists on the unidirectional edge. If it does, select the corresponding MOS transistor as a candidate contributing MOS transistor; otherwise, do nothing. Then, construct a candidate contributing MOS transistor set from all the candidate contributing MOS transistors in the entire circuit. ; 3) Traverse the set of candidate contributing MOS Each MOSFET in the set belongs to the controlled and resisted MOSFET set. If it does, it is treated as a contributing controlled-resistance MOS; otherwise, no operation is performed. S3: For the first Each power supply value mode disconnects the controlled and hindered MOS set in the directed dependency graph. The directed dependency graph is obtained by taking the unidirectional edges represented by all MOS gate edges. Then, a pre-defined strongly connected component algorithm is used to identify the directed dependency graph. maximally strongly connected components as circuit blocks ,in , Represents a directed dependency graph The number of identified circuit blocks is used to obtain the circuit segmentation results under each power supply value mode.

2. The mixed-signal circuit segmentation method according to claim 1, characterized in that, The digital path identification sensitization method in step S2 includes the following steps: 1) Initialize the access set Voltage node queue Path queue Then A digital power supply was added to the access set. and voltage node queue Then add Path to path queue , No. The starting voltage node of the path is the first A digital power supply, ; 2) From the voltage node queue Extracting voltage nodes and remove it from the voltage node queue Delete it, and then obtain the voltage node based on the directed dependency graph. Neighbor voltage node set ; 3) From the set of neighboring voltage nodes Extracting neighboring voltage nodes and from the set of neighboring voltage nodes Delete; 4) Determine if it is a neighboring voltage node That is, neighboring voltage nodes Has this been accessed? If yes, proceed to step 10; otherwise, proceed to step 5. 5) Determine neighboring voltage nodes If it corresponds to a MOS gate, proceed to step 6; otherwise, proceed to step 8. 6) If voltage node High level and neighboring voltage node Corresponding to NMOS gate, or voltage node Low level and neighboring voltage node If the PMOS gate is in the specified state, the MOS gate state is determined to be on; otherwise, the MOS gate state is determined to be off. 7) Determine if the MOS gate state is on. If yes, proceed to step 8); otherwise, proceed to step 10. 8) Connect neighboring voltage nodes Add to access set and voltage node queue , neighboring voltage nodes Add to path queue Medium voltage node Following the path; 9) Traverse the start and end dictionary of the directed dependency graph. If the voltage node... Not the starting point and neighboring voltage nodes If the endpoint is [the voltage node], then the neighboring voltage node [will be used]. The voltage is updated to the voltage of the corresponding path start point; that is, if the start point is a high voltage, then the voltage of the neighboring nodes is updated. If the starting point is low voltage, then set the voltage of the neighboring node to high voltage. If it's low voltage; otherwise, set the neighboring voltage node. The voltage is updated to the voltage node. The voltage; 10) Determine the set of neighboring nodes If the value is empty, proceed to step 11; otherwise, return to step 3. 11): Determine the voltage node queue If the value is empty, the sensitization process ends and proceeds to step 12; otherwise, return to step 2. 12) Output the voltage state of each voltage node or the gate state of the MOS transistor corresponding to the voltage node to obtain the identification sensitization result.

3. The mixed-signal circuit segmentation method according to claim 1, characterized in that, In step S3, each directed dependency graph is also processed. maximal strongly connected components The specific method for merging is as follows: 1) Regarding the first Individual power value selection modes One circuit block Perform topological sorting to obtain the circuit block topology sequence. The specific method for topological sorting is as follows: a) Initialize the circuit block topology sequence Empty; b) Calculation One circuit block in-degree ; c) Add all current in-degrees circuit block Constructing a sequence of zero-in-degree circuit blocks ; d) The current zero-in-degree circuit block sequence All circuit blocks are sorted in descending order of their outgoing degree; e) From the zero-degree circuit block sequence Take the first circuit block from the middle Add to circuit block topology sequence The end; f) The circuit block Decrement the in-degree of each neighboring circuit block by 1, and then add the neighboring circuit blocks with an in-degree of 0 after the update to the zero-in-degree circuit block sequence. ; g) Determine the zero-in-degree circuit block sequence If the value is empty, the topological sorting ends; otherwise, return to step d). 2) Traverse the circuit block topology sequence Each circuit block ,in Represents the circuit block topology sequence The Middle The original serial number of each circuit block, Locate the circuit block with the most components. Let the number of its devices be . ; 3) Separate the circuit blocks The search proceeds forward or backward, starting from the two circuit blocks before or after the starting point. If the cumulative number of devices between the starting and previous circuit blocks does not exceed [a certain threshold], the search continues. If the number of components in the circuit blocks before or after the starting point exceeds the limit, then merge it with the starting circuit block, and use the merged circuit block as the new starting circuit block. If the previous or subsequent circuit block is used as the new starting circuit block, the search continues until all circuit blocks have been searched.

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