Display module aging circuit, display module aging method and display panel

Abstract

The invention discloses a display module aging circuit, a display module aging method and a display panel, and belongs to the technical field of display. The display module aging circuit comprises a gating module and an amplifying module, the first input end of the gating module is used for inputting a control signal, and the second input end of the gating module is connected with the data signal generation circuit or the scanning signal generation circuit; the input end of the amplification module is connected with the data signal generation circuit or the scanning signal generation circuit; the output end of the amplification module is connected with the third input end of the gating module, and the amplification module is used for outputting the amplified data signal or scanning signal; and the output end of the gating module is connected with the display module. Therefore, by amplifying the voltage of the data signal or the scanning signal, the aging efficiency of the transistor in the display module is improved, the characteristic of the transistor can reach a stable value more quickly, the display stability is improved, and the aging treatment can be flexibly controlled through the gating module.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display module aging circuit, a display module aging method and a display panel. Background Art

[0002] For transistors in pixel circuits, leakage current may occur due to process problems. At the same time, light-emitting components such as organic light-emitting diodes (OLEDs) have large differences in the early rapid decay period. These conditions will affect the display uniformity. Therefore, these components need to be aged so that their characteristics can reach stable values ​​more quickly. The commonly used aging method is to play different pictures in turn, so that the above components are constantly turned on and off to age them, but this method is less efficient. Summary of the invention

[0003] The embodiments of the present application provide a display module aging circuit, a display module aging method and a display panel to solve the technical problem of low efficiency of device aging processing.

[0004] According to one aspect of an embodiment of the present application, a display module aging circuit is provided, comprising: a gating module and an amplifying module; the first input end of the gating module is used to input a control signal, the second input end of the gating module is connected to a data signal generating circuit or a scan signal generating circuit, and is used to input a data signal or a scan signal; the input end of the amplifying module is connected to the data signal generating circuit or the scan signal generating circuit, and is used to input a data signal or a scan signal; the output end of the amplifying module is connected to the third input end of the gating module, and is used to output an amplified data signal or a scan signal; the output end of the gating module is connected to the display module, and is used to output an amplified data signal or a scan signal, or, output the data signal or the scan signal.

[0005] In one possible embodiment, the gating module includes: a first transistor and a second transistor; the gate of the first transistor is connected in parallel with the gate of the second transistor for inputting a control signal, and the first transistor and the second transistor are in opposite switching states based on the same control signal; the input electrode of the first transistor serves as the second input terminal of the gating module, and is connected to a data signal generating circuit or a scanning signal generating circuit; the input electrode of the second transistor serves as the third input terminal of the gating module, and is connected to the output terminal of the amplification module; the output electrode of the first transistor and the output electrode of the second transistor serve as the output terminal of the gating module and are connected to the display module.

[0006] In a possible implementation, the amplification module includes: an amplifier, a first resistor and a second resistor; the positive input terminal of the amplifier serves as the input terminal of the amplification module and is connected to a data signal generating circuit or a scanning signal generating circuit; the negative input terminal of the amplifier is grounded through the first resistor and is connected to the output terminal of the amplifier through the second resistor; the output terminal of the amplifier serves as the output terminal of the amplification module and is connected to the third input terminal of the selection module.

[0007] In a possible implementation manner, the amplification module further includes: a third resistor; the third resistor is connected between the positive input terminal and the data signal generating circuit or the scanning signal generating circuit.

[0008] In one possible implementation, when the second input terminal of the gating module and the input terminal of the amplifying module are connected to the data signal generating circuit, the output terminal of the gating module is connected to the source of at least one transistor in the display module; when the second input terminal of the gating module and the input terminal of the amplifying module are connected to the scanning signal generating circuit, the output terminal of the gating module is connected to the gate of at least one transistor in the display module.

[0009] According to another aspect of the present application, a display module aging method is provided, which is applied to the display module aging circuit described in any one of the first aspects above, and the method includes: determining whether it is necessary to perform aging treatment on the display module; in response to the need to perform aging treatment on the display module, adjusting the control signal to output the amplified data signal or scan signal through the selection module.

[0010] In one possible embodiment, the gating module includes: a first transistor and a second transistor; the adjusting of the control signal to output the amplified data signal or scan signal through the gating module includes: adjusting the control signal to a high level to control the first transistor to be in an off state and the second transistor to be in an on state; amplifying the data signal or scan signal based on the amplification module; and outputting the amplified data signal or scan signal to the display module through the second transistor.

[0011] In a possible implementation, the amplification module includes: an amplifier, a first resistor and a second resistor, wherein the second resistor is a variable resistor; amplifying the data signal or the scan signal based on the amplification module includes: adjusting the resistance value of the second resistor based on a required amplification factor; and amplifying the data signal or the scan signal based on the adjusted first resistor, the second resistor and the amplifier.

[0012] In a possible implementation, the method further includes: in response to the display module not needing to be aged, adjusting the control signal to output the data signal or the scan signal through the gating module.

[0013] According to another aspect of an embodiment of the present application, a display panel is also provided, comprising a display module, a data signal generating circuit, a scanning signal generating circuit, and a plurality of display module aging circuits as described in any one of the aforementioned first aspects; wherein the data signal generating circuit and the scanning signal generating circuit are respectively connected to different display module aging circuits.

[0014] The embodiment of the present application proposes a display module aging circuit, a display module aging method and a display panel, and the display module aging circuit includes: a gating module and an amplifying module; the first input end of the gating module is used to input a control signal, and the second input end of the gating module is connected to a data signal generating circuit or a scanning signal generating circuit for inputting a data signal or a scanning signal; the input end of the amplifying module is connected to a data signal generating circuit or a scanning signal generating circuit for inputting a data signal or a scanning signal; the output end of the amplifying module is connected to a third input end of the gating module for outputting an amplified data signal or a scanning signal; the output end of the gating module is connected to a display module for outputting an amplified data signal or a scanning signal, or outputting the data signal or a scanning signal. In this way, by amplifying the data signal or the scanning signal, the aging speed of the device in the display module can be accelerated, and there is no need to set a complex screen carousel, thereby improving the efficiency of the device aging process. In addition, the gating module can further improve the flexibility of signal amplification, and the signal output can be flexibly adjusted according to the aging requirements. Moreover, by amplifying and outputting the data signal and the scanning signal, it is also easier to find possible defects in the data line and the scanning line, thereby improving the yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0016] Figure 1 is a structural schematic diagram of a display module aging circuit provided in an embodiment of the present application;

[0017] Figure 2 is a structural schematic diagram of a display module aging circuit provided in an embodiment of the present application;

[0018] Figure 3 is a structural schematic diagram of a display module aging circuit provided in an embodiment of the present application;

[0019] Figure 4is a structural schematic diagram of a display module aging circuit provided in an embodiment of the present application;

[0020] Figure 5 It is a flow chart of a display module aging method provided in an embodiment of the present application;

[0021] Figure 6 It is a flow chart of a display module aging method provided in an embodiment of the present application;

[0022] Figure 7 is a structural schematic diagram of a display panel provided in an embodiment of the present application;

[0023] Figure 8 is a structural schematic diagram of a display panel provided in an embodiment of the present application;

[0024] Fig. 9 is a structural schematic diagram of a display module aging circuit provided in an embodiment of the present application;

[0025] Fig.10 It is a signal timing diagram provided by an embodiment of the present application;

[0026] Fig.11 It is a flow chart of a display module aging method provided in an embodiment of the present application.

[0027] Description of Reference Numerals

[0028] 1. Selection module; 2. Amplification module; 3. Data signal generating circuit; 4. Scan signal generating circuit; 5. Display module; 6. Display module aging circuit; 11. First transistor; 12. Second transistor; 21. Amplifier; 22. First resistor; 23. Second resistor; 24. Third resistor. DETAILED DESCRIPTION

[0029] In order to enable those skilled in the art to better understand the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only embodiments of a part of the present application, not all embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work should fall within the scope of protection of the present application. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0030] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0031] This embodiment provides a display module aging circuit. Figure 1 Schematic diagram of a display module aging circuit provided in an embodiment of the present application. Figure 1 As shown, the display module aging circuit may include: a gating module 1 and an amplifying module 2;

[0032] The first input end of the gating module 1 is used to input a control signal, and the second input end of the gating module 1 is connected to a data signal generating circuit or a scanning signal generating circuit, and is used to input a data signal or a scanning signal;

[0033] The input end of the amplifying module 2 is connected to the data signal generating circuit or the scanning signal generating circuit for inputting the data signal or the scanning signal; the output end of the amplifying module 2 is connected to the third input end of the gating module 1 for outputting the amplified data signal or the scanning signal;

[0034] The output end of the gating module 1 is connected to the display module 5, and is used to output the amplified data signal or scanning signal, or output the data signal or scanning signal.

[0035] In this embodiment, the display module aging circuit can be used to perform aging processing on the target transistor in the display module, for example, to perform aging processing on the target transistor in the pixel circuit of the display module 5. The target transistor can be a thin film transistor (TFT) or the like.

[0036] In one embodiment, the display module aging circuit can be connected between the data signal generating circuit 3 and the display module 5, for example, connected between the data signal generating circuit 3 and the source of the transistor in the display module 5. At this time, the second input end of the selection module 1 and the input end of the amplification module 2 are connected to the data signal generating circuit 3 for inputting the data signal, and the amplification module 2 is used to amplify the data signal.

[0037] In one embodiment, when the display module aging circuit is connected between the data signal generating circuit 3 and the display module, the display module aging circuit can be arranged on the source driving circuit. The source driving circuit can include multiple display module aging circuits, for example, one display module aging circuit can be connected to the source of a column of target transistors in the display module.

[0038] In one embodiment, the display module aging circuit can be connected between the scanning signal generating circuit 4 and the display module, for example, connected between the scanning signal generating circuit 4 and the gate of the transistor in the display module. At this time, the second input end of the selection module 1 and the input end of the amplification module 2 are connected to the scanning signal generating circuit 4 for inputting the scanning signal, and the amplification module 2 is used to amplify the scanning signal.

[0039] In one embodiment, when the display module aging circuit is connected between the scan signal generating circuit 4 and the display module, the display module aging circuit can be arranged on the gate driving circuit. The gate driving circuit can include multiple display module aging circuits, for example, one display module aging circuit can be connected to the gates of a row of target transistors in the display module.

[0040] In one embodiment, the gating module 1 may include a switch circuit, such as a switch circuit composed of transistors. The switch circuit may be switched by adjusting a control signal to switch the second input terminal or the third input terminal for input.

[0041] In one embodiment, the control signal can realize the path selection of the gating module 1 by switching high level or low level. For example, when aging treatment is required, the control signal can be adjusted to a high level; when aging treatment is not required, the control signal can be adjusted to a low level.

[0042] In one embodiment, the gating module 1 may include two paths, and the conduction states of the two paths are different under the same control signal. For example, when the control signal is at a low level, the first path is turned on and the second path is turned off; when the control signal is at a high level, the first path is turned off and the second path is turned on.

[0043] In one embodiment, the input end of the first path can be used as the second input end of the gating module 1, connected to the data signal generating circuit 3 or the scanning signal generating circuit 4, and used to input the data signal or the scanning signal; the input end of the second path can be used as the third input end of the gating module 1, connected to the output end of the amplifying module 2, and used to input the amplified data signal or the scanning signal. The output end of the first path and the output end of the second path can be used as the output end of the gating module 1 and connected to the display module.

[0044] In one embodiment, when the control signal is at a low level, the first path is turned on and the second path is turned off. At this time, the target transistor of the display module is not aged and no signal amplification is required, and the data signal or the scan signal is directly output to the display module through the first path. When the control signal is at a high level, the first path is turned off and the second path is turned on. At this time, the target transistor of the display module is aged, and the data signal or the scan signal enters the amplification module 2 for amplification, and the amplified data signal or the scan signal is output to the display module through the second path.

[0045] In one embodiment, the gating module 1 may include two transistors, and the transistors may be metal-oxide-semiconductor field-effect transistors (MOS). For example, the first path includes a first transistor 11, and the second path includes a second transistor 12. Exemplarily, the first transistor 11 may be a P-type MOS tube (PMOS), and the second transistor 12 may be an N-type MOS tube (NMOS).

[0046] In one embodiment, the amplification module 2 may include an amplifier 21, such as an operational (OP) amplifier 21, etc. The amplifier 21 may be used to amplify a data signal or a scan signal.

[0047] In this way, by amplifying the data signal or the scanning signal, the aging speed of the device in the display module can be accelerated, and there is no need to set up a complex screen carousel, thereby improving the efficiency of the device aging process. The flexibility of signal amplification can be further improved by the selection module 1, and the signal output can be flexibly adjusted according to the aging requirements by adjusting the control signal. In addition, by amplifying the output of the data signal and the scanning signal, it is also easier to find possible defects in the data line and the scanning line, thereby improving the product yield.

[0048] This embodiment provides a display module aging circuit. Figure 2 Schematic diagram of a display module aging circuit provided in an embodiment of the present application. Figure 2 As shown, the gating module 1 in the display module aging circuit may include: a first transistor 11 and a second transistor 12;

[0049] The gate of the first transistor 11 is connected in parallel with the gate of the second transistor 12 for inputting a control signal, and the first transistor 11 and the second transistor 12 are in opposite switching states based on the same control signal;

[0050] The input electrode of the first transistor 11 is used as the second input terminal of the gating module 1, and is connected to the data signal generating circuit 3 or the scanning signal generating circuit 4; the input electrode of the second transistor 12 is used as the third input terminal of the gating module 1, and is connected to the output terminal of the amplifying module 2;

[0051] The output electrode of the first transistor 11 and the output electrode of the second transistor 12 are connected to the display module as the output end of the gating module 1 .

[0052] In this embodiment, the first transistor 11 and the second transistor 12 are in opposite switching states based on the same control signal, which may mean that the first transistor 11 and the second transistor 12 are in opposite switching states when the control signal is at a high level, and / or the first transistor 11 and the second transistor 12 are in opposite switching states when the control signal is at a low level. Here, the switching state includes an on state and an off state.

[0053] In one embodiment, the first transistor 11 may be a PMOS transistor, and the second transistor 12 may be an NMOS transistor. When the control signal applied to the gate is at a high level, the PMOS transistor is turned on and the NMOS transistor is turned off; when the control signal is at a low level, the NMOS transistor is turned on and the PMOS transistor is turned off.

[0054] In one embodiment, when the first transistor 11 is a PMOS transistor, the input electrode of the first transistor 11 is a source electrode, and the output electrode is a drain electrode; when the second transistor 12 is an NMOS transistor, the input electrode of the second transistor 12 is a drain electrode, and the output electrode is a source electrode.

[0055] In one embodiment, the first transistor 11 and the second transistor 12 may also be the same transistor, and a conversion device, such as a logic "NOT" gate, may be set at the gate of the first transistor 11 or the second transistor 12, so as to convert the control signal state of the transistor and realize that the first transistor 11 and the second transistor 12 are in opposite switching states.

[0056] In one embodiment, the first transistor 11 can be in the first path, and the second transistor 12 can be in the second path. When the target transistor of the display module is not aged, the control signal is at a low level, the first transistor 11 is turned on, and the second transistor 12 is turned off. At this time, no signal amplification is required, and the data signal or the scan signal is directly output to the display module through the first transistor 11. When the target transistor of the display module needs to be aged, the control signal is at a high level, the first transistor 11 is turned off, the second transistor 12 is turned on, the data signal or the scan signal enters the amplification module 2 for amplification, and the amplified data signal or the scan signal is output to the display module through the second transistor 12.

[0057] In one embodiment, the output electrode of the first transistor 11 and the output electrode of the second transistor 12 can be connected in parallel to the display module through a line. For example, when the input electrode of the first transistor 11 and the input end of the amplification module 2 are connected to the data signal generation circuit 3, the output electrode of the first transistor 11 and the output electrode of the second transistor 12 can be connected in parallel to the source electrode of the target transistor through a line, for example, connected to the source electrode of a column of target transistors through a line.

[0058] In one embodiment, when the input electrode of the first transistor 11 and the input end of the amplification module 2 are connected to the scanning signal generating circuit 4, the output electrode of the first transistor 11 and the output electrode of the second transistor 12 can be connected in parallel to the gate of the target transistor through a line, for example, connected to the gate of a row of target transistors through a line.

[0059] In this way, there is no need to input multiple different control signals separately. Under the same control signal, only one path where the transistor in the selection module 1 is located will be turned on. Therefore, based on the switching of the control signal level, the path switching can be realized, thereby realizing flexible control of whether to amplify the data signal / scan signal, thereby improving the availability of the circuit, and there is no need to adjust the circuit after the aging process is completed.

[0060] This embodiment provides a display module aging circuit. Figure 3 Schematic diagram of a display module aging circuit provided in an embodiment of the present application. Figure 3 As shown, in the aforementioned display module aging circuit, the amplification module 2 includes: an amplifier 21, a first resistor 22 and a second resistor 23;

[0061] The positive input terminal of the amplifier 21 is used as the input terminal of the amplifying module 2 and is connected to the data signal generating circuit 3 or the scanning signal generating circuit 4; the negative input terminal of the amplifier 21 is grounded through the first resistor 22, and is connected to the output terminal of the amplifier 21 through the second resistor 23;

[0062] The output end of the amplifier 21 is connected to the third input end of the gating module 1 as the output end of the amplifying module 2 .

[0063] In this embodiment, the amplifier 21 may be an OP amplifier 21 . The amplifier 21 has two input terminals, a positive terminal and a negative terminal. The positive terminal is used to input a data signal or a scanning signal, and the negative terminal is connected to the ground and the output terminal.

[0064] In one embodiment, the output terminal of the amplifier 21 may be connected to the input terminal of the second transistor 12 , so as to output the amplified data signal or scan signal to the display module through the second transistor 12 .

[0065] In one embodiment, the output end of the amplifier 21 may also be connected to the third input end of the gating module 1 via a current limiting resistor, and the current limiting resistor may prevent the amplified signal current from being too large and causing damage to the transistor.

[0066] In one embodiment, the input data signal Vdata is passed through the first resistor 22R1, the second resistor 23R2 and the amplifier 21 to obtain an amplified data signal Vdata′=Vdata*(1+R2 / R1). The input scan signal Vscan is passed through the first resistor 22R1, the second resistor 23R2 and the amplifier 21 to obtain an amplified scan signal Vscan′=Vscan*(1+R2 / R1).

[0067] In one embodiment, the second resistor 23 can be a variable resistor, so that the amplification factor of the data signal or the scan signal of the amplifier module 2 can be adjusted by adjusting the resistance value of the second resistor 23, and the amplification factor can be flexibly adjusted based on the aging processing requirements of the target transistor.

[0068] In this way, the data signal / scan signal can be amplified through the amplifier 21 and the peripheral resistor network including the first resistor 22 and the second resistor 23, so that it can be output to the display module through the enabled path when aging is required, and the target transistor can be efficiently aged.

[0069] This embodiment provides a display module aging circuit. Figure 4 Schematic diagram of a display module aging circuit provided in an embodiment of the present application. Figure 4 As shown, in the above display module aging circuit, the amplification module 2 further includes: a third resistor 24; the third resistor 24 is connected between the positive input terminal and the data signal generating circuit or the scanning signal generating circuit.

[0070] In this embodiment, the third resistor 24 is a current-limiting resistor, which is used to buffer the data signal or the scanning signal to prevent the amplifier module 2 and the transistor from being damaged by excessive signal current.

[0071] In one embodiment, the third resistor 24 may also be a variable resistor, and the resistance of the third resistor 24 may be adjusted according to the structure of the data signal generating circuit 3 or the scanning signal generating circuit 4, thereby flexibly providing accurate current limiting buffering effect for different data signals or scanning signals.

[0072] In this way, by using the third resistor 24 as a current-limiting resistor, the damage to the circuit and the target transistor caused by excessive signal current can be reduced, and the working efficiency and life of the transistor and the display module can be further improved.

[0073] In some embodiments, when the second input terminal of the gating module 1 and the input terminal of the amplifying module 2 are connected to the data signal generating circuit 3, the output terminal of the gating module 1 is connected to the source of at least one transistor in the display module;

[0074] When the second input end of the gating module 1 and the input end of the amplifying module 2 are connected to the scanning signal generating circuit 4 , the output end of the gating module 1 is connected to the gate of at least one transistor in the display module.

[0075] In one embodiment, the output end of the gating module 1 is connected to the source of at least one transistor in the display module, and may be connected to the source of multiple transistors in the same column of the display module. The output end of the gating module 1 is connected to the gate of at least one transistor in the display module, and may be connected to the gate of multiple transistors in the same row of the display module.

[0076] In this way, the display module aging circuit can provide an amplified or unamplified data signal to a column of transistors, or provide an amplified or unamplified scanning signal to a row of transistors, so that batch aging processing can be performed or normal driving signals can be provided to achieve flexible aging control.

[0077] This embodiment provides a display module aging method. Figure 5 1 is a flow chart of a display module aging method provided in an embodiment of the present application, and the method can be applied to the display module aging circuit described in any of the above embodiments. Figure 5 As shown, the method may include:

[0078] S10: Determine whether the display module needs to be aged;

[0079] S20 : ​​In response to the need to perform aging processing on the display module, adjusting the control signal to output the amplified data signal or the scan signal through the gating module 1 .

[0080] In this embodiment, the aging process refers to a process of aging the target transistor in the display module so that its characteristics quickly reach a stable value. Step S10 may include: determining whether the display module needs to be aged based on the characteristic parameters of the target transistor in the display module.

[0081] Here, the characteristic parameter may be determined based on at least one of a characteristic curve of the target transistor, a current operating condition, an operating time, and the like.

[0082] In one embodiment, adjusting the control signal may include adjusting the control signal to a high level or a low level, or adjusting the voltage of the control signal based on the characteristic parameters of the transistors included in the gating module 1. For example, when the gating module 1 includes a first transistor 11 PMOS tube and a second transistor 12 NMOS tube, adjusting the control signal may include adjusting the control signal to a high level, and adjusting the high level voltage of the control signal based on the voltage value of the data signal or the scan signal and the on-voltage threshold of the second transistor 12, so as to control the first transistor 11 to be in an off state and the second transistor 12 to be in an on state.

[0083] Exemplarily, the data signal voltage is Vdata, the scan signal voltage is Vscan, and the NMOS tube conduction voltage threshold is Vth, then the high level voltage value of the control signal is ≥ Vdata+Vth, or the high level voltage value of the control signal is ≥ Vscan+Vth.

[0084] In one embodiment, outputting the amplified data signal or scan signal may include: outputting the amplified data signal or scan signal to a display module. For example, it may include: outputting the amplified data signal to a source of a target transistor in the display module, or outputting the amplified scan signal to a gate of a target transistor in the display module.

[0085] In one embodiment, outputting the amplified data signal to the source of the target transistor in the display module may include: outputting the amplified data signal to the source of multiple target transistors in the same column of the display module. Outputting the amplified scan signal to the gate of the target transistor in the display module may include: outputting the amplified scan signal to the gate of multiple target transistors in the same row of the display module.

[0086] In this way, by amplifying the data signal or the scanning signal, the aging speed of the device in the display module can be accelerated, and there is no need to set up a complex screen carousel, thereby improving the efficiency of the device aging process. The flexibility of signal amplification can be further improved by the selection module 1, and the signal output can be flexibly adjusted according to the aging requirements by adjusting the control signal. In addition, by amplifying the output of the data signal and the scanning signal, it is also easier to find possible defects in the data line and the scanning line, thereby improving the product yield.

[0087] In some embodiments, the gating module includes: a first transistor 11 and a second transistor 12; the step S20 of adjusting the control signal to output the amplified data signal or scanning signal through the gating module 1 may include:

[0088] Adjusting the control signal to a high level to control the first transistor 11 to be in an off state and the second transistor 12 to be in an on state;

[0089] Amplifying the data signal or the scanning signal based on the amplification module 2;

[0090] The amplified data signal or scan signal is output to the display module through the second transistor 12 .

[0091] In one embodiment, the first transistor 11 may be a PMOS transistor, the second transistor 12 may be an NMOS transistor, and adjusting the control signal to a high level may include: adjusting the control signal to a high level, and adjusting the high level voltage of the control signal based on the voltage value of the data signal or the scan signal and the turn-on voltage threshold of the second transistor 12. For example, the high level voltage value of the control signal is equal to the sum of the voltage value of the data signal or the scan signal and the turn-on voltage threshold of the second transistor 12.

[0092] In one embodiment, the second input end of the selection module 1 and the input end of the amplification module 2 are connected to the data signal generation circuit 3, and when the data signal is input, the high-level voltage value of the control signal is equal to the sum of the voltage value of the data signal and the on-voltage threshold of the second transistor 12.

[0093] In one embodiment, the second input end of the selection module 1 and the input end of the amplification module 2 are connected to the scanning signal generating circuit 4, and when the scanning signal is input, the high-level voltage value of the control signal is equal to the sum of the voltage value of the scanning signal and the on-voltage threshold of the second transistor 12.

[0094] In this way, the selection control of the two paths of the gating module 1 is realized by the first transistor 11 and the second transistor 12. The path switching can be realized based on the switching of the control signal level, thereby realizing the flexible control of whether to amplify the data signal / scanning signal, improving the availability of the circuit, and there is no need to adjust the circuit after the aging process is completed.

[0095] In some embodiments, the amplification module 2 includes: an amplifier 21, a first resistor 22 and a second resistor 23, wherein the second resistor 23 is a variable resistor; and amplifying the data signal or the scan signal based on the amplification module 2 includes:

[0096] Adjusting the resistance of the second resistor 23 based on the required amplification factor;

[0097] The data signal or the scanning signal is amplified based on the adjusted first resistor 22 , the second resistor 23 and the amplifier 21 .

[0098] In one embodiment, before adjusting the resistance of the second resistor 23 based on the required magnification factor, the method may further include: determining the required magnification factor based on the characteristic parameter of the target transistor. The characteristic parameter may be determined based on at least one of the characteristic curve, current working condition, and working time of the target transistor.

[0099] In one embodiment, the amplification module 2 may further include: a third resistor 24. Amplifying the data signal or the scan signal based on the adjusted first resistor 22, the second resistor 23 and the amplifier 21 may include: performing current limiting protection based on the third resistor 24, and amplifying the data signal or the scan signal based on the adjusted first resistor 22, the second resistor 23 and the amplifier 21.

[0100] In one embodiment, the third resistor 24 may also be a variable resistor, and amplifying the data signal or the scan signal based on the adjusted first resistor 22, the second resistor 23 and the amplifier 21 may include: adjusting the resistance value of the third resistor 24 according to the structure of the data signal generating circuit 3 or the scan signal generating circuit 4; performing current limiting protection based on the adjusted third resistor 24, and amplifying the data signal or the scan signal based on the adjusted first resistor 22, the second resistor 23 and the amplifier 21. In this way, accurate current limiting buffering can be flexibly provided for different data signals or scan signals.

[0101] In one embodiment, the input data signal Vdata is passed through the first resistor 22R1, the second resistor 23R2 and the amplifier 21 to obtain an amplified data signal Vdata′=Vdata*(1+R2 / R1). The input scan signal Vscan is passed through the first resistor 22R1, the second resistor 23R2 and the amplifier 21 to obtain an amplified scan signal Vscan′=Vscan*(1+R2 / R1).

[0102] In this way, the data signal / scan signal can be amplified through the amplifier 21 and the peripheral resistor network including the first resistor 22 and the second resistor 23, so that it can be output to the display module through the enabled path when aging is required, and the target transistor can be efficiently aged.

[0103] This embodiment provides a display module aging method. Figure 6 1 is a flow chart of a display module aging method provided in an embodiment of the present application, and the method can be applied to the display module aging circuit described in any of the above embodiments. Figure 6 As shown, the method may include:

[0104] S11: Determine whether the display module needs to be aged;

[0105] S21: In response to the need to perform aging processing on the display module, adjusting the control signal to output the amplified data signal or the scanning signal through the gating module 1;

[0106] S31 : In response to the display module not needing to be aged, adjusting the control signal to output a data signal or a scan signal through the gating module 1 .

[0107] In this embodiment, the specific implementation methods and related embodiments of step S11 and step S21 can refer to the specific implementation methods and related embodiments of step S10 and step S20 in the aforementioned embodiment, and will not be repeated here.

[0108] In one embodiment, adjusting the control signal to output the data signal or scan signal through the selection module 1 may include: adjusting the control signal to a low level to control the first transistor 11 to be in an on state and the second transistor 12 to be in an off state, and outputting the data signal or scan signal to the display module through the first transistor 11.

[0109] In one embodiment, the first transistor 11 can be a PMOS tube, and the second transistor 12 can be an NMOS tube, so that when the control signal input to the gate is at a low level, the first transistor 11 is turned on and the second transistor 12 is turned off, and the data signal or the scanning signal does not pass through the amplification module 2, but is directly output to the display module through the first transistor 11 to perform normal display module driving.

[0110] In one embodiment, the second input end of the gating module 1 and the input end of the amplifying module 2 are connected to the data signal generating circuit 3 for inputting a data signal, and the data signal is output to the source of the target transistor in the display module through the first transistor 11. For example, the data signal is output to the source of multiple target transistors in the same column in the display module.

[0111] In one embodiment, the second input end of the gating module 1 and the input end of the amplifying module 2 are connected to the scanning signal generating circuit 4, and when the scanning signal is input, the scanning signal is output to the gate of the target transistor in the display module through the first transistor 11. For example, the scanning signal is output to the gates of multiple target transistors in the same row in the display module.

[0112] In this way, when aging treatment is not required, there is no need to adjust the circuit and wiring. The original data signal or scanning signal can be directly output to the display module by adjusting the control signal to a low level to drive the display module.

[0113] This embodiment provides a display panel. Figure 7 is a schematic diagram of a display panel provided in an embodiment of the present application. Figure 7 As shown, it includes: a display module 5, a data signal generating circuit 3, a scanning signal generating circuit 4 and a plurality of display module aging circuits 6 described in any of the aforementioned embodiments; wherein the data signal generating circuit 3 and the scanning signal generating circuit 4 are respectively connected to different display module aging circuits 6.

[0114] Here, the data signal generating circuit 3 and the scanning signal generating circuit 4 are connected to the display module 5 through different display module aging circuits 6 .

[0115] In one embodiment, the display module aging circuit 6 connected to the data signal generating circuit 3 can be arranged in a source driver, and the display module aging circuit 6 connected to the scanning signal generating circuit 4 can be arranged in a gate driver.

[0116] In one embodiment, the number of display module aging circuits 6 connected to the data signal generation circuit 3 may be equal to the number of columns of target transistors in the display module 5. The number of display module aging circuits 6 connected to the scan signal generation circuit 4 may be equal to the number of rows of target transistors in the display module 5.

[0117] In this way, the display panel can add the above-mentioned display module aging circuit 6 in the gate drive and source drive to perform aging treatment on the display module 5. After the aging treatment, there is no need to adjust the circuit architecture and routing, and the switching can be completed by directly adjusting the path through the selection module 1.

[0118] As a possible implementation, the overall block diagram of the display panel is as follows: Figure 8 As shown, it includes three modules: OLED overall display module, gate driver and source driver, wherein the gate driver provides a scan signal Scan to turn on the T1 transistor, and the source driver provides a data signal Vdata to turn on the TD transistor, and then combined with the power supply voltage VDD to drive the display of the diode D. In this embodiment, a display module aging circuit, i.e., an Aging circuit, is added on the basis of the original gate and source drivers. When the control signal, i.e., the Aging_Enable signal, is pulled high, the gate driver Scan signal outputs a Sout signal through the Aging circuit, and the source driver Vdata signal outputs a Vout signal through the Aging circuit. Both of them respectively increase the voltage of the scan signal and the data signal to tighten the aging of the T1 and TD devices, screen out the bad scan lines and data lines, and improve the uniformity of the OLED display.

[0119] The aging circuit module on the gate-source driver can be Fig. 9 As shown, it includes two modules, the selection circuit and the amplifier circuit. The selection circuit module is composed of two transistors, the NMOS tube TN and the PMOS tube TP. The amplifier circuit is composed of an OP amplifier and a peripheral resistor network. R1 and R3 are fixed resistance resistors, and R2 is an adjustable resistance resistor. The Vdata and Scan signals are connected to the source of the TP tube and the input of the amplifier circuit. The output and output relationship is:

[0120] Vdata′=Vdata*(1+R2 / R1); Scan′=Scan*(1+R2 / R1).

[0121] By adjusting the value of R2, the output multiple can be controlled. ′ The drain of the TN tube is connected, the source of the TN tube and the drain of the TP tube are connected to the output signals Vout and Sout, and the gates of the TN and TP tubes are connected to the control signal Aging_Enable. Specifically, the signal timing diagram can be as follows Fig.10 As shown in the figure, when there is no aging requirement, the Aging_Enable signal is low, the lower TP tube of the selection circuit is turned on, Vout = Vdata, Sout = Scan, when there is an aging requirement, the Aging_Enable signal is high, and the upper TN tube in the selection circuit is turned on. Vout = Vdata', Sout = Scan ′ , Vout and Sout are then given to the OLED overall display driver module to complete the strict aging process. Here, the high level voltage of the control signal Aging_Enable ≥ Vdata′ / Scan

[0122] +Vth, Vth is the NMOS conduction threshold 0.2 ~ 0.7V. The specific overall workflow is as follows Fig.11 shown.

[0123] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course can also be implemented by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, a magnetic disk, or an optical disk), and includes a number of instructions for enabling a terminal device (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present invention.

[0124] The above description is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are included in the protection scope of the present application.

[0125] The above description is only a specific implementation of the present application, so that those skilled in the art can understand or implement the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest range consistent with the principles and novel features applied for herein.

Claims

1. A display module aging circuit, characterized in that: include: gating module and amplifying module; The first input end of the gating module is used to input a control signal, and the second input end of the gating module is connected to a data signal generating circuit or a scanning signal generating circuit, and is used to input a data signal or a scanning signal; The input end of the amplification module is connected to the data signal generation circuit or the scan signal generation circuit for inputting the data signal or the scan signal; the output end of the amplification module is connected to the third input end of the gating module for outputting the amplified data signal or the scan signal; The output end of the gating module is connected to the display module, and is used to output the amplified data signal or scanning signal, or output the data signal or scanning signal.

2. The display module aging circuit according to claim 1, characterized in that: The gating module includes: a first transistor and a second transistor; The gate of the first transistor is connected in parallel with the gate of the second transistor for inputting a control signal, and the first transistor and the second transistor are in opposite switching states based on the same control signal; The input electrode of the first transistor is used as the second input terminal of the gating module, and is connected to the data signal generating circuit or the scanning signal generating circuit; the input electrode of the second transistor is used as the third input terminal of the gating module, and is connected to the output terminal of the amplifying module; The output electrode of the first transistor and the output electrode of the second transistor are connected to the display module as the output end of the gating module.

3. The display module aging circuit according to claim 1, characterized in that: The amplification module includes: an amplifier, a first resistor and a second resistor; The positive input terminal of the amplifier is used as the input terminal of the amplification module and is connected to the data signal generation circuit or the scanning signal generation circuit; the negative input terminal of the amplifier is grounded through the first resistor and is connected to the output terminal of the amplifier through the second resistor; The output end of the amplifier is connected to the third input end of the gating module as the output end of the amplifying module.

4. The display module aging circuit according to claim 3, characterized in that: The amplification module further includes: a third resistor; the third resistor is connected between the positive input terminal and the data signal generating circuit or the scanning signal generating circuit.

5. The display module aging circuit according to claim 1, characterized in that: When the second input terminal of the gating module and the input terminal of the amplifying module are connected to the data signal generating circuit, the output terminal of the gating module is connected to the source of at least one transistor in the display module; When the second input end of the gating module and the input end of the amplifying module are connected to the scanning signal generating circuit, the output end of the gating module is connected to the gate of at least one transistor in the display module.

6. A display module aging method, applied to the display module aging circuit according to any one of claims 1 to 5, characterized in that: The method comprises: Determine whether the display module needs to be aged; In response to the need to perform an aging process on the display module, the control signal is adjusted to output the amplified data signal or the scan signal through the gating module.

7. The display module aging method according to claim 6, characterized in that: The gating module includes: a first transistor and a second transistor; the step of adjusting the control signal to output the amplified data signal or the scanning signal through the gating module includes: Adjusting the control signal to a high level to control the first transistor to be in an off state and the second transistor to be in an on state; amplifying the data signal or the scanning signal based on the amplification module; The amplified data signal or scan signal is output to the display module through the second transistor.

8. The display module aging method according to claim 7, characterized in that: The amplification module includes: an amplifier, a first resistor and a second resistor, wherein the second resistor is a variable resistor; and amplifying the data signal or the scanning signal based on the amplification module includes: adjusting the resistance value of the second resistor based on the required amplification factor; The data signal or the scan signal is amplified based on the adjusted first resistor, the second resistor and the amplifier.

9. The method according to claim 6, characterized in that The method further comprises: In response to the display module not needing to be aged, the control signal is adjusted to output the data signal or the scan signal through the gating module.

10. A display panel, characterized in that: include: A display module, a data signal generating circuit, a scanning signal generating circuit, and a plurality of display module aging circuits as claimed in any one of claims 1 to 5; wherein the data signal generating circuit and the scanning signal generating circuit are respectively connected to different display module aging circuits.

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