Display panel and display device

Abstract

The invention provides a display panel and a display device, and belongs to the technical field of display driving, and the display panel comprises a power management circuit, a driving circuit and at least one AND gate circuit. The power management circuit is used for outputting logic voltage. Each AND gate circuit comprises a voltage input end, a signal input end and a signal output end. The voltage input end is connected with the power management circuit. The signal input end is used for accessing a first digital signal. The AND gate circuit is used for converting the first digital signal into a second digital signal after the logic voltage is powered on. The driving circuit is connected with the signal output end of the AND gate circuit and the power management circuit and works based on the logic voltage and the second digital signal. Therefore, the driving circuit is prevented from mistakenly receiving and processing the second digital signal when the logic voltage is not established, so that the power-on time sequence of the driving circuit is ensured to be correct, and the driving circuit is prevented from being abnormal or damaged possibly caused by disorder of the power-on time sequence.

Description

Technical Field

[0001] The present application relates to the field of display driving technology, and in particular to a display panel and a display device. Background Art

[0002] Liquid Crystal Display (LCD) technology is a widely used display technology in modern electronic devices. Through the action of an external electric field, the arrangement direction of liquid crystal molecules can be precisely controlled, thereby modulating light to achieve the purpose of displaying images.

[0003] At present, each integrated circuit (IC) in an LCD display panel needs to meet a certain timing when powered on. For example, when the driver integrated circuit recognizes and processes digital signals, it is necessary to first establish a logic voltage as a reference to ensure that the driver integrated circuit can work in the correct voltage and signal environment. Otherwise, the driver integrated circuit will not work properly. If the digital signal is input before the logic voltage is established, not only will the digital signal not be correctly recognized and processed, but it may also cause abnormal voltage inside the driver integrated circuit, resulting in a shortened life of the driver integrated circuit or even permanent damage.

[0004] Therefore, how to ensure that the driver integrated circuit is powered on at a correct timing is a problem that needs to be solved urgently. Summary of the invention

[0005] In view of the deficiencies in the prior art, the present application provides a display panel and a display device.

[0006] In a first aspect, the present application provides a display panel, comprising:

[0007] A power management circuit for outputting a logic voltage;

[0008] At least one AND gate circuit, each of the AND gate circuits comprising a voltage input terminal, a signal input terminal and a signal output terminal; the voltage input terminal is connected to the power management circuit; the signal input terminal is used to access a first digital signal; the AND gate circuit is used to convert the first digital signal into the second digital signal after the logic voltage is powered on;

[0009] The driving circuit is connected to the signal output terminal of the AND gate circuit and the power management circuit, and operates based on the logic voltage and the second digital signal.

[0010] Optionally, the AND gate circuit includes a switch tube, and the switch tube includes a control electrode connected to the voltage input end, a first electrode connected to the signal input end, and a second electrode connected to the signal output end.

[0011] Optionally, the AND gate circuit includes a clamping subcircuit and a voltage dividing subcircuit;

[0012] The voltage dividing subcircuit is connected to the voltage input terminal and the signal output terminal;

[0013] The clamping subcircuit is connected to the voltage dividing subcircuit, the signal input terminal and the signal output terminal, and is used to be turned on or off according to the first digital signal and the logic voltage;

[0014] Among them, when the clamping subcircuit is turned on, the potential of the signal output end is clamped to the first potential; when the clamping subcircuit is turned off, the potential of the signal output end is the second potential obtained by the voltage divider subcircuit dividing the logic voltage to form the second digital signal.

[0015] Optionally, the voltage dividing subcircuit includes a first resistor and a second resistor;

[0016] The first end of the first resistor is connected to the voltage input end, and the second end is connected to the signal output end and the clamp subcircuit at a voltage division node;

[0017] A first end of the second resistor is connected to the voltage division node, and a second end of the second resistor is grounded.

[0018] Optionally, the clamping subcircuit includes a first diode; the first diode includes an anode connected to the voltage dividing node and a cathode connected to the signal input terminal.

[0019] Optionally, the AND gate circuit further includes a second diode; the second diode includes an anode connected to the voltage dividing node and a cathode connected to the voltage input terminal.

[0020] Optionally, the driving circuit is a source driving circuit, and the first digital signal and the second digital signal include image signals;

[0021] The display panel also includes a timing controller;

[0022] The timing controller is connected to the signal input terminal and is used to output the first digital signal to the signal input terminal;

[0023] The source driving circuit is connected to the signal output terminal, and is used for generating a data signal according to the second digital signal, and outputting the data signal to the pixel circuit.

[0024] Optionally, the display panel further includes an equalizer disposed between the timing controller and the signal input terminal, and the equalizer is used to amplify the first digital signal.

[0025] Optionally, the driving circuit is a timing controller, and the first digital signal and the second digital signal include one of a horizontal synchronization signal, a vertical synchronization signal and a data enable signal.

[0026] In a second aspect, in one embodiment, the present application provides a display device, comprising the display panel as described above.

[0027] In summary, the present application first outputs a logic voltage through a power management circuit. Then, the first digital signal is converted into a second digital signal through an AND gate circuit when the logic voltage is powered on, and the second digital signal is output through its signal output terminal, while the logic state of the second digital signal is always 0 when the logic voltage is not powered on. In this way, it is avoided that the drive circuit mistakenly receives and processes the second digital signal when the logic voltage is not established, thereby ensuring the correct power-on timing of the drive circuit and avoiding abnormalities or damage to the drive circuit that may be caused by confusion in the power-on timing. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0029] Figure 1 This is a schematic diagram of the power-on timing of logic voltage and digital signal in one embodiment of the present application.

[0030] Figure 2 This is a schematic diagram of a display panel in one embodiment of the present application;

[0031] Figure 3 This is a connection diagram of an AND gate circuit in one embodiment of the present application;

[0032] Figure 4 This is a connection diagram of an AND gate circuit in another embodiment of the present application;

[0033] Figure 5 This is an architectural diagram of an AND gate circuit application scenario in one embodiment of the present application;

[0034] Figure 6 This is a schematic diagram of an equalizer in one embodiment of the present application;

[0035] Figure 7 This is an architectural diagram of an AND gate circuit application scenario in another embodiment of the present application.

[0036] Explanation of the reference numerals: 1. power management circuit; 2. AND gate circuit; 21. voltage divider sub-circuit; 22. clamping sub-circuit; 3. drive circuit; 31. source drive circuit; 32. timing controller; 4. gate drive circuit. DETAILED DESCRIPTION

[0037] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0038] In the description of the present application, it should be understood that the terms "first" and "second" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined. In the present application, the word "exemplary" is used to mean "used as an example, illustration or description". Any embodiment described as "exemplary" in the present application is not necessarily interpreted as being more preferred or more advantageous than other embodiments. In order to enable any technician in the field to implement and use the present application, the following description is given. In the following description, details are listed for the purpose of explanation. It should be understood that a person of ordinary skill in the art can recognize that the present application can also be implemented without using these specific details. In other examples, well-known structures and processes will not be elaborated in detail to avoid unnecessary details that make the description of the present application obscure. Therefore, the present application is not intended to be limited to the embodiments shown, but is consistent with the widest range of principles and features disclosed in the present application.

[0039] First, based on the content of the background technology of the present application, the background of the present application is further explained. Figure 1 , Figure 1 Schematic diagram of the power-on timing of the logic voltage VDD1 and the digital signal DIG.

[0040] Figure 1 The figure shows a normal power-on sequence, that is, the logic voltage VDD1 is established first, and after a time interval t1, the digital signal DIG to be processed is provided after the logic voltage VDD1 is stabilized. Figure 1(b) is an abnormal power-on timing, for example, the timing of the logic voltage VDD1 is delayed or the timing of the digital signal DIG is advanced, so that the digital signal DIG is connected first, and the logic voltage VDD1 is established after the time interval t2. At this time, the logic voltage VDD1 cannot be used as the reference voltage of the digital signal DIG, making it difficult for the driving circuit to correctly process the digital signal DIG.

[0041] At present, the related technology usually adopts the method of setting a delay circuit to adjust the timing between the logic voltage VDD1 and the digital signal DIG, that is, a delay circuit is set at the digital signal DIG input terminal DIGin of the driving circuit, so that the digital signal DIG is delayed by the delay circuit before being input to the driving circuit, thereby providing more time to establish a stable logic voltage VDD1, so as to adjust the power-on timing. However, on the one hand, in the field of display driving, if the digital signal DIG is delayed, especially real-time signals such as image signals, it is easy to cause problems such as delay in displaying the picture. On the other hand, the delay circuit can only solve short-term timing problems. For example, when the delay time of the delay circuit is less than Figure 1 At the time interval t2 shown in (b), even if a delay circuit is set, the ideal power-on timing control cannot be achieved, or when the voltage source of the logic voltage VDD1 fails and the logic voltage VDD1 cannot be output, the digital signal DIG after the delay circuit will continue to be input to the drive circuit, causing abnormal operation or even damage to the drive circuit.

[0042] Based on the above problems, this application is proposed. Figure 2 As shown, in one embodiment, the present application provides a display panel, which includes a power management circuit 1, a driving circuit 3 and at least one AND gate circuit 2. The power management circuit 1 is used to output a logic voltage VDD1. At least one AND gate circuit 2, each AND gate circuit 2 includes a voltage input terminal VDD, a signal input terminal DIGin and a signal output terminal DIGout. The voltage input terminal VDD is connected to the power management circuit 1. The signal input terminal DIGin is used to access the first digital signal DIG. The AND gate circuit 2 is used to convert the first digital signal DIG into a second digital signal DIG after the logic voltage VDD1 is powered on. The driving circuit 3 is connected to the signal output terminal DIGout of the AND gate circuit 2 and the power management circuit 1, and operates based on the logic voltage VDD1 and the second digital signal DIG.

[0043] As an example, the real table between the two input terminals (voltage input terminal VDD and signal input terminal DIGin) and the signal output terminal DIGout of the AND gate circuit 2 is shown in Table 1.

[0044]

[0045] The logic voltage is powered on when the potential of the logic voltage is greater than a preset value, and the logic state of the logic voltage is determined to be 1, otherwise the logic state of the logic voltage is 0. When the logic voltage is not powered on, the logic state of the second digital signal is always 0 through the AND gate circuit 2, and after the logic voltage is powered on, the AND gate circuit 2 converts the first digital signal into a second digital signal with a consistent logic state.

[0046] As an example, the power management circuit 1 inputs the logic voltage to the AND gate circuit 2 and the drive circuit 3 respectively, so that the AND gate circuit 2 obtains the second digital signal according to the logic voltage, and the drive circuit 3 uses the logic voltage as a reference voltage to identify and process the second digital signal.

[0047] In the above implementation, the logic voltage is first outputted through the power management circuit 1. Then, the first digital signal is successfully converted into the second digital signal through the AND gate circuit 2 when the logic voltage is powered on, and the second digital signal is outputted through its signal output terminal DIGout, while the logic state of the second digital signal is always 0 when the logic voltage is not powered on. This avoids the driver circuit 3 from erroneously receiving and processing the second digital signal when the logic voltage is not established, thereby ensuring the correct power-on timing of the driver circuit 3 and avoiding abnormality or damage to the driver circuit 3 that may be caused by confusion in the power-on timing.

[0048] Reference Figure 3 As an implementation of the AND gate circuit 2, the AND gate circuit 2 includes a switch tube Q1, and the switch tube Q1 includes a control electrode connected to the voltage input terminal VDD, a first electrode connected to the signal input terminal DIGin, and a second electrode connected to the signal output terminal DIGout.

[0049] As an example, the switch tube Q1 can be an N-type tube. When the logic voltage is powered on, the switch tube Q1 is turned on, and the first digital signal connected to the signal input terminal DIGin is obtained after the conduction voltage drop of the switch tube Q1 to obtain the second digital signal, and the second digital signal is output to the signal output terminal DIGout. When the logic voltage is not established, the switch tube Q1 is turned off, and the first digital signal of the signal input terminal DIGin cannot be transmitted, so that the logic state of the signal output terminal DIGout is always 0.

[0050] In the above implementation, the logic voltage is used as the control electrode signal of the switch tube Q1, so that the switch tube Q1 can conduct between the signal input terminal DIGin and the signal output terminal DIGout only after the logic voltage is powered on, to ensure that the second digital signal is output after the logic voltage is powered on.

[0051] Reference Figure 4As another embodiment of the AND gate circuit 2, the AND gate circuit 2 includes a clamping subcircuit 22 and a voltage divider subcircuit 21. The voltage divider subcircuit 21 is connected to the voltage input terminal VDD and the signal output terminal DIGout. The clamping subcircuit 22 is connected to the voltage divider subcircuit 21, the signal input terminal DIGin and the signal output terminal DIGout, and is used to be turned on or off according to the first digital signal and the logic voltage. When the clamping subcircuit 22 is turned on, the potential of the signal output terminal DIGout is clamped to the first potential. When the clamping subcircuit 22 is turned off, the potential of the signal output terminal DIGout is the second potential obtained by the voltage divider subcircuit 21 dividing the logic voltage to form a second digital signal.

[0052] As an example, the logical state is usually represented by different levels of voltage or current. For example, when the voltage or current level of the signal is higher than the preset logical threshold, the logical state can be determined to be 1 (or high level); when the voltage or current level of the signal is lower than the preset logical threshold, the logical state can be determined to be 0 (or low level). In this embodiment, the first potential and the second potential respectively represent two logical states of the second digital signal, the first potential can be lower than the preset logical threshold, and the corresponding logical state is 0, and the second potential can be higher than the preset logical threshold, and the corresponding logical state is 1.

[0053] In the above embodiment, the clamping subcircuit 22 is turned on or off according to the first digital signal and the logic voltage, thereby providing two logic states. When the clamping subcircuit 22 is turned on, the potential of the signal output terminal DIGout is clamped to a preset first potential. After the clamping subcircuit 22 is turned off, the voltage divider subcircuit 21 divides the logic voltage to obtain a second potential. The first potential and the second potential respectively represent two logic states of the second digital signal, thereby realizing the generation of the second digital signal, and the logic voltage participates in the generation of the second digital signal, so that the second digital signal cannot be generated before the logic voltage is established, thereby ensuring the power-on timing of first establishing the logic voltage and then generating the second digital signal.

[0054] Reference Figure 4 As an implementation of the voltage divider subcircuit 21, the voltage divider subcircuit 21 includes a first resistor R1 and a second resistor R2. The first end of the first resistor R1 is connected to the voltage input terminal VDD, and the second end is connected to the signal output terminal DIGout and the clamp subcircuit 22 at the voltage divider node A. The first end of the second resistor R2 is connected to the voltage divider node A, and the second end is grounded.

[0055] Reference Figure 4 As an implementation of the clamping sub-circuit 22, the clamping sub-circuit 22 includes a first diode Di1. The first diode Di1 includes an anode connected to the voltage dividing node A and a cathode connected to the signal input terminal DIGin.

[0056] As an example, the logic voltage is used as the voltage source of the voltage divider subcircuit 21. When the logic voltage is not established, the potential of the voltage divider node A is 0, so that the potential of the signal output terminal DIGout is 0. When the logic voltage is powered on, if the logic state of the first digital signal is 1, the voltage difference between the potential of the voltage divider node A and the first digital signal after the logic voltage is divided is small, so that the voltage difference across the first diode Di1 is less than the conduction voltage of the first diode Di1, and the first diode Di1 cannot be turned on. At this time, the potential of the voltage divider node A is equal to the second point obtained by dividing the logic voltage by the first resistor R1 and the second resistor R2, that is, the potential of the signal output terminal DIGout is the second potential, and the second potential should be greater than the preset logic threshold, so that the logic state of the second digital signal output by the signal output terminal DIGout is 1. When the logic voltage is powered on, if the logic state of the first digital signal is 0, the voltage difference between the potential at the voltage dividing node A and the first digital signal after the logic voltage is divided is large, thereby turning on the first diode Di1. Since the cathode of the first diode Di1 is connected to the first digital signal with a logic state of 0, the potential of the anode of the first diode Di1 is clamped to the sum of its cathode potential and the conduction voltage of the first diode Di1. The sum is the first potential. The first potential should be less than the preset logic threshold, thereby making the logic state of the second digital signal output by the signal output terminal DIGout 0.

[0057] Furthermore, by adjusting the resistance of the first resistor R1 and the second resistor R2, the voltage division value of the voltage division node A can be changed to match the preset logic thresholds of different drive circuits 3. For example, if the preset logic threshold of the first digital signal is 5V, that is, the first digital signal greater than 5V is judged as a logic state of 1, and less than 5V is judged as a logic state of 0. If the preset logic threshold of the drive circuit 3 is different from the preset logic threshold of the first digital signal, for example, the preset logic threshold of the drive circuit 3 is 3V, then the voltage division value of the voltage division node A can be adjusted to be greater than 3V by adjusting the resistance of the first resistor R1 and the second resistor R2, so that the drive circuit 3 can correctly identify the logic state of the second digital signal.

[0058] In the above embodiment, the first diode Di1 can clamp its anode potential according to its cathode potential when it is turned on, so as to provide a stable first potential, so that the logic state of the second digital signal output by the signal output terminal DIGout is 0; at the same time, when the first diode Di1 is turned off, the potential of the signal output terminal DIGout is determined by the voltage division of the first resistor R1 and the second resistor R2, so as to output a suitable second level, so that the logic state of the second digital signal output by the signal output terminal DIGout is 1.

[0059] Reference Figure 4 As a further embodiment of the AND gate circuit 2, the AND gate circuit 2 further includes a second diode Di2. The second diode Di2 includes an anode connected to the voltage division node A and a cathode connected to the voltage input terminal VDD.

[0060] In the above implementation, the second diode Di2 helps to absorb the interference signal, thereby preventing the interference signal from being erroneously transmitted to the signal output terminal DIGout.

[0061] Reference Figure 6 As a first implementation of the driving circuit 3, the driving circuit 3 may be a source driving circuit 31, and the first digital signal and the second digital signal may include an image signal. Based on this implementation, the display panel further includes a timing controller 32. The timing controller 32 is connected to the signal input terminal DIGin, and is used to output the first digital signal to the signal input terminal DIGin. The source driving circuit 31 is connected to the signal output terminal DIGout, and is used to generate a data signal according to the second digital signal, and output the data signal to the pixel circuit.

[0062] The image signal may be in various formats, which are not specifically limited here, such as low-voltage differential signaling (LVDS) signal, DPI (Digital Panel Interface) signal, etc.

[0063] Figure 6 Schematic diagram of a display panel in an embodiment of the present application, the display panel also includes a gate drive circuit 43. The display area 5 of the display panel may include a plurality of scan lines G1 to Gn, a plurality of data lines D1 to Dm intersecting the plurality of scan lines G1 to Gn, and a plurality of pixel units respectively arranged in a plurality of regions defined by the intersection of the scan lines G1 to Gn and the data lines D1 to Dm. For example, the pixel unit may include a thin film transistor (TFT), which includes a gate and a source electrode respectively connected to the scan line and the data line corresponding thereto. When a scan line is selected from the plurality of scan lines G1 to Gn, the thin film transistor of the pixel unit connected to the selected scan line is turned on, and then the source drive circuit 31 may apply a voltage to the plurality of data lines D1 to Dm, thereby displaying an image.

[0064] Among them, the power management circuit 1 provides power supply for the timing controller 32, the source driving circuit 31 and the gate driving circuit 43. The timing controller 32 receives the image data and the control signal, and performs pre-processing such as format conversion and data sorting on the image data to obtain the image signal. At the same time, the timing controller 32 also generates a control signal and a clock signal. Then, the image signal and the control signal are sent to the source driving circuit 31 and the gate driving circuit 43 respectively. The gate driving circuit 43 receives the control signal and the clock signal from the timing controller 32 to generate a gate driving signal for line-by-line scanning, and sequentially turns on or off the thin film transistor switches in the display area 5 through the gate driving signal to control the gating of the scanning line. After receiving the image signal from the timing controller 32, the source driving circuit 31 converts the image signal into a data signal and stores it in the internal register, and outputs it synchronously according to the scanning signal of the gate driving circuit 43.

[0065] In the above embodiment, the driving circuit 3 is a source driving circuit 31, and the first digital signal and the second digital signal include an image signal, which ensures that the source driving circuit 31 first establishes a logic voltage and then receives the image signal, thereby ensuring that the source driving circuit 31 can work normally, and then the display panel can display a normal picture.

[0066] In some embodiments, the display panel further includes an equalizer EQ disposed between the timing controller 32 and the signal input terminal DIGin, for amplifying the first digital signal.

[0067] Reference Figure 7 As a second implementation of the driving circuit 3, the driving circuit 3 may also be a timing controller 32. In this case, the first digital signal and the second digital signal include one of a horizontal synchronization signal, a vertical synchronization signal and a data enable signal.

[0068] Among them, the horizontal synchronization signal (Horizontal Synchronization, HSYNC) is used to indicate the beginning and end of a row of pixel data. The vertical synchronization signal (Vertical Synchronization, VSYNC) is used to indicate the beginning and end of a frame of image, marking the end of the image data transmission of the current frame and the start of the data transmission of a new frame. The data enable signal (Data Enable, DE) is used to indicate whether the currently transmitted pixel data is valid. When the data enable signal is at a high level, it indicates that the currently transmitted image signal is valid; when the data enable signal is at a low level, it indicates that the currently transmitted image signal is invalid and should be ignored. The horizontal synchronization signal, the vertical synchronization signal and the data enable signal can be sent to the timing controller 32 by the front end of the display panel or components such as the graphics processing unit (GPU).

[0069] As an example, the second embodiment of the driving circuit 3 is consistent with the architecture of the display panel of the first embodiment of the driving circuit 3, and will not be described in detail here. Different from the first embodiment, in this embodiment, the AND gate circuit 2 is arranged between the timing controller 32 and the power management circuit 1, so as to ensure that the logic voltage is established first, and then the horizontal synchronization signal, the vertical synchronization signal or the data enable signal is connected to ensure that the timing controller 32 works normally.

[0070] It should be noted that the driving circuit 3 can be any circuit in the display panel that requires power-on timing control, and is not specifically limited here.

[0071] In a second aspect, in one embodiment, the present application provides a display device, comprising the display panel as described above.

[0072] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0073] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other without conflict.

[0074] The above are only preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. A display panel, characterized in that: include: A power management circuit for outputting a logic voltage; At least one AND gate circuit, each of the AND gate circuits comprising a voltage input terminal, a signal input terminal and a signal output terminal; The voltage input terminal is connected to the power management circuit; the signal input terminal is used to receive the first digital signal; the AND gate circuit is used to convert the first digital signal into a second digital signal after the logic voltage is powered on; The driving circuit is connected to the signal output terminal of the AND gate circuit and the power management circuit, and operates based on the logic voltage and the second digital signal.

2. The display panel according to claim 1, characterized in that: The AND gate circuit includes a switch tube, and the switch tube includes a control electrode connected to the voltage input end, a first electrode connected to the signal input end, and a second electrode connected to the signal output end.

3. The display panel according to claim 1, characterized in that: The AND gate circuit includes a clamping subcircuit and a voltage dividing subcircuit; The voltage dividing subcircuit is connected to the voltage input terminal and the signal output terminal; The clamping subcircuit is connected to the voltage dividing subcircuit, the signal input terminal and the signal output terminal, and is used to be turned on or off according to the first digital signal and the logic voltage; Among them, when the clamping subcircuit is turned on, the potential of the signal output end is clamped to the first potential; when the clamping subcircuit is turned off, the potential of the signal output end is the second potential obtained by the voltage divider subcircuit dividing the logic voltage to form the second digital signal.

4. The display panel according to claim 3, characterized in that: The voltage dividing subcircuit includes a first resistor and a second resistor; The first end of the first resistor is connected to the voltage input end, and the second end is connected to the signal output end and the clamp subcircuit at a voltage division node; A first end of the second resistor is connected to the voltage division node, and a second end of the second resistor is grounded.

5. The display panel according to claim 4, characterized in that: The clamping subcircuit includes a first diode; the first diode includes an anode connected to the voltage division node and a cathode connected to the signal input terminal.

6. The display panel according to claim 4, characterized in that: The AND gate circuit further includes a second diode; the second diode includes an anode connected to the voltage division node and a cathode connected to the voltage input terminal.

7. The display panel according to any one of claims 1 to 6, characterized in that: The driving circuit is a source driving circuit, and the first digital signal and the second digital signal include image signals; The display panel also includes a timing controller; The timing controller is connected to the signal input terminal and is used to output the first digital signal to the signal input terminal; The source driving circuit is connected to the signal output terminal, and is used for generating a data signal according to the second digital signal, and outputting the data signal to the pixel circuit, so that the display panel performs display based on the data signal.

8. The display panel according to claim 7, characterized in that: The display panel further includes an equalizer disposed between the timing controller and the signal input terminal, and the equalizer is used to amplify the first digital signal.

9. The display panel according to any one of claims 1 to 6, characterized in that: The driving circuit is a timing controller, and the first digital signal and the second digital signal include one of a horizontal synchronization signal, a vertical synchronization signal, and a data enable signal.

10. A display device, characterized in that: include: A display panel as claimed in any one of claims 1 to 9.

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