Memory, data storage method, chip and electronic equipment

Abstract

The invention discloses a memory, a data storage method, a chip and electronic equipment, and belongs to the technical field of electronic information. The memory comprises a storage module and an output module; the storage module is used for performing redundant storage on the original data to obtain first data and second data; the output module is used for performing logical operation on the first data and the second data to obtain first operation result data; and outputting third data based on the first operation result data. According to the method and the device, two pieces of data which are the same as the original data are stored redundantly, and even if the stored two pieces of data are possibly changed after being stored and become the first data and the second data, the first data and the second data are subjected to logical operation; the first operation result data which is more accurate than the first data and the second data can be obtained, so that the more accurate third data can be output based on the first operation result data.

Description

Technical Field

[0001] The present application relates to the field of electronic information technology, and in particular to a memory, a data storage method, a chip and an electronic device. Background Art

[0002] In the field of electronic information technology, memory records electronic signals through different physical media to store the data corresponding to the electronic signals. During the storage process of data in the memory, it may change due to the influence of various factors, resulting in the data read from the memory may be different from the stored data, thus affecting the accuracy of subsequent data processing based on the read data. Summary of the invention

[0003] The present application provides a memory, a data storage method, a chip and an electronic device, which can be used to improve the accuracy of output data. The technical solution is as follows:

[0004] On the one hand, the present application provides a memory, which includes a storage module and an output module; the storage module is used to redundantly store original data to obtain first data and second data; the output module is used to perform logical operations on the first data and the second data to obtain first operation result data; based on the first operation result data, output third data.

[0005] In one possible implementation, the output module is used to generate first verification data based on first operation result data and verification data generation rules; determine third data based on a first comparison result of the first verification data and the second verification data, and the second verification data is generated according to the verification data generation rules and the original data.

[0006] In one possible implementation, the output module is used to determine the first operation result data as the third data when the first comparison result indicates that the first verification data and the second verification data are the same; or, when the first comparison result indicates that the first verification data and the second verification data are different, restore the third data according to the verification data generation rule, the first verification data, the second verification data and the first operation result data.

[0007] In a possible implementation, the output module is used to perform an XOR operation on the first operation result data and the inverted data to obtain the second operation result data, where the inverted data is obtained by inverting the original data; and determine the third data based on the second operation result data.

[0008] In a possible implementation, the output module is used to determine the first operation result data as the third data when the second operation result data indicates that the values ​​of each group of corresponding bits in the first operation result data and the inverted data are different.

[0009] In one possible implementation, the output module is used to determine the first operation result data as third data when the second operation result data indicates that the values ​​of at least one group of corresponding bits in the first operation result data and the inverted data are the same and the number of bits with the first value in the first operation result data is the same as a reference number, and the reference number is the number of bits with the first value in the original data; or, when the second operation result data indicates that the values ​​of at least one group of corresponding bits in the first operation result data and the inverted data are the same and the number of bits with the second value in the inverted data is the same as the reference number, invert the inverted data to obtain third data, the reference number is the number of bits with the first value in the original data, and the second value is opposite to the first value.

[0010] In a possible implementation, the output module is used to determine the first operation result data as the third data.

[0011] In a possible implementation, the logical operation includes an OR operation.

[0012] In a possible implementation, the storage module includes a one time programmable (OTP) unit, and the OTP unit is used to store the first data and the second data.

[0013] On the other hand, a data storage method is provided, the method comprising: redundantly storing original data to obtain first data and second data; performing logical operations on the first data and the second data to obtain first operation result data; and outputting third data based on the first operation result data.

[0014] In one possible implementation, outputting third data based on first operation result data includes: generating first verification data according to the first operation result data and verification data generation rules; determining third data according to a first comparison result of the first verification data and the second verification data, the second verification data being generated according to the verification data generation rules and the original data; and outputting third data.

[0015] In one possible implementation, third data is determined based on a first comparison result of first verification data and second verification data, including: when the first comparison result indicates that the first verification data and the second verification data are the same, the first operation result data is determined as the third data; or, when the first comparison result indicates that the first verification data and the second verification data are different, the first operation result data is restored according to the verification data generation rule, the first verification data, and the second verification data to obtain the third data.

[0016] In one possible implementation, outputting third data based on first operation result data includes: performing an XOR operation on the first operation result data and inverted data to obtain second operation result data, wherein the inverted data is obtained by inverting the original data; and outputting third data based on the second operation result data.

[0017] In one possible implementation, outputting third data based on second operation result data includes: when the second operation result data indicates that the values ​​of each group of corresponding bits in the first operation result data and the inverted data are different, determining the first operation result data as the third data; and outputting the third data.

[0018] In one possible implementation, outputting third data according to second operation result data includes: determining the first operation result data as third data when the second operation result data indicates that the values ​​of at least one group of corresponding bits in the first operation result data and the inverted data are the same and the number of bits with the first value in the first operation result data is the same as a reference number, and the reference number is the number of bits with the first value in the original data; or, when the second operation result data indicates that the values ​​of at least one group of corresponding bits in the first operation result data and the inverted data are the same and the number of bits with the second value in the inverted data is the same as the reference number, inverting the inverted data to obtain third data, the reference number is the number of bits with the first value in the original data, and the second value is opposite to the first value; and outputting the third data.

[0019] In a possible implementation, outputting third data based on first operation result data includes: determining the first operation result data as the third data; and outputting the third data.

[0020] In a possible implementation, the logical operation includes an OR operation.

[0021] In a possible implementation manner, the method is applied to a memory, the memory includes an OTP unit, and the first data and the second data are stored through the OTP unit.

[0022] On the other hand, a chip is also provided, the chip comprising any possible memory described above.

[0023] On the other hand, an electronic device is also provided, and the electronic device includes any possible memory as described above.

[0024] The technical solution provided by this application brings at least the following beneficial effects:

[0025] In the present application, two copies of data that are identical to the original data are redundantly stored. Even though the two copies of the stored data may change after storage and become the first data and the second data, by performing logical operations on the first data and the second data, first operation result data that is more accurate than the first data and the second data can be obtained, thereby enabling more accurate third data to be output based on the first operation result data. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0027] Figure 1 is a schematic diagram of the structure of a memory provided in an embodiment of the present application;

[0028] Figure 2 is a schematic diagram of redundant storage of original data provided by an embodiment of the present application;

[0029] Figure 3 It is a structural schematic diagram of a one-time programmable unit provided by the related art;

[0030] Figure 4 is a schematic diagram of the structure of another memory provided in an embodiment of the present application;

[0031] Figure 5 This is a schematic diagram of a data storage after a period of storage provided by an embodiment of the present application;

[0032] Figure 6 It is a schematic diagram of a calculation process provided by an embodiment of the present application;

[0033] Figure 7 is a schematic diagram of another data storage after a period of time provided by an embodiment of the present application;

[0034] Figure 8 is another schematic diagram of a calculation process provided in an embodiment of the present application;

[0035] Fig. 9 This is a schematic diagram of another data storage after a period of time provided by an embodiment of the present application;

[0036] Fig.10 This is another schematic diagram of a calculation process provided by an embodiment of the present application;

[0037] Fig.11 is a schematic diagram of the structure of another memory provided in an embodiment of the present application;

[0038] Fig.12 is a structural diagram of another memory provided in an embodiment of the present application;

[0039] Fig.13 It is a flow chart of a data storage method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0040] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0041] Memory is a device that stores data and can store input data. Memory includes many types, such as semiconductor memory. Semiconductor memory includes volatile memory and non-volatile memory. The characteristic of volatile memory is that it maintains the stored data when power is supplied and erases the data when the power is cut off. Non-volatile memory has the function of not erasing the data stored in the storage unit even if the power is interrupted.

[0042] Regardless of the type of memory, the data stored in the memory may change (or be damaged). For example, the data in the memory may change due to electromagnetic interference, circuit aging in the memory, or power outages. If the data stored in the memory changes, when reading the data, the data read may be erroneous data, which will affect the accuracy of subsequent data processing. Therefore, in the field of electronic information technology, the read data is usually detected and corrected to restore accurate data and reduce the impact of reading erroneous data.

[0043] The related art provides a variety of solutions for detecting and correcting the read data. For example, the related art provides a solution for data storage based on error checking and correcting (ECC) check codes. In this solution, when the data to be stored is written into the memory, a check code can be generated according to certain rules, and the data to be stored and the check code are stored. When the stored data needs to be read, the memory will generate a new check code for the stored data according to the same rules. If the new check code is the same as the stored check code, it is considered that the stored data has not changed, that is, the stored data is still correct data, and the stored data can be output to realize data reading. If the new check code is different from the stored check code, the memory will perform data correction according to the rules for generating the check code, the new check code, the stored check code and the stored data, and output the corrected data to realize data reading.

[0044] However, when correcting data through the ECC check code, only the value of one bit in the data can be corrected. If the values ​​of multiple bits in the stored data change, the ECC check code cannot correct it. Therefore, the relevant technology is difficult to ensure the accuracy of the output data.

[0045] The embodiment of the present application provides a memory that can improve the accuracy of output data, or improve the consistency of output data with corresponding stored data. The memory can be applied to a variety of implementation scenarios where data storage is required, for example, the memory can be applied to display driver integrated circuit (Display Driver Integrated Circuit, DDIC), organic light emitting diode (Organic Light Emitting Diode, OLED) DDIC, timing controller (Timing Controller, TCON) and touch and display driver integrated circuit (Touch and Display Driver Integrated Circuit, TDDIC), liquid crystal display driver integrated circuit (Liquid Crystal Display Driver Integrated Circuit, LCD DDIC), display, automobile storage system or camera storage system and any other scenarios where data storage is required.

[0046] See also Figure 1 , shows a schematic diagram of the structure of a memory provided by an embodiment of the present application, the memory includes a storage module 11 and an output module 12 connected to each other. The storage module 11 and the output module 12 can be composed of hardware circuits and related devices, such as logic gates, resistors or power supplies.

[0047] The storage module 11 is used to perform redundant storage on the original data to obtain the first data and the second data; the output module 12 is used to perform logical operations on the first data and the second data to obtain the first operation result data; and output the third data based on the first operation result data. The original data is the data initially stored or written into the storage module 11, and the first data stored in the storage module 11 is obtained based on the original data, that is, the data initially stored in the storage module 11 is the original data, but the original data may be changed during the storage process of the storage module 11, and become the first data, and the first data may be the same as the original data or different from the original data. The second data is obtained by copying the original data, that is, when the original data is stored in the storage module 11, the storage module 11 may copy the original data, and save both the original data and the copied data, and the copied data may also be changed during the storage process of the storage module 11, and become the second data, and the second data may be the same as the original data or different from the original data. The second data can also be called the backup data or redundant data of the first data, and the second data may be the same as or different from the first data.

[0048] For example, if the original data is 0xA3, the storage module 11 can copy the original data and expand the number of bits of the original data to obtain 0xA3A3 when storing the original data. If the number of bits of the original data is 8 bits, 0xA3A3 with 16 bits is expanded, and the data is stored in the form of 0xA3A3 to achieve redundant storage of the original data. When storing 0xA3A3, the storage module 11 can store the high-order data and the low-order data in different locations.

[0049] See also Figure 2 , showing a schematic diagram of redundant storage of original data. Figure 2 The original data 0xA3A3 in hexadecimal (Hex) is changed to binary (B) format, so the original data stored is 10100011, and redundantly stored as 1010001110100011. Among them, the data with bit numbers from 15 to 8 are high-order data, and the data with bit numbers from 7 to 0 are low-order data. The high-order data and the low-order data can be stored in different positions of the storage module 11 respectively.

[0050] That is, in the embodiment of the present application, the first data and the second data stored in the storage module 11 may be located at different positions in the storage module 11, and when reading the first data and the second data, the first data and the second data may be read based on different addresses, respectively. The first data and the second data are stored at different positions in the storage module 11, so that the environments to which the first data and the second data belong are different, and thus the possibility and manner of the first data and the second data being affected by environmental factors may be different, which is more conducive to obtaining the third data identical to the original data based on the first data and the second data.

[0051] For example, the first data and the second data are stored based on different circuits and devices. The circuits and devices storing the first data may be damaged due to voltage instability, causing the first data to change. However, the second data may not be affected by the voltage, resulting in the second data being the same as the original data. Therefore, it is easier to obtain the third data that is the same as the original data based on the first data and the second data, which can better reflect the effectiveness of redundant storage.

[0052] In a possible implementation, the memory provided in the embodiment of the present application may be a non-volatile memory based on a fuse method such as OTP or multiple-time programmable (MTP). Taking the memory as an OTP-based non-volatile memory as an example, the memory may store data through multiple OTP cells, and each OTP cell may have an unprogrammed or programmed state. Even if a power outage occurs, the OTP cell will not lose the programmed data, and the programmed OTP cell may have an irreversible characteristic that cannot be reprogrammed.

[0053] See also Figure 3 , shows a schematic diagram of the structure of an OTP cell provided by the related art. The OTP cell is an OTP cell that stores data based on an embedded fuse (Embedded Fuse, Efuse) or a fuse. The OTP cell stores binary data by controlling the connection or disconnection of the Efuse (or fuse). Figure 3As shown, the OTP cell can be connected to a word line (WL) and a bit line (BL). Among them, WL is a horizontal line connecting multiple OTP cells. One WL can select an entire row of OTP cells. When a WL is selected, all OTP cells connected to the WL are activated so that the OTP cells connected to the WL can be read or programmed. BL is a vertical line connecting OTP cells. In a read or write operation, BL will provide or detect the data level through the connected OTP cell. When a specific OTP cell is selected, WL activates the row, and BL is responsible for transmitting the value in the data corresponding to the OTP cell.

[0054] The OTP cell includes an Efuse (or fuse) and a transistor (Transistor, TR). During the programming process, that is, during the data writing process, the WL corresponding to the data storage location is selected, the corresponding row is activated, and then a programming voltage VDD is applied to the corresponding BL. This programming voltage VDD changes the state of the Efuse (or fuse) in the OTP cell. For example, to Figure 3 By applying programming voltage VDD to the OTP unit in the device, the Efuse (or fuse) in the OTP unit can be controlled to become connected or disconnected. When Efuse (or fuse) is in the connected state, it indicates that the value written to the bit is 1; when Efuse (or fuse) is in the disconnected state, it indicates that the value written to the bit is 0.

[0055] Since the OTP cell is one-time programmable, once the OTP cell is programmed, the Efuse (or fuse) state is fixed and irreversible. If you need to change the value stored in the OTP cell that has stored 0 to 1, you must reconnect the Efuse (or fuse), but a damaged Efuse (or fuse) cannot be reconnected. Therefore, once the value stored in the OTP cell is 0, the Efuse (or fuse) in the OTP cell is cut off, and the value stored in the OTP cell cannot be changed back to 1.

[0056] See also Figure 4Another possible structural diagram of a memory is shown, in which the storage module 11 may include one or more OTP units 111, and the first data and the second data are stored through the OTP unit 111. Based on the above description of the characteristics of the OTP unit 111, it can be known that if the value stored in the OTP unit 111 is 0, permanent storage of 0 can be achieved. However, if the Efuse (or fuse) in the OTP unit 111 is in a connected state, that is, the stored value is 1, after storage, due to the instability of the programming voltage applied to the OTP unit 111, the Efuse (or fuse) may be damaged, thereby causing the value stored in the OTP unit 111 to change from 1 to 0.

[0057] In the embodiment of the present application, after reading the first data and the second data, the output module 12 can process the first data and the second data. Even if the data stored in the OTP unit 111 is changed, the third data that is the same as or more similar to the original data can be restored and output, thereby improving the accuracy of the read data.

[0058] There are multiple ways for the output module 12 to process the first data and the second data and output the third data that is the same as the original data. For example, the output module 12 can perform a logical operation on the first data and the second data to obtain first operation result data; based on the first operation result data, obtain and output the third data.

[0059] Since the value stored in the OTP unit 111 can only change from 1 to 0, but not from 0 to 1, the position of 1 in the original data can be determined based on the first data and the second data, and accurate third data can be obtained. Based on this feature, the first operation result data can be obtained by performing an OR operation on the first data and the second data, and the third data can be determined based on the first operation result data. That is, the logical operation includes an OR operation. By performing an OR operation on the first data and the second data, as long as the value of at least one bit in a group of bits corresponding to the first data or the second data has not changed, the third data identical to the original data can be restored. Among them, the corresponding group of bits refers to two bits in the same order as the multiple bits of the first data and the multiple bits of the second data.

[0060] For example, see Figure 5 A schematic diagram of data storage after a period of storage is shown, the first data is data from the 15th bit to the 8th bit, the second data is data from the 7th bit to the 0th bit, the 15th bit is 1 in the order of the multiple bits of the first data, the 7th bit is also 1 in the order of the multiple bits of the second data, so the 15th bit and the 7th bit are a corresponding set of bits. Correspondingly, the 14th bit and the 6th bit are also a corresponding set of bits.

[0061] contrast Figure 2 and Figure 5 It can be seen that the stored first data has not changed and is still 10100011, while the data of the 5th bit and the 1st bit in the stored second data have changed from 1 to 0, that is, the second data has become 10000001, and the hexadecimal data corresponding to the second data has become 0x81. Figure 6 After the operation process shown performs a bitwise OR operation on the first data and the second data, the first operation result data obtained is 10100011, and the corresponding hexadecimal data is 0xA3.

[0062] Figure 7 A schematic diagram showing another type of data storage after a period of time. Figure 2 and Figure 7 It can be seen that the first data stored has changed to 10000001, and the hexadecimal data corresponding to the first data has changed to 0x81. The second data stored has also changed to 10100010, and the hexadecimal data corresponding to the second data has changed to 0xA2. Figure 8 After the operation process shown performs a bitwise OR operation on the first data and the second data, the first operation result data obtained is 10100011, and the corresponding hexadecimal data is 0xA3.

[0063] Fig. 9 A schematic diagram showing another type of data storage after a period of time. Figure 2 and Fig. 9 It can be seen that the stored first data has not changed, but the stored second data has changed to 00000000, and the hexadecimal data corresponding to the second data has changed to 0x00. Fig.10 After the operation process shown performs a bitwise OR operation on the first data and the second data, the first operation result data obtained is 10100011, and the corresponding hexadecimal data is 0xA3.

[0064] After obtaining the first operation result data, the third data can be obtained based on the first operation result data in a variety of different ways. For example, the output module 12 can obtain the third data in the following ways A to C.

[0065] Method A: The first operation result data is determined as the third data. Figure 5 , Figure 7 and Fig. 9As can be seen from the description, even if the value of one or more bits of the first data or the second data changes, the first operation result data identical to the original data can be obtained by performing a bitwise OR operation on the first data and the second data, and thus the first operation result data can be determined as the third data. Mode A can efficiently determine accurate third data when the value of at most one bit in each group of bits of the first data and the second data changes.

[0066] Method B: Generate first verification data according to the first operation result data and verification data generation rules; determine third data according to a first comparison result of the first verification data and the second verification data, and the second verification data is generated according to the verification data generation rules and the original data.

[0067] That is, in mode B, the first operation result data can be further detected and corrected to further improve the accuracy of the output third data. The verification data generation rule can be a generation rule of the ECC check code. When the original data is written, the storage module 11 can generate second verification data based on the original data according to the verification data, and also store the second verification data. When the third data needs to be read, the first verification data is generated based on the first operation result data according to the verification data generation rule. The first verification data and the second verification data are compared to obtain a first comparison result.

[0068] When the third data is determined according to the first comparison result, the third data may be determined based on two different methods: method B1 and method B2.

[0069] Mode B1: when the first comparison result indicates that the first verification data and the second verification data are the same, the first operation result data is determined as the third data.

[0070] The second verification data is verification data generated based on the original data, and the first verification data is verification data generated based on the first operation result data. Since the verification data generation rules used to generate the first verification data and the second verification data are the same, if the first verification data and the second verification data are the same, it means that the first operation result data used to generate the first verification data and the second verification data respectively are the same as the original data, then the first operation result data can be determined as the third data.

[0071] In method B1, even though the second verification data may be erroneous, the first operation result data may be different from the original data, but both the first operation result data and the second verification data are changed, and the probability that the changed second verification data is exactly the same as the first verification data generated by the first operation result data is very small. Therefore, when the first verification data and the second verification data are the same, the first operation result data is likely to be the same as the original data. Therefore, in this case, determining the first operation result data as the third data can improve the accuracy of the output third data.

[0072] Mode B2: when the first comparison result indicates that the first verification data and the second verification data are different, the third data is restored according to the verification data generation rule, the first verification data, the second verification data and the first operation result data.

[0073] If the first verification data and the second verification data are different, it means that the first operation result data is different from the original data, or the second verification data has changed, so the first operation result data cannot be used as the third data. In this case, the first operation data can be corrected by the verification data generation rule, the first verification data and the second verification data to recover the third data.

[0074] For example, the different parts of data in the first verification data and the second verification data can be compared, and according to the verification data generation rule, the data a that generated this part of data in the first verification data and the data b that generated this part of data in the second verification data can be reversed, and then part of the data in the first operation result data can be replaced based on the data b to obtain the third data.

[0075] For example, the original data is 1011, and 1011 is d1-d4 respectively, that is, d1=1, d2=0, d3=1, d4=1; the verification data generation rule is to generate the second verification data p1p2p3 according to the original data, p1 is the value of the XOR result of d1 and d2 and then the XOR value of d3, p1=0; p2 is the value of the XOR result of d1 and d3 and then the XOR value of d4, p2=1; p3 is the value of d2 and d4, p3=1; that is, the second verification data is 011.

[0076] Assuming that the first operation result data is 0011, according to the same verification data generation rule, the first verification data p4p5p6=101 is generated according to the first operation result data. The first verification data and the second verification data are different, and the different partial data are the first two bits of the first verification data and the second verification data, that is, p4 is different from p1, and p5 is different from p2. According to the verification data generation rule, it can be deduced that the partial data for generating p4 is 001x, the data for generating p5 is 0x11, the data for generating p1 is 101x, and the data for generating p2 is 1x11. Therefore, it can be determined that the value of the first bit in the first operation result data is different from the value of the first bit in the original data, and the first bit in the first operation result data can be replaced to restore the third data 1011.

[0077] Mode C: Perform an XOR operation on the first operation result data and the inverted data to obtain the second operation result data, where the inverted data is obtained by inverting the original data; determine the third data based on the second operation result data.

[0078] When storing the original data, the storage module 11 may store an additional inverted data. For example, for the original data 00001111, the storage module 11 may store an inverted data 11110000 on the basis of storing the first data and the second data.

[0079] Since data can only change from 1 to 0 but not from 0 to 1, if the value of a bit in the inverted data is 1, the value of the bit in the original data must be 0. If the value of a bit in the inverted data is 0, it means that the value of the bit in the original data is 1. Only when an error occurs will the values ​​of the corresponding bits in the inverted data and the first operation result data be 0.

[0080] For example, the original data is 00001111, the first operation result data calculated for the first data and the second data is 00001011, and the stored inverted data is 11110000, and the second operation result data obtained by operating the first operation result data and the inverted data is 11111011. Based on the second operation data, it can be known that the second bit in the inverted data or the first operation result data has changed. Therefore, the method C can accurately determine the bit where the error occurs, which is more conducive to data correction and outputting more accurate third data.

[0081] After obtaining the second operation result data, the third data may be determined according to the second operation result data in the following manners C1 to C3.

[0082] Mode C1: when the second operation result data indicates that the values ​​of each group of corresponding bits in the first operation result data and the inverted data are different, the first operation result data is determined as the third data.

[0083] If the values ​​of the corresponding bits of the first operation result data and the inverted data are different, it means that the first operation result data is completely opposite to the inverted data. Because the values ​​in the first operation result data and the inverted data can only change from 1 to 0 but not from 0 to 1, in a group of corresponding bit values, only one bit value can change, or in other words, for a group of corresponding bits, one possibility is that the value of the first operation result data in the group of bit values ​​has changed from 1 to 0 (in this case, the value of the inverted data in the group of bit values ​​is 0 and cannot change); another possibility is that the value of the inverted data in the group of bit values ​​has changed from 1 to 0 (in this case, the value of the first operation result data in the group of bit values ​​is 0 and cannot change), and there is no other possibility, so as long as the values ​​of a group of bits are different, the values ​​of the group of bits are all correct values.

[0084] Therefore, in mode C1, the values ​​of each group of bits are different, and the first operation result data can be directly output as the third data. The output third data is the same as the original data, which improves the accuracy of the output third data.

[0085] Method C2: When the second operation result data indicates that the values ​​of at least one group of corresponding bits in the first operation result data and the inverted data are the same, compare the number of bits whose values ​​are the first value in the first operation result data with a reference number, where the reference number is the number of bits whose values ​​are the first value in the original data; when the number of bits whose values ​​are the first value in the first operation result data is the same as the reference number, determine the first operation result data as the third data.

[0086] If the data of corresponding bits in the first operation result data and the inverted data are the same, it means that an error has occurred in the first operation result data or the inverted data, and the stored reference quantity can be reused to determine which data has the error.

[0087] The reference number may be, for example, the number of 1s in the original data. If the number of 1s in the first operation result data is the same as the number of 1s in the original data, the first operation result data may be considered correct and the first operation result data may be determined as the third data.

[0088] Method C3: When the second operation result data indicates that at least one group of corresponding bits in the first operation result data and the inverted data are the same, compare the number of bits in the inverted data whose value is the second value with the reference number, and the second value is opposite to the first value; when the number of bits in the inverted data whose value is the second value is the same as the reference number, invert the inverted data to obtain third data.

[0089] If the number of 0s in the inverted data is the same as the number of 1s in the original data, it can be considered that the inverted data has not changed, so the inverted data can be inverted again to obtain third data that is the same as the original data.

[0090] For example, the original data is 11011, and the first value is 1. When redundantly storing the original data, the storage module 11 can also store a reference number 4, and the inverted data 00100 obtained by inverting. If the first data is 11010 and the second data is 11000 when reading the data, the first operation result data is 11010. The result of the XOR operation on the first operation result data and the inverted data is 11110, which means that there is a group of corresponding bits in the first operation result data and the inverted data that have the same value. Taking the 0th bit to the 4th bit from right to left as an example, it can be determined that the value of the 0th bit in the first operation result data and the value of the 0th bit in the inverted data are the same, which means that the value of the 0th bit in the first operation result data may be wrong, or the value of the 0th bit in the inverted data may be wrong.

[0091] In this case, the number of 1s in the first operation result data and the reference number can be compared according to method C2. The number of 1s in the first operation result data is 3, while the reference number is 4. If the number of 1s in the first operation result data is different from the reference number, it is considered that the first operation result data is erroneous. Further, the number of 0s in the inverted data and the reference number can be compared according to method C3. If the number of 0s in the inverted data is 4, which is the same as the reference number, it can be determined that there is no error in the inverted data, and the inverted data can be inverted to obtain 11011, which is the third data.

[0092] Optionally, when storing the reference quantity, a binary representation of the reference quantity may be stored, for example, if the reference quantity is 4, 0100 may be stored. Alternatively, a reference quantity of zeros may be stored to avoid an error in the reference quantity, for example, 4 zeros may be stored to indicate that the reference quantity is 4.

[0093] According to the above-mentioned methods, even if multiple bits of data in the first data or the second data are changed, third data that is the same as or more similar to the original data can be determined, thereby improving the accuracy of the read data.

[0094] See also Fig.11 , shows a schematic diagram of the structure of a memory provided in an embodiment of the present application, wherein first data and second data are respectively stored at different positions in a storage module 11, and when third data needs to be read, the output module 12 can process the first data and the second data to obtain the third data.

[0095] Further, see Fig.12, showing a schematic diagram of the structure of another memory provided by an embodiment of the present application. The storage module 11 performs write control on the input original data, such as copying the original data, calculating the second verification data or generating inverted data based on the original data, and stores the data through the OTP unit 111. When the output module 12 needs to read the third data, it performs read control on the stored data, such as reading the first data and the second data, and can also read the required second verification data and inverted data, etc. Afterwards, the output module 12 can perform error detection on the read data according to methods A to C, and after detecting the error, perform error correction, determine the accurate third data and output it.

[0096] To summarize, in the embodiment of the present application, two copies of data that are identical to the original data are redundantly stored. Even if the two copies of the stored data may change after storage to generate first data and second data, by performing logical operations on the first data and the second data, first operation result data that is more accurate than the first data and the second data can be obtained, thereby enabling more accurate third data to be output based on the first operation result data.

[0097] Especially for non-volatile memory or storage system based on OTP implementation, when the memory or storage system is powered on and started, the value stored in the OTP unit is read to initialize the settings and operations. The data stored in the OTP unit may be damaged due to various reasons. However, if the critical data is damaged and there is no way to recover it, incorrect data will be read, and the memory or storage system may not work. Therefore, the memory provided by the embodiment of the present application can improve the accuracy and integrity of the read data, maintain the normal operation of the memory or the storage system equipped with the memory, and improve the stability of the system.

[0098] Furthermore, the chip or component of the memory provided by the embodiment of the present application can reduce the possibility of replacing the chip or the entire component, thereby extending the service life of the product to reduce the warranty cost and reduce the overall unit price of the product. In addition, the memory provided by the embodiment of the present application may have a smaller logical size than the memory based on ECC implementation provided by the related art, which can save generation resources.

[0099] In an exemplary embodiment, a data storage method is also provided, which includes but is not limited to the following: Fig.13 S1301 to S1303 are shown.

[0100] S1301, redundantly store original data to obtain first data and second data.

[0101] In a possible implementation manner, the method is applied to a memory, the memory includes a one-time programmable unit, and the first data and the second data are stored through the one-time programmable unit.

[0102] S1302, performing a logical operation on the first data and the second data to obtain first operation result data.

[0103] Optionally, the logical operation comprises an OR operation.

[0104] S1303, output third data based on the first operation result data.

[0105] In a possible implementation, outputting third data based on first operation result data includes: determining the first operation result data as the third data; and outputting the third data.

[0106] In another possible implementation, outputting third data based on first operation result data includes: generating first verification data according to the first operation result data and verification data generation rules; determining third data according to a first comparison result of the first verification data and the second verification data, the second verification data being generated according to the verification data generation rules and the original data; and outputting third data.

[0107] For example, determining the third data according to a first comparison result of the first verification data and the second verification data includes: when the first comparison result indicates that the first verification data and the second verification data are the same, determining the first operation result data as the third data.

[0108] For another example, determining third data based on a first comparison result of first verification data and second verification data includes: when the first comparison result indicates that the first verification data and the second verification data are different, restoring the first operation result data according to the verification data generation rule, the first verification data, and the second verification data to obtain the third data.

[0109] In another possible implementation, the third data is output based on the first operation result data, including: performing an XOR operation on the first operation result data and the inverted data to obtain the second operation result data, the inverted data is obtained by inverting the original data; and outputting the third data based on the second operation result data.

[0110] In this way, the third data is output according to the second operation result data, including: when the second operation result data indicates that the values ​​of each group of corresponding bits in the first operation result data and the inverted data are different, the first operation result data is determined as the third data; and the third data is output.

[0111] Alternatively, when the second operation result data indicates that the values ​​of at least one group of corresponding bits in the first operation result data and the inverted data are the same and the number of bits whose values ​​are the first value in the first operation result data is the same as the reference number, the first operation result data may be determined as the third data; and the third data may be output. The reference number is the number of bits whose values ​​are the first value in the original data.

[0112] Alternatively, when the second operation result data indicates that the values ​​of at least one group of corresponding bits in the first operation result data and the inverted data are the same and the number of bits in the inverted data whose values ​​are the second value is the same as the reference number, the inverted data is inverted to obtain third data; and the third data is output. The reference number is the number of bits whose values ​​are the first value in the original data, and the second value is opposite to the first value.

[0113] Regarding the implementation process and beneficial effects of the data storage method provided in the embodiment of the present application, reference can be made to the description of the memory embodiment described above, which will not be repeated here.

[0114] In an exemplary embodiment, a chip is also provided, which includes any possible memory described above.

[0115] In an exemplary embodiment, an electronic device is further provided, which includes any possible memory described above.

[0116] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.) and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant laws, regulations and standards of relevant countries and regions. For example, the data involved in this application are all obtained with full authorization.

[0117] It should be understood that the "plurality" mentioned in this article refers to two or more. "And / or" describes the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0118] The above description is only an exemplary embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A memory, characterized in that: The memory includes a storage module and an output module; The storage module is used to perform redundant storage on the original data to obtain the first data and the second data; The output module is used to perform a logic operation on the first data and the second data to obtain first operation result data; Based on the first operation result data, third data is output.

2. The memory according to claim 1, characterized in that: The output module is used to generate first verification data according to the first operation result data and verification data generation rules; determine the third data according to a first comparison result of the first verification data and the second verification data, and the second verification data is generated according to the verification data generation rules and the original data.

3. The memory according to claim 2, characterized in that: the output module is configured to determine the first operation result data as the third data when the first comparison result indicates that the first verification data and the second verification data are the same; Alternatively, when the first comparison result indicates that the first verification data and the second verification data are different, the third data is restored according to the verification data generation rule, the first verification data, the second verification data and the first operation result data.

4. The memory according to claim 1, characterized in that: The output module is used to perform an XOR operation on the first operation result data and the inverted data to obtain the second operation result data, wherein the inverted data is obtained by inverting the original data; and determine the third data according to the second operation result data.

5. The memory according to claim 4, characterized in that: The output module is used to determine the first operation result data as the third data when the second operation result data indicates that the values ​​of each group of corresponding bits in the first operation result data and the inverted data are different.

6. The memory according to claim 4, characterized in that: The output module is configured to determine the first operation result data as the third data when the second operation result data indicates that the values ​​of at least one group of corresponding bits in the first operation result data and the inverted data are the same and the number of bits whose values ​​are the first value in the first operation result data is the same as a reference number, wherein the reference number is the number of bits whose values ​​are the first value in the original data; Alternatively, when the second operation result data indicates the value of at least one group of corresponding bits in the first operation result data and the inverted data and the number of bits in the inverted data whose value is the second value is the same as the reference number, the inverted data is inverted to obtain the third data, and the second value is opposite to the first value.

7. The memory according to claim 1, characterized in that: The output module is used to determine the first operation result data as the third data.

8. The memory according to any one of claims 1 to 7, characterized in that: The logical operation includes an OR operation.

9. The memory according to any one of claims 1 to 8, characterized in that: The storage module includes a one-time programmable unit, and the one-time programmable unit is used to store the first data and the second data.

10. A data storage method, characterized in that: The method comprises: Redundantly storing the original data to obtain first data and second data; Performing a logical operation on the first data and the second data to obtain first operation result data; Based on the first operation result data, third data is output.

11. The method according to claim 10, characterized in that The step of outputting the third data based on the first operation result data comprises: Performing an XOR operation on the first operation result data and the inverted data to obtain second operation result data, wherein the inverted data is obtained by inverting the original data; The third data is output according to the second operation result data.

12. The method according to claim 11, characterized in that Outputting the third data according to the second operation result data includes: When the second operation result data indicates that the values ​​of the respective groups of corresponding bits in the first operation result data and the inverted data are different, determining the first operation result data as the third data; The third data is output.

13. The method according to claim 11, characterized in that Outputting the third data according to the second operation result data includes: In a case where the second operation result data indicates that the values ​​of at least one group of corresponding bits in the first operation result data and the inverted data are the same and the number of bits whose values ​​are the first value in the first operation result data is the same as a reference number, determining the first operation result data as the third data, the reference number being the number of bits whose values ​​are the first value in the original data; Alternatively, when the second operation result data indicates that the values ​​of at least one group of corresponding bits in the first operation result data and the inverted data are the same and the number of bits in the inverted data whose values ​​are the second value is the same as the reference number, the inverted data is negated to obtain the third data, the reference number is the number of bits in the original data whose values ​​are the first value, and the second value is opposite to the first value; The third data is output.

14. The method according to claim 10, characterized in that The step of outputting the third data based on the first operation result data comprises: Determine the first operation result data as the third data; The third data is output.

15. A chip, characterized in that: The chip includes the memory as described in any one of claims 1-9.

16. An electronic device, characterized in that: The electronic device comprises the memory as described in any one of claims 1-9.

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