Chip inductor

Abstract

The invention belongs to the technical field of electronic devices, and discloses a chip inductor. The chip inductor comprises a leading-out end layer and an inner electrode. A first conductor electrically connected with the outer electrode is arranged on the surface of the leading-out end layer; the inner electrode comprises a plurality of inductance layers stacked in sequence, leading-out end layers are arranged at the two ends of the inner electrode respectively, second conductors used for forming induction coils are arranged on the surfaces of the inductance layers, third conductors are further arranged on the surfaces of the inductance layers located at the two ends of the inner electrode, and one ends of the third conductors are connected with the second conductors. The other end of the third conductor is connected with the first conductor. According to the induction coil, the third conductor is directly formed on the inductance layer at the two ends of the inner electrode, the magnetic circuit length of the induction coil can be shortened, and the quality factor (namely the Q value) is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic components, and in particular to a chip inductor. Background Art

[0002] Chip inductors, also known as surface mount inductors, are a new generation of leadless or short-lead miniature electronic components suitable for surface mount technology.

[0003] Chip inductors have the advantages of small size and are conducive to miniaturization of circuits, and can meet the structural requirements of miniaturization and integration of electronic products.

[0004] Please see attached Figure 1 A chip inductor is provided in the prior art, which includes an existing lead-out terminal layer 100, the existing lead-out terminal layer 100 is used to connect and conduct with the external electrode, and the existing lead-out terminal layer 100 is electrically connected to the end of the existing internal electrode 300 through the connecting layer 200. Since two connecting layers 200 are distributed at both ends of the existing internal electrode 300 and the two connecting layers 200 are independently layered, the magnetic circuit formed by the existing chip inductor is relatively long, which is not conducive to improving the quality factor (i.e., Q value) of the entire chip inductor. Summary of the invention

[0005] The object of the present invention is to provide a chip inductor for reducing the length of a magnetic circuit and improving the high quality factor (ie, Q value) of the entire chip inductor.

[0006] To achieve this object, the present invention adopts the following technical solutions:

[0007] A chip inductor, comprising:

[0008] A lead-out terminal layer, a surface of which is provided with a first conductor electrically connected to the external electrode;

[0009] The inner electrode comprises a plurality of inductor layers stacked in sequence, the lead-out terminal layers are respectively provided at both ends of the inner electrode, a second conductor for forming an induction coil is provided on the surface of the inductor layer, and a third conductor is also provided on the surface of the inductor layer at both ends of the inner electrode, one end of the third conductor is connected to the second conductor, and the other end of the third conductor is connected to the first conductor.

[0010] As an optional solution of a chip inductor, one end of the third conductor is connected to the end of the second conductor.

[0011] As an optional solution of the chip inductor, one end of the third conductor is connected to the middle structure of the second conductor.

[0012] As an optional solution of a chip inductor, the chip inductor further includes a lead layer, wherein the lead layer is provided between the lead terminal layer and the inner electrode, and the first conductor is connected to the third conductor via a fourth conductor located in the lead layer.

[0013] As an optional solution for the chip inductor, the lead layer is provided with a lead hole penetrating the lead layer, and the fourth conductor is located in the lead hole.

[0014] As an optional solution for a chip inductor, before the chip inductor is formed, a plurality of lead layers are stacked in sequence.

[0015] As an optional solution of the chip inductor, the chip inductor further includes a substrate layer, and the substrate layer is stacked on a side of the lead-out layer away from the inner electrode.

[0016] As an optional solution for a chip inductor, before the chip inductor is formed, a plurality of substrate layers are stacked in sequence.

[0017] As an optional solution for a chip inductor, the length of the second conductor is 1 / 2 of the length of a single turn of the induction coil.

[0018] As an optional solution for a chip inductor, the length of the second conductor is ¾ of the length of a single turn of the induction coil.

[0019] Beneficial effects:

[0020] In the present invention, by directly forming the third conductor on the inductor layer at both ends of the inner electrode, the connection layer used to connect the lead-out layer and the inner electrode in the prior art can be directly eliminated without changing other structural parameters, thereby shortening the magnetic path length of the chip inductor and improving the Q value. Specifically, the shorter magnetic path length can shorten the magnetic flux path and reduce energy loss. The reduced energy loss can enable the chip inductor to store and release energy more effectively, thereby improving the Q value. In addition, the shortening of the magnetic path length also helps to increase the magnetic flux density, thereby improving the inductance value and improving the Q value. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a schematic diagram of the exploded structure of a chip inductor provided by the prior art;

[0022] Figure 2 It is a schematic diagram of an exploded structure of a chip inductor provided in an embodiment of the present invention.

[0023] In the figure:

[0024] 100, existing lead-out terminal layer; 200, connection layer; 300, existing internal electrode;

[0025] 1. Lead-out layer; 11. First conductor; 2. Inner electrode; 21. Inductor layer; 211. Second conductor; 212. Third conductor; 3. Lead layer; 31. Fourth conductor; 4. Substrate layer. DETAILED DESCRIPTION

[0026] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0027] In the description of the present invention, unless otherwise clearly specified and limited, the terms "connected", "connected", and "fixed" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0028] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0029] In the description of this embodiment, the terms "upper", "lower", "right", etc., directions or positional relationships are based on the directions or positional relationships shown in the drawings, and are only for the convenience of description and simplification of operation, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are only used to distinguish in the description and have no special meaning.

[0030] Please see attached Figure 2This embodiment relates to a chip inductor, which includes a lead-out layer 1 and an inner electrode 2. The lead-out layer 1 has a first conductor 11 electrically connected to the outer electrode on its surface; the inner electrode 2 includes a plurality of sequentially stacked inductor layers 21, the two ends of the inner electrode 2 are provided with lead-out layers 1, the surface of the inductor layer 21 is provided with a second conductor 211 for forming an induction coil, and the surfaces of the inductor layers 21 at the two ends of the inner electrode 2 are also provided with a third conductor 212, one end of the third conductor 212 is connected to the second conductor 211, and the other end of the third conductor 212 is connected to the first conductor 11.

[0031] Specifically, the lead-out layer 1 is used to connect the inner electrode 2 and the outer electrode so that the chip inductor can be connected to the external circuit. The chip inductor can be easily connected to the electronic system through the lead-out layer 1 to realize signal transmission and processing. The substrate of the lead-out layer 1 is made of ceramic material, and specifically ferrite ceramics can be used. Ferrite ceramics have good magnetic and electrical properties, which can meet the processing requirements of the chip inductor for high-frequency signals. At the same time, ferrite ceramics also have high mechanical strength and heat resistance, which can ensure the stability and reliability of the chip inductor during long-term use. In some embodiments, silver paste can be coated on the substrate surface of the lead-out layer 1, and a first conductor 11 with good conductivity can be formed by a sintering and curing process. The shape of the substrate is rectangular, and the first conductor 11 is in the shape of a long strip after molding. The first conductor 11 extends from the center of the substrate toward one of the top corners of the substrate. The structure of the first conductor 11 exposed on the outer side wall at the top corner can be connected to the external electrode.

[0032] The material of the second conductor 211 used to form the induction coil can be a metal with high conductivity. For example, the material can be copper or silver. The second conductor 211 can also be formed on the surface of the inductor layer 21 by a powder sintering process. Multiple inductor layers 21 are stacked in sequence so that the multiple layers of second conductors 211 are connected in sequence to form an induction coil with a surrounding structure. At the same time, a third conductor 212 is also formed on the inductor layer 21 at both ends of the inner electrode 2 by a powder sintering process. One end of the third conductor 212 is connected to the second conductor 211, and the other end is electrically connected to the first conductor 11 on the adjacent lead-out terminal layer 1.

[0033] In this embodiment, by directly forming the third conductor 212 on the inductor layer 21 at both ends of the inner electrode 2, the connection layer used to connect the lead-out layer 1 and the inner electrode 2 in the prior art can be directly eliminated without changing other structural parameters, thereby shortening the magnetic path length of the induction coil and improving the quality factor (i.e., Q value). Specifically, a shorter magnetic path length can shorten the magnetic flux path and reduce energy loss. The reduced energy loss can enable the chip inductor to store and release energy more effectively, thereby improving the Q value. In addition, the shortening of the magnetic path length also helps to increase the magnetic flux density, thereby improving the inductance value and the Q value.

[0034] In this embodiment, the length of the second conductor 211 is 3 / 4 of the length of a single turn of the induction coil, and the second conductor 211 forms a U-shaped structure after sintering on the surface of the inductor layer 21. Of course, in other embodiments, according to design requirements, the length of the second conductor 211 can also be 1 / 2 of the length of a single turn of the induction coil, so that the second conductor 211 forms an L-shaped structure after sintering on the surface of the inductor layer 21. Those skilled in the art can understand that the structure of the chip inductor provided in this application can adapt to various winding forms of the induction coil of the inner electrode 2, thereby improving adaptability.

[0035] In some embodiments, one end of the third conductor 212 is connected to a terminal end of the second conductor 211 .

[0036] Please continue to refer to the attached Figure 2 The third conductor 212 is a strip-shaped silver-coated layer printed on the inductor layer 21 at both ends of the inner electrode 2. One end of the third conductor 212 is connected to the end of the second conductor 211 of the inductor layer 21 and extends toward the center of the inductor layer 21. Correspondingly, a through hole is opened in the center of the lead-out terminal layer 1, and the third conductor 212 can be connected to the first conductor 11 on the lead-out terminal layer 1 at the through hole.

[0037] By connecting one end of the third conductor 212 to the end of the second conductor 211 , the silver coating operation can be performed along a single planned path during the molding process, thereby improving the processability.

[0038] In some embodiments, one end of the third conductor 212 is connected to the middle structure of the second conductor 211 .

[0039] One end of the third conductor 212 can also be directly connected to the middle structure of the second conductor 211 instead of the end point, that is, any position in the middle of the second conductor 211 can be connected to the end of the third conductor 212 and extend toward the center of the inductor layer 21 .

[0040] One end of the third conductor 212 is connected to the middle structure of the second conductor 211 at any position, which shortens the length of the third conductor 212 to a certain extent, reduces the silver coating material, and reduces the cost.

[0041] In this embodiment, the chip inductor further includes a lead layer 3 , which is disposed between the lead terminal layer 1 and the internal electrode 2 , and the first conductor 11 is connected to one end of the third conductor 212 via a fourth conductor 31 located in the lead layer 3 .

[0042] Specifically, the lead layer 3 is sandwiched between the lead-out layer 1 and the inner electrode 2, and the relative position of the lead-out layer 1 can be adjusted through the lead layer 3. For example, when the number of turns of the inner electrode 2 is small, the length of the entire inner electrode 2 is relatively small. By adding the lead layer 3 between the lead-out layer 1 and the inner electrode 2 to adjust the relative position between the lead-out layer 1 and the outer electrode, the lead-out layer 1 on both sides of the inner electrode 2 can adapt to the position of the outer electrode, thereby ensuring the stability and convenience of the connection. On the other hand, the introduction of the lead layer 3 can also make the product length of the overall chip inductor meet the design requirements.

[0043] In some embodiments, a lead hole penetrating the lead layer 3 is provided on the lead layer 3 , and the fourth conductor 31 is located in the lead hole.

[0044] In this embodiment, the lead hole is a circular hole, and the two sides of the lead hole are respectively opposite to the center of the lead-out layer 1 and the center of the inductor layer 21 at the end of the inner electrode 2. The fourth conductor 31 is placed inside the lead hole after solidification, so that the two ends of the fourth conductor 31 can be connected to the first conductor 11 and the third conductor 212 respectively, so as to realize the electrical connection between the inner electrode 2 and the lead-out layer 1. Of course, those skilled in the art can understand that the position of the lead hole is not limited to the center of the lead layer 3, but is determined according to the connection position of the ends of the first conductor 11 and the third conductor 212, and the specific size parameters of the lead hole can be selected or adjusted according to the processability and conductivity of the connection, and this application does not make specific limitations.

[0045] In some implementations, before the chip inductor is formed, a plurality of lead layers 3 are stacked in sequence.

[0046] Before the entire chip inductor is sintered and solidified, the lead layer 3 can be set to be multiple layers, that is, the number of layers is ≥ 2. Multiple lead layers 3 can conveniently adjust the relative position of the lead end layer 1 and the product length of the chip inductor. Exemplarily, the lead layer 3 is a double-layer stacked arrangement structure. After the product is sintered and solidified, the multiple lead layers 3 form an integrated structure.

[0047] Adaptively, the lead holes of the lead layer 3 are arranged in sequence along the stacking direction of the lead layer 3, and at the same time, the fourth conductors 31 inside the lead holes are electrically connected in sequence, and the fourth conductors 31 located on the two outermost lead layers 3 are connected to the first conductor 11 and the third conductor 212 respectively.

[0048] In some embodiments, the chip inductor further includes a substrate layer 4 , which is stacked on a side of the lead-out terminal layer 1 away from the internal electrode 2 .

[0049] Specifically, the substrate layer 4 is stacked and arranged at the outermost side of the chip inductor. The substrate layer 4 can provide stable support for other parts, ensure the stability and reliability of the chip inductor in the circuit, and prevent structural damage or performance degradation caused by external factors (such as impact factors and / or vibration factors) and erosion by external environmental factors. When the chip inductor is working, a certain amount of heat is usually generated. The substrate layer 4 helps to dissipate this part of the heat to prevent the chip inductor from being damaged due to overheating.

[0050] In some implementations, before the chip inductor is formed, a plurality of substrate layers 4 are stacked in sequence.

[0051] Before the entire chip inductor is sintered and solidified, the substrate layer 4 can be set to be multiple layers, that is, the number of layers is ≥ 2. After the product is sintered and solidified, multiple substrate layers 4 form an integrated structure. By setting multiple stacked substrate layers 4, the product length of the chip inductor can be made to meet the design requirements, that is, the actual product length of the chip inductor is usually determined. When the number of coils of the inner electrode 2 is small, the length of the inner electrode 2 is small. Therefore, by stacking multiple substrate layers 4, the product length of the chip inductor can meet the design requirements. In this embodiment, two layers of substrate layers 4 are stacked at both ends of the chip inductor. Of course, in other embodiments, the product length of the overall chip inductor can be made to meet specific design requirements by adjusting the number of substrate layers 4. This embodiment does not specifically limit the number of substrate layers 4.

[0052] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. For those skilled in the art, various obvious changes, readjustments and substitutions can be made without departing from the protection scope of the present invention. It is not necessary and impossible to list all the embodiments here. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the claims of the present invention.

Claims

1. A chip inductor, characterized in that: include: A lead-out terminal layer (1), wherein a first conductor (11) electrically connected to an external electrode is provided on a surface of the lead-out terminal layer (1); An inner electrode (2) comprises a plurality of inductor layers (21) stacked in sequence, the lead-out terminal layers (1) being respectively provided at both ends of the inner electrode (2), a second conductor (211) for forming an induction coil being provided on the surface of the inductor layer (21), and a third conductor (212) being further provided on the surface of the inductor layer (21) at both ends of the inner electrode (2), one end of the third conductor (212) being connected to the second conductor (211), and the other end of the third conductor (212) being connected to the first conductor (11).

2. The chip inductor according to claim 1, characterized in that: One end of the third conductor (212) is connected to the end of the second conductor (211).

3. The chip inductor according to claim 1, characterized in that: One end of the third conductor (212) is connected to the middle structure of the second conductor (211).

4. The chip inductor according to claim 1, characterized in that: The chip inductor further comprises a lead layer (3), wherein the lead layer (3) is arranged between the lead terminal layer (1) and the inner electrode (2), and the first conductor (11) is connected to the third conductor (212) via a fourth conductor (31) located in the lead layer (3).

5. The chip inductor according to claim 4, characterized in that: The lead layer (3) is provided with a lead hole penetrating the lead layer (3), and the fourth conductor (31) is located in the lead hole.

6. The chip inductor according to claim 4, characterized in that: Before the chip inductor is formed, a plurality of lead layers (3) are stacked in sequence.

7. The chip inductor according to claim 1, characterized in that: The chip inductor further comprises a substrate layer (4), wherein the substrate layer (4) is stacked on a side of the lead-out terminal layer (1) away from the internal electrode (2).

8. The chip inductor according to claim 7, characterized in that: Before the chip inductor is formed, a plurality of substrate layers (4) are stacked in sequence.

9. The chip inductor according to any one of claims 1 to 8, characterized in that: The length of the second conductor (211) is 1 / 2 of the length of a single turn of the induction coil.

10. The chip inductor according to any one of claims 1 to 8, characterized in that: The length of the second conductor (211) is 3 / 4 of the length of a single turn of the induction coil.

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