Semiconductor package structure and method of forming semiconductor package

Abstract

A method of forming a semiconductor package includes forming a first integrated circuit on a front side of a semiconductor substrate of a first device die, forming a trench capacitor extending into the semiconductor substrate from a back side of the semiconductor substrate, and forming a first through-via and a second through-via penetrating the semiconductor substrate. The trench capacitor is electrically coupled between the first through-via and the second through-via. A second device die is bonded to the first die. The second device die includes a second integrated circuit, and a power supply node of the second integrated circuit is electrically coupled to the first through-via and the second through-via. The embodiment of the invention also discloses a semiconductor packaging structure.

Description

Technical Field

[0001] Embodiments of the present application relate to a semiconductor package structure and a method of forming a semiconductor package. Background Art

[0002] The packaging of integrated circuits is becoming more and more complex, integrating more device dies in the same package to achieve more functions. For example, multiple device dies (such as processors and memory cubes) can be joined and integrated together. A package can include device dies formed using different technologies and having different functions to form a system. This can save manufacturing costs and optimize device performance. Summary of the invention

[0003] According to one aspect of an embodiment of the present application, a method for forming a semiconductor package is provided, comprising: forming a first integrated circuit on the front side of a semiconductor substrate of a first device die; forming a trench capacitor extending from the back side of the semiconductor substrate into the semiconductor substrate; forming a first through hole and a second through hole penetrating the semiconductor substrate, wherein the trench capacitor is electrically coupled between the first through hole and the second through hole; and joining a second device die to the first device die, wherein the second device die includes a second integrated circuit, and wherein a power supply node of the second integrated circuit is electrically coupled to the first through hole and the second through hole.

[0004] According to another aspect of an embodiment of the present application, a semiconductor packaging structure is provided, comprising: a first device die, the first device die comprising: a semiconductor substrate; a first integrated circuit, located at the bottom surface of the semiconductor substrate; a first through hole and a second through hole, penetrating the semiconductor substrate; and a trench capacitor, extending from the top surface of the semiconductor substrate into the semiconductor substrate, wherein the trench capacitor is electrically coupled to the first through hole and the second through hole; and a second device die, located above the first device die and bonded to the first device die, wherein the second device die comprises a second integrated circuit, and a power node of the second integrated circuit is connected to at least one of the first through hole and the second through hole.

[0005] According to another aspect of an embodiment of the present application, a semiconductor packaging structure is provided, comprising: a first device die, the first device die comprising: a semiconductor substrate; a first integrated circuit, close to the bottom surface of the semiconductor substrate; and a trench capacitor, wherein a first portion of the first integrated circuit and a first portion of the trench capacitor are located on opposite sides of the semiconductor substrate, and wherein a second portion of the first integrated circuit and a second portion of the trench capacitor are located in the semiconductor substrate; and a second device die, located above the first device die and bonded to the first device die, wherein the second device die comprises a second integrated circuit electrically coupled to the trench capacitor. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, the size of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figure 1-Figure 13 A cross-sectional view of an intermediate stage in the formation of a package including a deep trench capacitor formed using a TSV-first approach is shown in accordance with some embodiments.

[0008] Figure 14-16 A cross-sectional view of an intermediate stage in the formation of a package including a deep trench capacitor formed using a TSV last approach is shown in accordance with some embodiments.

[0009] Fig.17 and Fig.18 A top view of a deep trench capacitor is shown in accordance with some embodiments.

[0010] Fig.19 and Fig. 20 Cross-sectional views of TSVs and corresponding deep trench capacitors formed using a TSV-first process and a TSV-last process, respectively, are shown in accordance with some embodiments.

[0011] Figure 21-23 Shown are top view shapes of some deep trenches of a deep trench capacitor according to some embodiments.

[0012] Fig.24 A process flow for forming a package according to some embodiments is shown. DETAILED DESCRIPTION

[0013] The following disclosure provides many different embodiments or examples for realizing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0014] Additionally, for ease of description, spacing relation terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or in the process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein may likewise be interpreted accordingly.

[0015] A package including a deep trench capacitor as a decoupling capacitor and a method for forming the same are provided. According to some embodiments of the present disclosure, a top die is bonded to a bottom die. A deep trench capacitor is formed in the bottom die for regulating the power supply of the top die. The deep trench capacitor can be formed to extend from the back side of the semiconductor substrate of the bottom die into the semiconductor substrate, thereby using the chip area not used by the bottom die and saving the chip area of ​​both the top die and the bottom die.

[0016] The embodiments discussed herein are intended to provide examples to enable making or using the subject matter of the present disclosure, and those of ordinary skill in the art will readily appreciate the modifications that may be made while remaining within the intended scope of the different embodiments. In the various views and illustrative embodiments, the same reference numerals are used to represent the same elements. Although the method embodiments may be discussed as being performed in a particular order, other method embodiments may also be performed in any logical order.

[0017] Figures 1 to 13 1 shows a cross-sectional view of an intermediate stage in the process of forming a package according to some embodiments of the present disclosure. The corresponding process is also schematically reflected in Fig.24 The process flow shown.

[0018] Figure 1 A device die 10 is shown in accordance with some embodiments. The device die 10 includes a substrate 12. According to some embodiments, the substrate 12 is a semiconductor substrate, which may include or may be a crystalline silicon substrate, while it may also include or be formed of other semiconductor materials, such as silicon germanium, carbon-doped silicon, etc. According to some embodiments, the device die 10 includes an integrated circuit 14, which includes active devices, such as transistors (not shown), formed at the top surface of the semiconductor substrate 12. The device die 10 is formed as part of a wafer, which is divided to form a plurality of identical device dies 10.

[0019] According to some embodiments, through-holes (sometimes referred to as through-substrate vias (TSVs)) 16 are formed to extend into substrate 12. When formed in a silicon substrate, TSVs 16 are sometimes also referred to as through-silicon vias. TSVs 16 include TSVs 16A and TSVs 16B for conducting power supplies such as VDD and VSS (electrical ground). Signal TSVs 16, not shown, may also be present.

[0020] Each TSV 16 may be separated by a dielectric isolation liner 112 (eg, Fig.19 and Fig. 20 The TSV 16 and the corresponding dielectric isolation liner 112 are formed of a dielectric material such as silicon oxide or silicon nitride. Fig.19 and Fig. 20 The dielectric isolation liner 112 electrically and physically insulates each TSV 16 from the semiconductor substrate 12. The TSV 16 and the dielectric isolation liner 112 may extend from the top surface of the semiconductor substrate 12 to an intermediate level between the top surface and the bottom surface of the semiconductor substrate 12.

[0021] According to some embodiments, the top surface of TSV 16 is shown flush with the top surface of semiconductor substrate 12. According to alternative embodiments, TSV 16 extends into one of dielectric layers 22 and extends from the top surface of the corresponding dielectric layer 22 into semiconductor substrate 12.

[0022] Interconnect structure 20 is formed on the front side of semiconductor substrate 12. Interconnect structure 20 may include a plurality of dielectric layers 22 and conductive features 24 in dielectric layers 22. Conductive features 24 including metal lines / pads and vias may be electrically connected to TSVs 16 and integrated circuits 14.

[0023] According to some embodiments, the dielectric layer 22 is formed of silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, combinations thereof and / or multilayers thereof. The dielectric layer 22 may include one or more intermetallic dielectric (IMD) layers formed of a low-k dielectric material having a low dielectric constant (k value), which may be, for example, less than about 3.5, or in a range between about 2.5 and about 3.5. The dielectric layer 22 may also include a passivation layer, which may be formed of a non-low-k dielectric material, such as an oxide, a nitride, a combination thereof and / or a combination thereof. Some dielectric layers 22 on the front side of the device die 10 may also include or be formed of a polymer, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc.

[0024] Conductive feature 24 may be formed in the low-k dielectric layer. According to some embodiments, conductive feature 24 may be formed using a damascene process. There may be some metal pads (eg, aluminum-copper pads) above the low-k dielectric layer and in the passivation layer and / or non-low-k dielectric layer.

[0025] Metal pad 30 is formed near the top surface of device die 10, and surface dielectric layer 22 covers metal pad 30. According to some embodiments, surface dielectric layer 22 includes a silicon-containing dielectric material, such as SiO, SiC, SiN, SiOCN, SiCN, SiON, etc.

[0026] According to some embodiments, the electrical connector 30 includes a solder area, a metal pillar, a metal pad, a metal bump (sometimes referred to as a microbump), etc. The material of the electrical connector 30 may include a non-solder material, which may be formed of or include copper, nickel, aluminum, gold, multiple layers thereof, alloys thereof, etc. The electrical connector 30 may be electrically connected to the integrated circuit 14.

[0027] Throughout the description, the side of the semiconductor substrate 12 having the active circuit 14 and the interconnect structure 20 is referred to as the front side (or active side) of the semiconductor substrate 12, and the opposite side is referred to as the back side (or inactive side). In addition, the front side of the semiconductor substrate 12 is referred to as the front side (or active side) of the device die 10, and the back side of the semiconductor substrate 12 is also referred to as the back side (or inactive side) of the device die 10.

[0028] refer to Figure 2 , device die 10 is inverted and attached to carrier 32 and layer 34. Fig.24 As shown, in process 200, the corresponding process is shown as process 202. According to some embodiments, carrier 32 may be a glass carrier, a silicon wafer, an organic carrier, etc. According to some embodiments, carrier 32 may have a circular top view shape. Layer 34 may be a release film formed of a polymer-based material and / or an epoxy-based thermal release material (e.g., a light-to-heat conversion (LTHC) material), which can be decomposed under radiation such as a laser beam, so that carrier 32 can be peeled off from the overlying structure. According to some embodiments of the present disclosure, layer 34 as a release film is applied to carrier 32 by coating.

[0029] According to alternative embodiments, carrier 32 includes a silicon substrate and layer 34 is a bonding layer, which may include a silicon-containing dielectric material, such as SiO, SiC, SiN, SiOCN, SiCN, SiON, etc. According to these embodiments, device die 10 may be bonded to bonding layer 34 by fusion bonding.

[0030] Although one device die 10 is shown, there may be multiple device dies 10 attached to the underlying carrier 32. Furthermore, according to alternative embodiments, wafer-to-wafer attachment (or bonding) may be performed rather than attaching discrete device dies 10 to the carrier 32, and the device dies 10 may be located in an unsawn device wafer that is bonded to the carrier 32 via wafer-to-wafer bonding / attachment.

[0031] According to some embodiments, a pre-thinning process is performed from the back side of the device die 10, and the semiconductor substrate 12 is thinned. The pre-thinning process may be performed by a chemical mechanical polishing (CMP) process or a mechanical polishing process. The pre-thinning process is stopped before the TSV 16 is exposed. The pre-thinning process is used to reduce the aspect ratio of the gap between adjacent device dies 10, thereby making the subsequent gap filling process easier.

[0032] Next, if Figure 2 As shown, a gap filling process is performed to fill the gaps between adjacent device dies 10 and encapsulate the device dies 10 in a gap filling layer 38 (also referred to as an encapsulant). Fig.24 As shown, in process 200, the corresponding process is shown as process 204. According to some embodiments, gap filling layer 38 includes dielectric liner 38A and dielectric filling layer 38B on dielectric liner 34A. Dielectric liner 38A can be formed of a material having good adhesion to device die 10. According to some embodiments, dielectric liner 38A is formed of or includes silicon nitride. Dielectric liner 38A is formed by a conformal deposition process and is therefore a conformal layer. Dielectric filling layer 38B can be formed of an oxide-based dielectric material, such as silicon oxide, silicon oxynitride, silicate glass, etc. Dielectric filling layer 38B can be formed by a deposition process.

[0033] According to alternative embodiments, the gap-fill layer 38 is formed of or includes a molding compound, a molding underfill, etc. A corresponding process may include dispensing a dielectric material in a flowable form, and curing the dielectric material.

[0034] refer to Figure 3 After the gap filling layer 38 is deposited, a planarization process is performed to make the top surface of the device die 10 flush with the top surface of the gap filling layer 38. Fig.24 As shown, in flow 200, the corresponding process is shown as process 206. Hereinafter, the remaining portion of gap-fill layer 38 is referred to as gap-fill region 38. According to some embodiments, the planarization process is performed until TSV 16 is exposed.

[0035] Then, the semiconductor substrate 12 in the device die 10 may be recessed so that the top of the TSV 16 protrudes above the semiconductor substrate 12. At the same time, the gap filling region 38 may be recessed or not. Then, the dielectric isolation layer 40 may be filled into the recess, such as Figure 4 As shown. Fig.24As shown, in flow 200, the corresponding process is shown as process 208. The formation of dielectric isolation layer 40 may include performing a deposition process to deposit a dielectric layer into the recess so that the protruding portion of TSV 16 is located in the dielectric layer, and then performing a planarization process. The portion of the dielectric layer above TSV 16 is removed, and the remaining portion of the dielectric layer forms dielectric isolation layer 40, which becomes part of device die 10.

[0036] Reference Figure 5 , forming a deep trench capacitor 42. Fig.24 As shown, in flow 200, the corresponding process is shown as process 210. According to some embodiments, the formation process may include etching dielectric isolation layer 40 and semiconductor substrate 12 from the back side of semiconductor substrate 12 to form one or more trenches 98, and filling the trenches with dielectric layers and conductive layers to form deep trench capacitors 42.

[0037] According to some embodiments, the deep trench capacitor 42 includes multiple sub-layers, including a dielectric isolation layer 42A, a lower (capacitor) electrode 42B on the dielectric isolation layer 42A, a capacitor insulator 42C above the lower capacitor electrode 42B, and an upper (capacitor) electrode 42D above the capacitor insulator 42C. There may also be more capacitor insulators and capacitor electrodes on the upper capacitor electrode 42D, and the capacitor insulators are placed alternately with the capacitor electrodes. According to some embodiments, the dielectric isolation layer 42A can be formed of SiO, SiN, SiC, SiCN, SiOCN, AlO, AlN, etc. The lower electrode 42B and the upper electrode 42D can be formed of a conductive material or multiple conductive layers, such as titanium nitride (TiN), tantalum nitride (TaN), etc. The capacitor insulator 42C can be formed of a high-k dielectric material such as aluminum oxide (Al2O3), zirconium oxide (ZrO2), hafnium oxide (HFO2), etc., or multiple layers thereof or include the above materials.

[0038] Sublayers 42A, 42B, 42C, and 42D may be deposited using physical vapor deposition (PVD), atomic layer deposition (ALD), chemical layer deposition (CVD), and the like. In addition, sublayers 42A, 42B, 42C, and 42D may be deposited as conformal layers. The formation process also includes a plurality of patterning processes to remove the sublayers from undesirable locations. For example, when lower electrode 42B is left in the area directly above TSV 16B, it may be removed from the area directly above TSV 16A. When upper electrode 42D is left in the area directly above TSV 16B, it may be removed from the area directly above TSV 16B.

[0039] refer to Figure 6 , a dielectric layer 46 is formed by deposition to cover the capacitor 42. Fig.24As shown, in flow 200, the corresponding process is shown as process 212. Dielectric layer 46 fills the unfilled trenches of capacitor 42 (if any remain). According to some embodiments, dielectric layer 46 is formed of silicon oxide, silicon nitride, or the like.

[0040] Vias 48 (including vias 48A and 48B) are formed to extend into dielectric layer 46 and penetrate corresponding underlying portions of capacitor 42. Fig.24 As shown, in process 200, the corresponding process is shown as process 214. According to some embodiments, through hole 48A penetrates upper capacitor electrode 42D and is electrically connected to upper capacitor electrode 42D, and is electrically disconnected from lower capacitor electrode 42B. On the other hand, through hole 48B penetrates lower capacitor electrode 42B and is electrically connected to lower capacitor electrode 42B, and is electrically disconnected from upper capacitor electrode 42D. Through holes 48A and 48B are also electrically connected to TSVs 16A and 16B, respectively, and can be in contact with TSVs 16A and 16B, respectively. Therefore, by using through holes 48A and 48B, capacitor 42 is electrically coupled between TSVs 16A and 16B. When power (e.g., VDD and VSS) is conducted through TSVs 16A and 16B, deep trench capacitor 42 can act as a decoupling capacitor to filter out changes in power supply.

[0041] refer to Figure 7 , a bonding layer 50 is deposited on the device die 10 and the gap-filling region 38. The bonding layer 50 may be formed of a silicon-containing dielectric material, which may be selected from SiO, SiC, SiN, SiON, SiOC, SiCN, SiOCN, etc., or a combination thereof.

[0042] Further references Figure 7 , a bonding pad 52 is formed in the bonding layer 50. Fig.24 As shown, in the process 200, the corresponding process is shown as process 216. The bonding layer 50 may include a silicon-containing dielectric material, such as SiO, SiN, SiC, SiON, SiCN, SiOCN, etc. According to some embodiments, the bonding pad 52 is formed by etching the bonding layer 50 to expose the through hole 48, filling the conductive layer into the resulting opening, and performing a planarization process (such as a CMP process or a mechanical polishing process). Therefore, the top surfaces of the bonding pad 52 and the bonding layer 50 are coplanar with each other. The bonding pad 52 may include a material selected from copper, titanium, titanium nitride, tantalum, tantalum nitride, etc. For example, each bonding pad 52 may include a titanium nitride barrier layer and a copper region on the titanium nitride barrier layer.

[0043] refer to Figure 8 , device die 54 (also referred to as top die) is bonded to device die 10. Fig.24As shown, in flow 200, the corresponding process is shown as process 218. Although one device die 54 is shown, the device die 54 shown represents a plurality of device dies 54, each of which is located above and bonded to one of the underlying device dies 10. The bonding may be performed by a face-to-back bonding process, in which the front side of the device die 54 is bonded to the back side of the device die 10. According to some embodiments, each device die 54 may be a logic die, which may be a central processing unit (CPU) die, a microcontroller (MCU) die, an input output (IO) die or a baseband die, a memory die, etc. The device die 54 may also include a memory die.

[0044] The device die 54 may include a semiconductor substrate 56, which may be a silicon substrate. The device die 54 includes an integrated circuit device 58, which may include an active device (e.g., a transistor) or a passive device. An interconnect structure 60 for connecting the active devices and the passive devices in the device die 54 is formed on the front side of the corresponding semiconductor substrate 56. The interconnect structure 60 includes metal lines and vias, as schematically shown.

[0045] Each device die 54 includes a bonding pad 62 and a bonding layer 64 (also referred to as a bonding film) at the bottom surface of the device die 54 shown. The bottom surface of the bonding pad 62 can be coplanar with the bottom surface of the bonding layer 64. According to some embodiments, the bonding layer 64 can be formed of a silicon-containing dielectric material, which can be selected from SiO, SiC, SiN, SiON, SiOC, SiCN, SiOCN, etc. The bonding pad 62 may include copper and may be formed by a damascene process. The bonding layer 64 and the bonding pad 62 are planarized so that their surfaces are coplanar, which may be caused by CMP during the formation of the bonding pad 62.

[0046] The bonding of device die 54 to the underlying structure can be achieved by hybrid bonding. For example, bonding pad 62 is bonded to bonding pad 52 by metal-to-metal direct bonding. According to some embodiments, the metal-to-metal direct bonding is copper-to-copper direct bonding. In addition, bonding layer 64 of device die 54 is bonded to bonding layer 50 by fusion bonding (e.g., by generating Si-O-Si bonds).

[0047] According to some embodiments, Figure 8 As shown, a plurality of dummy dies 66 are also attached to the underlying structure. According to some embodiments, each dummy die 66 is attached by a layer 68. Layer 68 may be a bonding layer including a silicon-containing dielectric material, which may be selected from SiO, SiC, SiN, SiON, SiOC, SiCN, SiOCN, etc., or a combination thereof. According to some embodiments, the entire dummy die 66 is formed of a uniform material, without other materials and structures. The dummy die 66 may be formed of silicon or the above-mentioned silicon-containing dielectric material.

[0048] The attachment may be performed by fusion bonding bonding layer 68 to bonding layer 50. According to these embodiments, the same annealing process may be used to bond dummy die 66 and device die 54 to the underlying structure. Alternatively, layer 68 is an adhesive layer and dummy die 66 is attached to the underlying structure by bonding.

[0049] refer to Fig. 9 , forming a gap filling region 70 (also called a sealant). Fig.24 As shown, in the process 200, the corresponding process is shown as process 220. The formation process, structure and material of the gap filling region 70 can be selected from the candidate formation process, candidate structure and candidate material of the gap filling region 38, respectively. For example, the gap filling region 70 can include a dielectric liner 70A and a dielectric filling layer 70B on the dielectric liner 70A. Alternatively, the gap filling region 70 can include a molding compound, a molding underfill, etc. A planarization process is performed to flatten the top surfaces of the semiconductor substrate 56 of the device die 54, the dummy die 66 and the gap filling region 70.

[0050] Further references Fig. 9 , a bonding layer 72 is deposited on the semiconductor substrate 56 of the device die 54, the dummy die 66, and the gap-filling region 70. The bonding layer 72 may also be formed of or include a silicon-containing dielectric material, which may be selected from SiO, SiC, SiN, SiON, SiOC, SiCN, SiOCN, etc., or a combination thereof. A planarization process may then be performed to flatten the top surface of the bonding layer 72.

[0051] In subsequent processes, such as Fig.10 As shown, the support substrate 74 is bonded to the bonding layer 72. Fig.24 As shown, in process 200, the corresponding process is shown as process 222. The support substrate 74 can be formed of silicon. One or more dielectric layers 78 (including a bonding layer) are formed on the support substrate 74. The bonding layer can be formed of a silicon-containing dielectric material, such as SiO, SiN, SiC, SiON, SiCN, SiOCN, etc. The bonding layer in the dielectric layer 78 can be bonded to the bonding layer 72 by fusion bonding. Alignment marks 80 can also be formed in the dielectric layer 78 and can be formed of a metal material such as copper. For example, a backside metal layer 81 formed of copper, aluminum, nickel, etc. can be formed on the support substrate 74 to improve heat dissipation. Throughout the description, the components on layer 34 are collectively referred to as the reconstructed wafer 100.

[0052] The carrier 32 is then peeled off, and the resulting structure is as follows Fig.11 As shown. Fig.24As shown, in process 200, the corresponding process is shown as process 224. According to some embodiments in which carrier 32 includes a silicon wafer, carrier 32 can be removed by a smart cutting process, which includes injecting carrier 32, for example, using hydrogen to generate a stress concentration layer, and annealing carrier 32, so that carrier 32 can be separated at the stress concentration layer. The remaining portion of carrier 32 can be removed, for example, by etching, CMP process or mechanical grinding process. According to these embodiments, layer 34 ( Fig.10 ) can also be removed.

[0053] According to an alternative embodiment, in which carrier 32 is a glass carrier, reconstituted wafer 100 is debonded from carrier 32 by projecting a laser beam onto layer 34 , which may include LTHC coating material, thereby decomposing the LTHC coating to release from carrier 32 .

[0054] Next, if Fig.11 As shown, the surface dielectric layer 22 (one of the dielectric layers 22 of the device die 10) at the bottom side shown in the device die 10 is etched to expose the metal pad 30. Therefore, an opening is formed in the surface dielectric layer 22 and directly below the metal pad 30. Then a dielectric isolation layer 82 is formed to extend into the opening. The dielectric isolation layer 82 may include silicon oxide, silicon nitride, and may or may not include a polymer layer, such as a polyimide layer.

[0055] An electrical connector may be formed which may include solder region 84 and may or may not include a copper bump formed to extend into the opening to contact metal pad 30. Fig.24 As shown, in flow 200 , the corresponding process is shown as process 226 .

[0056] In subsequent processes, such as Fig.12 As shown, the reconstructed wafer 100 is divided in a sawing process to form individual packages 100'. Fig.24 As shown, in flow 200 , the corresponding process is shown as process 228 . Discrete package 100 ′ includes device dies 10 and 54 , and also includes dummy die 66 and support substrate 74 ′, which are separate parts from support substrate 74 .

[0057] refer to Fig.13 , the package 100' is bonded to the package assembly 88 to form the package 102. Fig.24 As shown, in process 200, the corresponding process is shown as process 230. The packaging component 88 may include a silicon interposer, which includes a silicon substrate and a through hole penetrating the silicon substrate. The silicon interposer does not contain active devices. According to alternative embodiments, the packaging component 88 is or includes an organic interposer, a packaging substrate, a printed circuit board, a package including a device die, etc.

[0058] According to some embodiments, power is conducted from packaging assembly 88 into device die 10 and further to device die 54. Power is conducted to die 10 through TSVs 16, for example, one conducting VSS (electrical ground) and the other conducting VDD. According to some embodiments, there are no decoupling capacitors in device die 54 and capacitor 42 is relied upon to decouple (regulate) power supply fluctuations. The power supplied to device die 54 is regulated by capacitor 42 and not by any other capacitor in device die 10 (e.g., any capacitor formed on the front side of device die 11) or any capacitor in packaging assembly 88.

[0059] According to some embodiments, power is provided to a power supply node 124 (shown schematically) in device die 54 , and integrated circuit 58 in device die 54 is connected to and receives power from power supply node 124 .

[0060] According to some embodiments, power decoupled by capacitor 42 is used by device die 54 but not by device die 10. For example, no circuitry (no integrated circuit 14) in device die 10 is electrically coupled to TSV 16 and capacitor 42. Power used by device die 10 may be regulated, for example, by decoupling capacitors (not shown) in package assembly 88. Alternatively, power used by device die 10 is not regulated by any capacitors in device die 10, 54, and package assembly 88.

[0061] According to an alternative embodiment, the power regulated by capacitor 42 is used by device die 54 and device die 10 . Fig.13 Electrical paths 92 are schematically shown and may include metal lines, contact plugs, etc. that electrically connect TSVs 16 and capacitors 42 to some of the integrated circuit devices 14 in device die 10. Electrical paths 92 are shown as dashed lines to indicate that they may or may not be formed.

[0062] According to some embodiments, package assembly 88 lacks decoupling capacitors for regulating power. According to alternative embodiments, package assembly 88 includes decoupling capacitors (not shown), which may be deep trench capacitors when package assembly 88 includes a silicon substrate, or may be metal-insulator-metal (MIM) capacitors. According to these embodiments, the decoupling capacitors in package assembly 88 regulate the power used by device die 10, but do not regulate the power used by device die 54.

[0063] According to some embodiments, capacitor 42 may overlap with some portion 14B of integrated circuit 14, wherein integrated circuit 14B may extend from the front side of semiconductor substrate 12, and capacitor 42 may extend from the back side of semiconductor substrate 12, and extend toward each other. For example, integrated circuit 14B may include source and drain regions extending into semiconductor substrate 12, and a gate stack below semiconductor substrate 12. Forming decoupling capacitor 42 in device die 10 saves chip area in device die 54, because device die 54 no longer needs to form decoupling capacitors therein. Chip area in device die 10 is also saved, because the (back side) chip area of ​​semiconductor substrate 12 that was not used is now used to form capacitor 42.

[0064] Fig.13 The process shown is a TSV-first process, in which TSV 16 is formed before forming metal lines and vias 24 (this formation process is referred to as a back-end process). According to alternative embodiments, a TSV-last process may be used. For example, Fig.14 , Fig.15 and Fig.16 Some intermediate processes for forming the package 102 using the post-TSV process are shown. Unless otherwise specified, the materials, structures, and formation processes of the components in these embodiments are substantially the same as the same components represented by the same reference numerals in the previous embodiments. Throughout the description, the details of the materials, structures, and formation processes provided in each embodiment can be applied to any other applicable embodiment.

[0065] refer to Fig.14 , the device die 10 is placed on the carrier 32 . Fig.14 The device die 10 shown is Figure 1 and Figure 2 The same as shown, except Fig.14 The device die 10 shown in FIG. has not yet formed TSVs. Next, perform the Figure 2 and Figure 3 The resulting structure is shown in Figure 1. Fig.15 As shown, device die 10 is shown in gap-fill region 38. In addition, an etching process is performed to etch semiconductor substrate 12 and some of dielectric layer 22 to form opening 94. Thus, the bonding pad portion of conductive feature 24 is exposed to opening 94.

[0066] Subsequently, TSV 16 is formed in opening 94 and electrically connected to metal line 24. The formation process may include depositing a conformal dielectric liner ( Fig. 20 112), performing an anisotropic etching process to remove the horizontal portion of the dielectric liner 112, depositing a conductive barrier / adhesion layer 114 ( Fig. 20 ), depositing fill metal 116 ( Fig. 20 ), and performing a planarization process to remove excess portions of the conductive barrier / adhesion layer 114 and the fill metal 116. The rest of the package formation process is similar to Figures 4 to 13 The same as in.

[0067] Fig.17 1 shows a top view of capacitor 42 according to some embodiments. Deep trench region 96 includes one or more deep trenches formed, and lower capacitor electrode 42B extends into the deep trench and further extends laterally so that it can connect to one of vias 48B in vias 48, and further to TSV 16A. Upper capacitor electrode 42D also extends into the deep trench and further extends laterally so that it can connect to one of vias 48A in vias 48, and further to TSV 16A.

[0068] Fig.18 A deep trench 98 is shown in the deep trench region 96 according to some embodiments (see also Figure 5 ). According to some embodiments, as shown on the left, the plurality of deep trenches 98A have a circular top view and can be arranged in an array. According to an alternative embodiment, as shown on the right, the plurality of deep trenches 98B have an elongated top view and can be arranged as parallel strips.

[0069] Fig.19 1 shows a cross-sectional view of a portion of a TSV 16 and a capacitor 42 formed using a TSV-first process according to some embodiments. Due to the TSV-first process, the TSV 16 is wider on the front side (bottom side shown) of the semiconductor substrate 12 and narrower on the back side of the semiconductor substrate 12. The TSV 16 includes a dielectric liner 112, a barrier / adhesion layer 114, and a fill metal 116. Figure 3 As shown, the top horizontal portion of the barrier / adhesion layer 114 has been removed during the backside grinding process.

[0070] Fig. 20 A cross-sectional view of a portion of TSV 16 and capacitor 42 formed using a TSV-last process according to some embodiments is shown. Due to the TSV-last process, TSV 16 is wider on the back side (top side shown) of semiconductor substrate 12 and narrower on the front side of semiconductor substrate 12. TSV 16 includes dielectric liner 112, barrier / adhesion layer 114, and fill metal 116. The bottom horizontal portion of barrier / adhesion layer 114 remains unremoved.

[0071] Fig.21 , Fig. 22 and Fig.23 A deep trench 98 is shown according to some embodiments (see also Fig.18 ) of the top view. Fig.21 , Fig. 22 and Fig.23 In addition to the shape shown, the deep trench portion of capacitor 42 may take any shape having a larger surface area (larger parameter length). Fig.21 An elongated groove 98 is shown according to some embodiments. Fig. 22 A circular groove 98 is shown according to some embodiments. Fig.23 A cross-shaped groove 98 is shown according to some embodiments.

[0072] In the above embodiments, some processes and components are discussed according to some embodiments of the present disclosure to form a three-dimensional (3D) package. Other processes and components may also be included. For example, a test structure may be included to assist in verification testing of a 3D package or 3DIC device. The test structure may include, for example, a test pad formed in a redistribution layer or on a substrate, which allows testing of a 3D package or 3DIC, using a probe and / or a probe card, etc. Verification testing may be performed on intermediate structures and final structures. In addition, the structures and methods disclosed herein may be used in conjunction with a test method for intermediate verification of a known good die to increase yield and reduce cost.

[0073] Embodiments of the present disclosure have some advantageous features. By forming a decoupling capacitor used by a first device die (e.g., a top die) in a second device die (e.g., a bottom die), the chip area of ​​the first device die is saved. Since the decoupling capacitor is formed as a deep trench capacitor extending from the back side of the semiconductor substrate in the second device die, the chip area of ​​the second device die is also saved, so that the front side can still be used to form other integrated circuits.

[0074] According to some embodiments of the present disclosure, a method for forming a semiconductor package includes: forming a first integrated circuit on the front side of a semiconductor substrate of a first device die; forming a trench capacitor extending from the back side of the semiconductor substrate into the semiconductor substrate; forming a first through-hole and a second through-hole penetrating the semiconductor substrate, wherein the trench capacitor is electrically coupled between the first through-hole and the second through-hole; and joining a second device die to the first device die, wherein the second device die includes a second integrated circuit, and wherein a power supply node of the second integrated circuit is electrically coupled to the first through-hole and the second through-hole.

[0075] In one embodiment, the second device die is free of a decoupling capacitor for regulating power. In one embodiment, the second device die is bonded over the first device die, and wherein the trench capacitor overlaps a portion of the first integrated circuit. In one embodiment, the first through-via is electrically connected to electrical ground, and the second through-via is electrically connected to VDD. In one embodiment, the method further includes: placing the first device die over a carrier, wherein a front side of the semiconductor substrate faces the carrier; forming a gap fill region around the first device die; and performing a thinning process to thin the semiconductor substrate. In one embodiment, the method further includes, after the thinning process, etching the semiconductor substrate from a back side of the semiconductor substrate to form a deep trench, wherein the trench capacitor extends into the deep trench.

[0076] In one embodiment, a first through hole and a second through hole are formed before placing the first device die over the carrier, and a thinning process is performed until the first through hole and the second through hole are exposed. In one embodiment, the method further includes: after the thinning process, further etching the semiconductor substrate to form a through opening penetrating the semiconductor substrate, wherein the first through hole and the second through hole are formed in the through opening. In one embodiment, the method further includes bonding a packaging assembly to the first device die, wherein there is no decoupling capacitor in the packaging assembly. In one embodiment, the first integrated circuit in the first device die is configured to use a power supply regulated by a trench capacitor.

[0077] According to some embodiments of the present disclosure, a semiconductor packaging structure includes: a first device die, the first device die including: a semiconductor substrate; a first integrated circuit located at the bottom surface of the semiconductor substrate; a first through-hole and a second through-hole penetrating the semiconductor substrate; and a trench capacitor extending from the top surface of the semiconductor substrate into the semiconductor substrate, wherein the trench capacitor is electrically coupled to the first through-hole and the second through-hole; and a second device die located above the first device die and bonded to the first device die, wherein the second device die includes a second integrated circuit, and a power node of the second integrated circuit is connected to at least one of the first through-hole and the second through-hole.

[0078] In one embodiment, the power supply nodes include a VDD node and a VSS node. In one embodiment, there is no decoupling capacitor for regulating power in the second device die. In one embodiment, all integrated circuits in the first device die are electrically decoupled from the trench capacitor. In one embodiment, the first integrated circuit is electrically decoupled from the trench capacitor. In one embodiment, the trench capacitor overlaps a portion of the first integrated circuit. In one embodiment, two power supply nodes of the second integrated circuit are connected to the first through-hole and the second through-hole. In one embodiment, the portion of the first integrated circuit includes a lower portion of the portion of the semiconductor substrate, and the trench capacitor occupies an upper portion of the portion of the semiconductor substrate.

[0079] According to some embodiments of the present disclosure, a semiconductor packaging structure includes: a first device die, the first device die including: a semiconductor substrate; a first integrated circuit, close to the bottom surface of the semiconductor substrate; and a trench capacitor, wherein a first portion of the first integrated circuit and a first portion of the trench capacitor are located on opposite sides of the semiconductor substrate, and wherein a second portion of the first integrated circuit and a second portion of the trench capacitor are located in the semiconductor substrate; and a second device die, located above the first device die and bonded to the first device die, wherein the second device die includes a second integrated circuit electrically coupled to the trench capacitor.

[0080] In one embodiment, the trench capacitor is a decoupling capacitor electrically coupled to a power node of the second integrated circuit. In one embodiment, the structure further comprises a first through-hole and a second through-hole penetrating the semiconductor substrate, wherein a first capacitor electrode and a second capacitor electrode of the trench capacitor are connected to the first through-hole and the second through-hole, respectively.

[0081] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose of the embodiments introduced herein and / or achieving the same advantages thereof. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and changes in the present disclosure without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a semiconductor package, comprising: forming a first integrated circuit on a front side of a semiconductor substrate of a first device die; forming a trench capacitor extending from a back side of the semiconductor substrate into the semiconductor substrate; forming a first through-hole and a second through-hole penetrating the semiconductor substrate, wherein the trench capacitor is electrically coupled between the first through-hole and the second through-hole; and A second device die is bonded to the first device die, wherein the second device die includes a second integrated circuit, and wherein a power supply node of the second integrated circuit is electrically coupled to the first through-via and the second through-via.

2. The method according to claim 1, wherein: The second device die has no decoupling capacitors for regulating power supplies.

3. The method according to claim 1, wherein: The second device die is bonded over the first device die, and wherein the trench capacitor overlaps a portion of the first integrated circuit.

4. The method according to claim 1, further comprising: placing the first device die over a carrier, wherein the front side of the semiconductor substrate faces the carrier; forming a gap-fill region around the first device die; and A thinning process is performed to thin the semiconductor substrate.

5. The method according to claim 4, further comprising: After the thinning process, the semiconductor substrate is etched from the back side of the semiconductor substrate to form a deep trench, wherein the trench capacitor extends into the deep trench.

6. The method according to claim 1, wherein: The first integrated circuit in the first device die is configured to use a power supply regulated by the trench capacitor.

7. A semiconductor packaging structure, comprising: A first device die, wherein the first device die comprises: Semiconductor substrate; A first integrated circuit is located at the bottom surface of the semiconductor substrate; A first through hole and a second through hole penetrating the semiconductor substrate; and a trench capacitor extending from a top surface of the semiconductor substrate into the semiconductor substrate, wherein the trench capacitor is electrically coupled to the first through-via and the second through-via; and A second device die is located above and bonded to the first device die, wherein the second device die includes a second integrated circuit and a power node of the second integrated circuit is connected to at least one of the first through-via and the second through-via.

8. A semiconductor packaging structure, comprising: A first device die, wherein the first device die comprises: Semiconductor substrate; A first integrated circuit is adjacent to a bottom surface of the semiconductor substrate; and a trench capacitor, wherein a first portion of the first integrated circuit and a first portion of the trench capacitor are located on opposite sides of the semiconductor substrate, and wherein a second portion of the first integrated circuit and a second portion of the trench capacitor are located in the semiconductor substrate; and A second device die is over and bonded to the first device die, wherein the second device die includes a second integrated circuit electrically coupled to the trench capacitor.

9. The semiconductor package structure according to claim 8, wherein: The trench capacitor is a decoupling capacitor electrically coupled to a power supply node of the second integrated circuit.

10. The semiconductor package structure according to claim 8, further comprising a first through hole and a second through hole penetrating the semiconductor substrate, wherein: A first capacitor electrode and a second capacitor electrode of the trench capacitor are connected to the first through-hole and the second through-hole, respectively.

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