A packaging structure for a UMCP product and its fabrication method
By stacking DRAM and Nand Flash chipsets in staggered layers and employing a double-sealing process, the problem of excessive thickness in UMCP products has been solved, achieving a thinner and lighter design and improved yield.
Patent Information
- Application Number
- CN202411349907.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-26
- Publication Date
- 2025-10-28
- Estimated Expiration
- 2044-09-26
AI Technical Summary
Existing UMCP products are too thick to meet the requirements of thin and light designs.
It adopts a staggered stacking structure of DRAM chipset and Nand Flash chipset, and separately encapsulates the FC main control chip with DRAM chipset and Nand Flash chipset through two encapsulation processes. It uses flip-chip process and POP packaging technology to reduce product thickness and improve yield.
This enabled a thinner and lighter design for UMCP products, improved product yield and stability, and reduced the loss of NAND chips.
Smart Images
Figure CN119601567B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the technical field of chip packaging, specifically to a packaging structure for a UMCP product. This invention also provides a method for manufacturing the packaging structure for a UMCP product. Background Technology
[0002] UMCP (Universal Multi Chip Package) is a general-purpose embedded multi-chip package; it encapsulates UFS (Universal Flash Memory, which consists of a main controller chip and multiple Flash chips) and LPDDR DRAM (Low Power Double Data Rate DRAM), suitable for advanced embedded storage applications.
[0003] With the increasing demand for thinner and lighter mobile terminal products, UMCP products need to be thinner and thinner. The existing traditional product stacking structure stacks NAND Flash chips on a substrate, stacks DRAM chips on top of NAND Flash chips, and mounts the FC main control chip on the substrate. The DRAM chips, NAND Flash chips, and FC main control chip are then encapsulated in a plastic package. This results in a relatively thick UMCP product after the DRAM chips are stacked on top of the NAND Flash chips, which no longer meets the requirements for thinner and lighter designs. Therefore, there is an urgent need to develop a thinner and lighter UMCP product. Summary of the Invention
[0004] To address the aforementioned issues, this invention provides a packaging structure for UMCP products that reduces product thickness, enabling the product to meet the requirements for lightweight and thin design.
[0005] A packaging structure for a UMCP product, characterized in that it comprises:
[0006] Stacked DRAM chipsets;
[0007] Stacked NAND Flash chipsets;
[0008] FC main control chip;
[0009] First substrate;
[0010] The second substrate is a carrier substrate;
[0011] And the first molding compound;
[0012] The bottom BUMP of the FC active chip is soldered to the central area of the upper surface of the first substrate. The bottom chip of the DRAM chip set is mounted on the upper surface of the FC main control chip. Each layer of DRAM chip in the DRAM chip set is connected to the corresponding upper surface of the first substrate through a first wire bonding group. The bottom first solder ball of the first substrate is soldered to one side area of the upper surface of the second substrate. The bottom chip of the Nand Flash chip set is mounted to the other side area of the upper surface of the second substrate. Each layer of Nand Flash chip set is connected to the corresponding upper surface of the second substrate through a second wire bonding group. The first molding compound encapsulates the DRAM chip set, Nand Flash chip set, FC main control chip, and first substrate on the upper surface of the second substrate.
[0013] Its further features are:
[0014] It also includes a second molding compound, which encapsulates the DRAM chipset and the FC main control chip on the upper surface of the first substrate, so that the RAM chipset, the FC main control chip, and the first substrate are pre-assembled into components, making subsequent packaging fast and efficient;
[0015] The DRAM chipset includes several layers of DRAM chips stacked in a staggered manner from bottom to top to one side. The upper DRAM chip of an adjacent DRAM chip is connected to the corresponding contact of the lower DRAM chip in the staggered space through wire bonding, until the bottommost DRAM chip is connected to the corresponding contact on the upper surface of the first substrate through wire bonding. This ensures that the length of a single wire bonding is not too long, which can cause bending during molding and affect product stability.
[0016] The Nand Flash chipset includes several layers of Nand Flash chips stacked in a staggered manner from bottom to top to one side. The upper Nand Flash chip of an adjacent Nand Flash chip is connected to the corresponding contact of the lower Nand Flash chip in the staggered space through wire bonding, until the bottommost Nand Flash chip is connected to the corresponding contact on the upper surface of the second substrate through wire bonding. This ensures that the length of a single wire bonding is not too long, which can cause bending during molding and affect product stability.
[0017] The DRAM chipset and the Nand Flash chipset are arranged in a staggered manner facing each other, which ensures that the spacing between the two sides is saved, making the width area of the second substrate relatively narrow.
[0018] A method for manufacturing a UMCP product packaging structure is characterized in that: the FC main control chip and DRAM chipset are first encapsulated on a first substrate to form an integral BGA chip, and the integral BGA chip is attached to one side of a second substrate using a flip-chip process, and the Flash chipset is mounted on the other side of the substrate and connected to form interconnection through a second wire bonding group. Then, a second encapsulation is performed to form a first molding compound, thus forming the UMCP product.
[0019] Its further features are:
[0020] During the first packaging, the DRAM chipset and the main control chip do not communicate with each other. They are tested separately during the testing process. Even if the main control chip is faulty, it will not affect the function and role of the DRAM chip.
[0021] When the DRAM chipset and FC controller chip package is determined to be abnormal, the abnormal component will be removed before the second packaging and will no longer be used, thus reducing the loss of NAND chips. Therefore, the product yield is improved by packaging twice.
[0022] Using the technology of this invention, the DRAM chipset and FC main control chip are encapsulated on a single substrate, which reduces the thickness of the single-package product. Then, the encapsulated DRAM chipset and main control chip are mounted on the carrier substrate using a flip-chip process. Simultaneously, the NAND chipset is mounted on the other side of the carrier substrate. After mounting, interconnection is formed by gold wire bonding. This process utilizes both POP packaging and SIP packaging. Its advantages are as follows:
[0023] By encapsulating the DRAM chipset and the main control chip together and then mounting the NAND chip on the other side, the product thickness can be greatly reduced: the original height of the NAND chipset and DRAM chipset stacked together was greater than the height of the product in this case.
[0024] This can improve product yield because the yield of the main control chip and NAND chip is relatively high, while the yield of DRAM chip is relatively low. During the packaging process, the DRAM chip and the main control chip do not communicate with each other, and they are tested separately. Even if the main control chip is abnormal, it will not affect the function and role of the DRAM chip. In addition, if the DRAM and main control chip package is abnormal in the initial test, it will be rejected in the second packaging and will not be used again, which can reduce the loss of NAND chips. Therefore, the two packaging processes can improve product yield. Attached Figure Description
[0025] Figure 1 This is a schematic diagram of the packaging structure of the present invention;
[0026] The names corresponding to the serial numbers in the diagram are as follows:
[0027] Second solder ball 1, second substrate 2, FC main control chip 3, BUMP 4, first substrate 5, Nand Flash chipset 6, second wire bonding group 7, DRAM chipset 8, first molding compound 9, second molding compound 10, first wire bonding group 11. Detailed Implementation
[0028] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.
[0029] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings and are used only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this invention. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.
[0030] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art will understand the specific meaning of the above terms in this invention based on the specific circumstances.
[0031] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.
[0032] A packaging structure for a UMCP product, see Figure 1 It includes: a stacked DRAM chipset 8, a stacked NandFlash chipset 6, an FC main control chip 3, a first substrate 5, a second substrate 2, a first molding compound 9, and a second molding compound 10.
[0033] In practice, the DRAM chipset 8 includes four layers of DRAM chips, and the Nand Flash chipset 6 includes four layers of Nand Flash chips.
[0034] The bottom BUMP4 of the FC active chip 3 is soldered to the central area of the upper surface of the first substrate 5. The bottom chip of the DRAM chip group 8 is mounted on the upper surface of the FC main control chip 3. Each layer of DRAM chip of the DRAM chip group 8 is connected to the corresponding upper surface of the first substrate 5 through the first bonding wire group 11. The second molding compound 10 encapsulates the DRAM chip group 8 and the FC main control chip 3 on the upper surface of the first substrate 5, so that the RAM chip group 8, the FC main control chip 3, and the first substrate 8 are pre-assembled into an integral BGA chip. The bottom first solder ball of the first substrate 8 is soldered to the upper surface of the second substrate 2. The bottom chip of the Nand Flash chip group 6 is mounted to the right side area of the upper surface of the second substrate 2. Each layer of chip of the Nand Flash chip group 6 is connected to the corresponding upper surface of the second substrate 2 through the second bonding wire group 7. The first molding compound 9 encapsulates the DRAM chip group 8, the Nand Flash chip group 6, the FC main control chip 3, and the first substrate 5 on the upper surface of the second substrate 2.
[0035] In specific implementation, the DRAM chipset 8 includes four layers of DRAM chips stacked in a staggered manner from bottom to top to the right. The upper layer of adjacent DRAM chips is connected to the corresponding contact of the lower layer of DRAM chips in the staggered space through wire bonding, until the bottom layer of DRAM chips is connected to the corresponding contact on the upper surface of the first substrate 5 through wire bonding. This ensures that the length of a single wire bonding is not too long, which can cause bending during molding and affect product stability.
[0036] The Nand Flash chipset 6 includes four layers of Nand Flash chips stacked in a staggered manner from bottom to top and left to right. The upper Nand Flash chip of an adjacent Nand Flash chip is connected to the corresponding contact of the lower Nand Flash chip in the staggered space by wire bonding, until the bottommost Nand Flash chip is connected to the corresponding contact on the upper surface of the second substrate 2 by wire bonding. This ensures that the length of a single wire bonding is not too long, which can cause bending during molding and affect product stability.
[0037] In practice, a second solder ball 1 is provided at the bottom of the second substrate 2, and the second solder ball performs soldering and assembly operations on the entire UMCP product.
[0038] By encapsulating the DRAM chipset 8 and the FC controller chip 3 together and then assembling them in the left area of the second substrate 2, and then mounting the Nand chipset 6 on the right side, the product thickness can be reduced: originally, the Nand chipset 6 and the DRAM chipset 8 stacked together required a total thickness of 8 layers, but now the DRAM chipset 8 and the FC controller chip 3 are encapsulated together and only 5 layers thick. In addition, the first substrate 5 and the first solder ball are added, and the total thickness does not exceed 7 layers.
[0039] A method for fabricating a UMCP product packaging structure, see Figure 1 The FC main control chip 3 and DRAM chipset 8 are first encapsulated on the first substrate 5 to form an integral BGA chip. The integral BGA chip is then attached to one side of the second substrate 2 using a flip-chip process. The Flash chipset 6 is mounted on the other side of the second substrate 2 and connected to form an interconnect through the second wire bonding group. After a second encapsulation, the first molding compound 9 is formed, thus forming the UMCP product.
[0040] In practice: because the yield of FC main control chip and Nand Flash chip is relatively high, while the yield of DRAM chip is relatively low, the DRAM chip is combined with the FC main control chip for the first packaging, so that the final product has pre-combination testing of DRAM chip;
[0041] During the first packaging, the DRAM chipset and the main control chip do not communicate with each other. They are tested separately during the testing process. Even if the main control chip is faulty, it will not affect the function and role of the DRAM chip.
[0042] When the DRAM chipset and FC controller chip package is determined to be abnormal, the abnormal component will be removed before the second packaging and will no longer be used, thus reducing the loss of NAND chips. Therefore, the product yield is improved by packaging twice.
[0043] Using the technology of this invention, the DRAM chipset and FC main control chip are encapsulated on a single substrate, which reduces the thickness of the single-package product. Then, the encapsulated DRAM chipset and main control chip are mounted on the carrier substrate using a flip-chip process. Simultaneously, the NAND chipset is mounted on the other side of the carrier substrate. After mounting, interconnection is formed by gold wire bonding. This process utilizes both POP packaging and SIP packaging. Its advantages are as follows:
[0044] By encapsulating the DRAM chipset and the main control chip together and then mounting the NAND chip on the other side, the product thickness can be greatly reduced: the original height of the NAND chipset and DRAM chipset stacked together was greater than the height of the product in this case.
[0045] This can improve product yield because the yield of the main control chip and NAND chip is relatively high, while the yield of DRAM chip is relatively low. During the packaging process, the DRAM chip and the main control chip do not communicate with each other, and they are tested separately. Even if the main control chip is abnormal, it will not affect the function and role of the DRAM chip. In addition, if the DRAM and main control chip package is abnormal in the initial test, it will be rejected in the second packaging and will not be used again, which can reduce the loss of NAND chips. Therefore, the two packaging processes can improve product yield.
[0046] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.
[0047] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.
Claims
1. A packaging structure for a UMCP product, characterized in that, It includes: Stacked DRAM chipsets; Stacked NAND Flash chipsets; FC main control chip; First substrate; The second substrate is a carrier substrate; And the first molding compound; The bottom BUMP of the FC main control chip is soldered to the center area of the upper surface of the first substrate. The bottom chip of the DRAM chip group is mounted on the upper surface of the FC main control chip. Each layer of DRAM chip group is connected to the corresponding upper surface of the first substrate through the first wire bonding group. The bottom first solder ball of the first substrate is soldered to one side area of the upper surface of the second substrate. The bottom chip of the Nand Flash chip group is mounted to the other side area of the upper surface of the second substrate. Each layer of Nand Flash chip group is connected to the corresponding upper surface of the second substrate through the second wire bonding group. The first molding compound encapsulates the DRAM chip group, Nand Flash chip group, FC main control chip, and first substrate on the upper surface of the second substrate. It also includes a second molding compound that encapsulates the DRAM chipset and the FC main control chip on the upper surface of the first substrate, thereby pre-assembling the DRAM chipset, the FC main control chip, and the first substrate into a component.
2. The packaging structure of a UMCP product according to claim 1, characterized in that: The DRAM chipset includes several layers of DRAM chips stacked in a staggered manner from bottom to top to one side. The upper DRAM chip of an adjacent DRAM chip is connected to the corresponding contact of the lower DRAM chip in the staggered space through wire bonding, until the bottommost DRAM chip is connected to the corresponding contact on the upper surface of the first substrate through wire bonding.
3. The packaging structure of a UMCP product according to claim 2, characterized in that: The Nand Flash chipset includes several layers of Nand Flash chips stacked in a staggered manner from bottom to top to one side. The upper Nand Flash chip of an adjacent Nand Flash chip is connected to the corresponding contact of the lower Nand Flash chip in the staggered space by wire bonding, until the bottommost Nand Flash chip is connected to the corresponding contact on the upper surface of the second substrate by wire bonding.
4. The packaging structure of a UMCP product according to claim 3, characterized in that: The DRAM chipset and the Nand Flash chipset are arranged in a staggered manner facing each other.
5. A method for manufacturing a UMCP product packaging structure as described in any one of claims 1-4, characterized in that: The FC main control chip and DRAM chipset are first encapsulated on the first substrate to form an integral BGA chip. The integral BGA chip is then attached to one side of the second substrate using a flip-chip process. The Flash chipset is mounted on the other side of the substrate and connected to each other through the second wire bonding group. After a second encapsulation, the first molding compound is formed, resulting in the UMCP product.
6. The method for manufacturing a UMCP product packaging structure according to claim 5, characterized in that: During the initial packaging, the DRAM chipset and the main control chip do not communicate with each other. They are tested separately during the testing process. Even if the main control chip malfunctions, it will not affect the function and role of the DRAM chip.
7. The method for manufacturing a UMCP product packaging structure according to claim 5, characterized in that: When the DRAM chipset and FC controller chip package is determined to be abnormal, the abnormal component will be removed before the second packaging and will no longer be used, thus reducing the loss of NAND chips. Therefore, the product yield is improved by packaging twice.
Citation Information
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Packaging structure of memory chip
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