Double-step high-power SSPC hardware circuit based on channel protection

Abstract

The invention belongs to the technical field of aviation power distribution systems, and discloses a channel protection-based double-step high-power SSPC hardware circuit, which adopts two sets of short-circuit protection circuits to set two overturning points. In hardware design, two sets of independent short-circuit protection circuits are designed, and output signals of the two sets of protection circuits are respectively connected with two I / O ports of a processor in a one-to-one manner. One of the two overturning points is used for identifying a low-multiple current, and the other overturning point is used for identifying a high-multiple current. And the output results of the two short-circuit protection circuits enter the processor for AND logical operation, so that the short-circuit protection function is realized.

Description

Technical Field

[0001] The invention relates to an aviation power distribution system, belongs to the field of MOSFET protection of power distribution systems, and specifically relates to a dual-step high-power SSPC hardware circuit design method based on channel protection. Background Art

[0002] With the rapid development of more-electric and all-electric aircraft, electric energy has become an important secondary energy source on aircraft, which greatly simplifies the aircraft structure, reduces the aircraft weight and full-cycle cost, and improves the safety, reliability and maintainability of the aircraft. As an important part of the power distribution system of more-electric and all-electric aircraft, the solid-state power controller has the advantages of fast switching speed, no contact, low electromagnetic interference and high reliability. As the capacity and types of electrical loads on aircraft also increase, it is necessary to improve the power level of DC solid-state power controller (SSPC) and carry out research on high-power DC SSPC.

[0003] High-power DC SSPC will generate a large current shock when starting capacitive load and short-circuit fault occurs, which will endanger the safe and reliable operation of the aircraft electrical system. Therefore, it is necessary to suppress the current shock and study the short-circuit protection technology of high-power DC SSPC.

[0004] In summary, a dual-step high-power SSPC hardware circuit based on channel protection is urgently needed. Summary of the invention

[0005] The present invention provides a dual-step high-power SSPC hardware circuit design method based on channel protection in a high-power distribution network, so as to realize reliable protection of MOSFET in the distribution system.

[0006] To achieve the above object, the present invention provides the following technical solutions:

[0007] In the first aspect, a dual-step high-power SSPC hardware circuit based on channel protection is provided, which includes: comparing the current acquisition value with the threshold of the resistance network flip point, and performing short-circuit protection through the high and low levels output by the comparator and the output level of the processor algorithm.

[0008] The dual-step high-power SSPC hardware circuit includes: a current acquisition circuit, a high-multiple flip circuit, a low-multiple flip circuit, a comparator circuit, a comparator output circuit and a processor operation circuit.

[0009] The value of the current acquisition circuit is used as the reference value of the comparator circuit input. The thresholds of the high-multiple flip circuit and the low-multiple flip circuit are compared with the reference value through the comparator circuit, and then output to the processor operation circuit through the comparator output circuit. After operation, the corresponding high and low levels are output.

[0010] One end of the current acquisition circuit is connected to the sampling resistor of the power circuit, and the other end is connected to the non-inverting input end of the comparator circuit. The high-multiple flip circuit and the low-multiple flip circuit are respectively connected to the inverting input ends of the two comparators. The output is compared by the comparator circuit, and the comparator output circuit is connected to the I / O pin of the processor and enters the processor operation circuit. After the "AND" logic operation of the processor operation circuit, the output is connected to the actuator of the SSPC to perform the short-circuit protection function.

[0011] As a further technical solution of the present invention, the in-phase input terminals of the two comparator circuits are commonly connected to the sampling resistor of the power circuit, and the collected values ​​are used as reference values ​​of the comparator circuits.

[0012] As a further technical solution of the present invention, the high-multiple flip circuit and the low-multiple flip circuit are formed by the same resistor network through resistor voltage division to form different voltage values ​​as high-multiple and low-multiple flip values.

[0013] As a further technical solution of the present invention, the flip value of the high-multiple flip circuit is compared with the reference value through a comparator circuit 1.

[0014] As a further technical solution of the present invention, the flip value of the low-multiple flip circuit is compared with the reference value through the comparator circuit 2.

[0015] As a further technical solution of the present invention, the flip value of the high-multiple flip circuit comes from point b, that is, the value of the voltage divider of R1 and R2 in the resistor network (R1, R2, R3).

[0016] As a further technical solution of the present invention, the flip value of the low-multiple flip circuit comes from point a, that is, the value of the voltage divider of R1 in the resistor network (R1, R2, R3).

[0017] As a further technical solution of the present invention, the reference value of the current acquisition circuit is input into the comparator (U1A and U1B) through the non-inverting input terminal, and the threshold values ​​of the high-multiple flip circuit and the low-multiple flip circuit are input into the comparator (U1A and U1B) through the inverting input terminal of the comparator, and are output after being operated by multiple logic gates inside the comparator (U1A and U1B).

[0018] As a further technical solution of the present invention, the outputs ITRIP_1 and ITRIP_2 of the comparator circuit 1 (U1A) and the comparator circuit 2 (U1B) are electrically connected to the I / O ports of the processor operation circuit respectively to input the processor.

[0019] Among them, ITRIP_1 and ITRIP_2 enter the processor and perform "AND" logic operation respectively. The logic operation rule is that when the current value is less than h times, the comparator circuit 1 outputs a high level, and the comparator circuit 2 outputs a high level; when the current value is greater than h times and less than g times, the comparator circuit 1 outputs a high level, and the comparator circuit 2 outputs a low level; when the current value is greater than g times, the comparator circuit 1 outputs a low level, and the comparator circuit 2 outputs a low level. The processor outputs the comparator 1 and comparator 2 levels after performing "AND" logic.

[0020] As a further technical solution of the present invention, the level output after performing the "AND" logic is sent to the driver chip that drives the SSPC to turn on and off, and then the SSPC trip protection is executed.

[0021] In the second aspect, a dual-step high-power SSPC hardware circuit design method based on channel protection is provided, which includes: sequentially designing a current acquisition circuit, a high-multiple flip circuit, a low-multiple flip circuit, a comparator circuit, a comparator output circuit, and a processor operation circuit;

[0022] The voltage reference value collected by the current acquisition circuit is compared with the preset thresholds of the high-multiple flip circuit and the low-multiple flip circuit through a comparator, and the corresponding logic level is output to the processor operation circuit through the comparator output circuit. After the "AND" logic operation in the processor operation circuit, it is output to the drive chip to control the SSPC actuator to perform SSPC trip protection.

[0023] Compared with the prior art, the present invention has the following beneficial effects:

[0024] 1. The circuit is simple and reliable, covering a wide range of short-circuit protection multiples. It is suitable for use in high-power SSPC occasions. At the same time, it realizes accurate protection for different multiples, improving the reliability and safety of equipment and distribution systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, without paying creative labor, other drawings obtained based on these drawings still belong to the scope of the present invention.

[0026] Figure 1 This is a block diagram of the short-circuit protection principle of the double-step high-power SSPC of the present invention;

[0027] Figure 2 It is the principle diagram of the high-power SSPC acquisition circuit of the present invention;

[0028] Figure 3 It is the principle diagram of the double-step high-power SSPC short-circuit protection circuit of the present invention;

[0029] Figure 4 This is the protection curve of the double-step high-power SSPC short-circuit protection circuit of the present invention. DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0031] A method for designing a high-power SSPC hardware circuit based on double-step channel protection. The method requires two sets of independent short-circuit protection circuits and current sampling circuits to work together to complete the short-circuit protection function of the high-power SSPC, ensuring accurate protection of different short-circuit protection multiples. The circuit consists of a current acquisition circuit, a high-multiple flip circuit, a low-multiple flip circuit, a comparator circuit, a comparator output circuit, and a processor operation circuit. The level flip is achieved by comparing the reference value of the acquisition circuit with the preset thresholds of the high-multiple flip circuit and the low-multiple flip circuit. When the processor operation circuit outputs a high level, the SSPC works normally and does not move. When it flips from a high level to a low level, the short-circuit protection function is implemented, and real-time and accurate protection is performed according to the preset threshold of the short-circuit protection multiple, so that the distribution equipment can work reliably and safely.

[0032] Figure 1 It is a block diagram of the short-circuit protection principle of a double-step high-power SSPC, which illustrates the circuit composition of the short-circuit protection function of the entire distribution network. Figure 2 It is the schematic diagram of the high-power SSPC acquisition circuit, which realizes the source of the comparator reference value input. Figure 3 It is the schematic diagram of the double-step high-power SSPC short-circuit protection circuit. It is the core design of the short-circuit protection circuit and adopts two independent short-circuit protection circuits. Figure 4 It is the protection curve of the double-step high-power SSPC short-circuit protection circuit, which shows the range and protection time of the short-circuit protection.

[0033] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0034] like Figure 1As shown, the reference value of the current acquisition circuit and the high multiple value of the high multiple flip circuit are compared in comparator circuit 1, and the reference value of the current acquisition circuit and the low multiple value of the low multiple flip circuit are compared in comparator circuit 2. The outputs of comparator circuit 1 and comparator circuit 2 are input into the processor operation circuit for "AND" logic processing. The logic processing in the processor operation circuit is as follows:

[0035] Process the input signal a, and perform I2T tripping or not tripping according to the acquisition result of the current acquisition circuit;

[0036] Processor signal b, when the control circuit is fault-free, this signal will not appear, so this signal is an abnormal signal. Since the current multiple identified by the short-circuit protection circuit 1 is very large, the circuit indicates that there is a g-fold (immediate trip) current, and an immediate trip strategy is adopted;

[0037] Processor signal c is a fixed time-delay trip. If the short-circuit current disappears (the short-circuit signal disappears) during the delay time, the time-delay trip timer needs to be reset to ensure that the next time the delay trip short-circuit signal comes, the timer starts from 0.

[0038] The processor signals d, believing that there is a g-fold short-circuit current and adopts an immediate tripping strategy.

[0039] The above trip signal is input to the driving circuit of the high-power SSPC, so that the driving circuit outputs a control signal to turn on or off the high-power load.

[0040] like Figure 2 As shown, the current acquisition circuit acquires the current signal through the sampling resistor in the power circuit in the form of voltage and isolates it from the power circuit. The resistance value outside the operational amplifier is designed to match the high level and the low level, and the voltage value of the operational amplifier is matched to complete the design of the amplification factor, thereby completing the normal current acquisition function.

[0041] like Figure 3 As shown, in the hardware design, two independent short-circuit protection circuits are set up (the output signals of the two circuits are connected one-to-one with the two I / O ports of the processor respectively), one circuit is used to identify h times the current, and the other circuit is used to identify g times the current.

[0042] Each short-circuit protection circuit is mainly composed of one comparator, and the overall output of the circuit is the output of the two comparators performing "AND" logic.

[0043] When the current value is less than h times, the comparator circuit 1 outputs a high level, and the comparator circuit 2 also outputs a high level; when the current value is greater than h times and less than g times, the comparator circuit 1 outputs a high level, and the comparator circuit 2 outputs a low level. At this time, the short-circuit protection is low-multiple protection; when the current value is greater than g times, the comparator circuit 1 outputs a low level, and the comparator circuit 2 also outputs a low level. At this time, it is high-multiple protection.

[0044] As Figure 4 shown, the entire tripping curve is divided into three major parts, including an immediate tripping protection curve, a time-delay tripping protection curve, and an I2T tripping protection curve.

[0045] a) Immediate tripping strategy and protection curve

[0046] For the current of "MAX_LEVEL", since there is no requirement for the lower limit of the tripping time and the current level is relatively large, an immediate tripping strategy is adopted, that is, when the current of "MAX_LEVEL" is recognized, a tripping operation is directly executed (it is necessary to ensure that the tripping time t < t3, and the actual immediate action can meet the requirements), and the fault current is cut off as soon as possible;

[0047] The actual protection curve is the first-segment ideal curve. The current level selected for the first-segment tripping curve is I ≥ g (g = (f + c) / 2, corresponding to the current multiple in the middle of the JA line and the KF line (ideal voltage division)), and the corresponding protection time is immediate protection (< t3 (corresponding to the time of the AE line), and actually < t4 can be guaranteed).

[0048] b) Time-delay tripping strategy and protection curve

[0049] For the current of "MIDDLE_LEVEL", a time-delay tripping strategy is adopted, and a fixed time t (t1 < t < t3) (t < t3 is to ensure that t meets the tripping time requirements of all currents of this level) is selected as the tripping time for all currents of this level;

[0050] The actual protection curve is the second-segment ideal curve. The current level selected for the second-segment tripping curve is h ≤ I < g (h = (d + e) / 2, corresponding to the current multiple in the middle of the EC line and the BD line), and the corresponding protection time is a fixed delay t4 (t4 = (t1 + t3) / 2, corresponding to the time of the vertical line Ⅱ).

[0051] c) I2T tripping strategy and protection curve

[0052] For the current of "MINI_LEVEL", an I2T tripping strategy is adopted to ensure that the tripping time of the current of this level meets the requirements of the tripping curve (the I2T curve is between "DI" and "GH").

[0053] The actual protection curve is the third ideal curve. The current level selected for the third short-circuit tripping curve is I < h, and the corresponding protection time is the I2T time-delay protection (the time corresponding to line III). The actual I2T curve will be designed at a position centered between the curves "DI" and "GH". When it is lower than a certain specific value, the SSPC does not require protection.

[0054] Thus, the object of the present invention is accomplished.

[0055] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above-described exemplary embodiments, and without departing from the spirit or basic characteristics of the present invention, the present invention can be implemented in other specific forms. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be encompassed within the present invention. Any reference signs in the claims should not be construed as limiting the claims involved.

Claims

1. A high-power SSPC hardware circuit based on channel protection double-step, characterized in that , including: current acquisition circuit, high-multiple flip circuit, low-multiple flip circuit, comparator circuit, comparator output circuit and processor operation circuit; The value of the current acquisition circuit is used as a reference value input to the comparator circuit, and the values ​​of the high-multiple flip circuit and the low-multiple flip circuit are compared with the reference value through the comparator circuit, and then output to the processor operation circuit through the comparator output circuit, and the corresponding high and low levels are output after operation; One end of the current acquisition circuit is connected to the sampling resistor of the power circuit, and the other end is connected to the non-inverting input end of the comparator circuit. The high-multiple flip circuit and the low-multiple flip circuit are respectively connected to the inverting input ends of the two comparators, and the output is output after comparison by the comparator circuit. The comparator output circuit is connected to the I / O pin of the processor and enters the processor operation circuit. After the "AND" logic operation of the processor operation circuit, the output is connected to the execution mechanism of the SSPC, thereby performing the short-circuit protection function.

2. According to claim 1, a high-power SSPC hardware circuit based on channel protection double-step, characterized in that: The in-phase input terminals of the two comparator circuits are commonly connected to the sampling resistor of the power circuit, and the collected values ​​are used as reference values ​​of the comparator circuits.

3. According to claim 1, a high-power SSPC hardware circuit based on channel protection double-step is characterized in that: The high-multiple flipping circuit and the low-multiple flipping circuit are formed by resistor voltage division in the same resistor network to form different voltage values ​​as high-multiple and low-multiple flipping values.

4. According to claim 3, a high-power SSPC hardware circuit based on channel protection double-step is characterized in that: The flip value of the high-multiple flip circuit is compared with the reference value through a comparator circuit 1 , and the flip value of the low-multiple flip circuit is compared with the reference value through a comparator circuit 2 .

5. A high-power SSPC hardware circuit based on channel protection double-step according to claim 4, characterized in that: The flipping value of the high-multiple flipping circuit is derived from the value of the voltage divided by the resistors R1 and R2; the flipping value of the low-multiple flipping circuit is derived from the value of the voltage divided by the resistor R1.

6. A high-power SSPC hardware circuit based on channel protection double-step according to claim 5, characterized in that: The reference value of the current acquisition circuit is input into the comparator circuit through the in-phase input terminal, and the values ​​of the high-multiple flip circuit and the low-multiple flip circuit are input into the comparator circuit through the inverting input terminal of the comparator circuit, and are output after being calculated by multiple logic gates inside the comparator circuit.

7. A high-power SSPC hardware circuit based on channel protection double-step according to claim 6, characterized in that: The outputs ITRIP_1 and ITRIP_2 of the comparator circuit 1 and the comparator circuit 2 are respectively electrically connected to the I / O ports of the processor operation circuit to input the processor.

8. A high-power SSPC hardware circuit based on channel protection double-step according to claim 7, characterized in that: After performing the "AND" logic, the output level is sent to the driver chip that drives the SSPC to turn on and off, and then the SSPC trip protection is executed.

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