Compensation drive circuit of power converter and power converter

Abstract

The invention relates to the field of power converters, and particularly provides a compensation driving circuit of a power converter and the power converter, and the compensation driving circuit comprises a compensation time calculation module, a driving signal generation module and a driving circuit, the compensation module is used for acquiring a current zero-crossing comparison signal reflecting the conduction condition of a rectifier tube at the output side of the power converter and a sampling driving signal of a rectifier bridge at the output side of the power converter, and calculating compensation time according to the current zero-crossing comparison signal and the sampling driving signal; and the driving signal generation module is used for acquiring a conduction signal representing the conduction condition of the rectifier tube by the high level, generating a final driving signal according to the conduction signal and the compensation time, and outputting the final driving signal to the driving circuit. Therefore, the rectifier tube is driven according to the compensation time and the conduction signal, meanwhile, the delay caused by the driving circuit can be compensated, and the rectified output current is balanced through compensation driving.

Description

Technical Field

[0001] The invention relates to the field of power converters, and in particular to a compensation drive circuit of a power converter and a power converter. Background Art

[0002] For power converters, the existing synchronous rectification technology is mainly aimed at low-voltage and high-current applications, and can be divided into three categories: theoretical calculation prediction type (referred to as calculation type), voltage signal drive type (referred to as voltage type), and current signal drive type (referred to as current type).

[0003] The computing type requires complex modeling and a lot of debugging work when dealing with dynamic scenarios, and the protection against abnormal faults cannot be as fast as the hardware type (including voltage type and current type). The voltage type and current type are subject to the inherent delay of the hardware (including control circuit and drive circuit delay) and have disadvantages in preventing backflow. Due to the limited PCB layout space, it is impossible to take into account the accuracy of the rising and falling edges of the drive. Due to the oscillation of the sampling signal, an incorrect response will be made to the abnormal sampling signal.

[0004] Since some rectifier tubes, such as wide bandgap devices, have a large reverse voltage drop, when the ratio of the actual pulse width to the ideal pulse width of the synchronous drive is less than 1, the topology of the output parallel structure will cause the voltage drops of the rectifier tubes in the two rectifier circuits to not be equal at all times, and the side with a higher pulse width ratio will gradually increase the pulse width ratio of that side, exacerbating the imbalance, making it difficult to maintain current balance in the two rectifier outputs by adjusting the primary side drive. Summary of the invention

[0005] In order to solve one of the above technical problems, the present invention proposes the following technical solution.

[0006] An embodiment of the first aspect of the present invention proposes a compensation drive circuit for a power converter, comprising a compensation time calculation module, a drive signal generation module and a drive circuit, wherein the compensation time calculation module is connected to the drive signal generation module, the output end of the drive signal generation module is connected to the drive circuit, and the output end of the drive circuit is connected to the rectifier tube of the rectifier bridge on the output side of the power converter.

[0007] The compensation time calculation module is used to obtain a current zero-crossing comparison signal reflecting the conduction status of the rectifier tube on the output side of the power converter and a sampling drive signal of the rectifier bridge on the output side of the power converter, and calculate the compensation time according to the current zero-crossing comparison signal and the sampling drive signal.

[0008] The driving signal generating module is used to obtain a conduction signal whose high level indicates the conduction status of the rectifier tube, generate a final driving signal according to the conduction signal and the compensation time, and output it to the driving circuit.

[0009] In addition, the compensation driving circuit of the power converter according to the above embodiment of the present invention may also have the following additional technical features.

[0010] According to one embodiment of the present invention, the compensation drive circuit of the power converter also includes a current sampling circuit and a current zero-crossing comparison circuit, the input end of the current sampling circuit is connected between the resonant capacitor on the output side of the power converter and the input end of the rectifier bridge, and the input end of the current zero-crossing comparison circuit is connected to the output end of the current sampling circuit.

[0011] The current sampling circuit is used to sample the input current of the rectifier bridge on the output side of the power converter and output a voltage signal proportional to the amplitude of the input current; the current zero-crossing comparison circuit is used to compare the voltage signal with a preset threshold voltage to generate a current zero-crossing comparison signal reflecting the conduction status of the rectifier tube on the output side of the power converter.

[0012] According to one embodiment of the present invention, the compensation drive circuit of the power converter also includes a logic processing module, the input end of the logic processing module is connected to the output end of the current zero-crossing comparison circuit, the output end of the logic processing module is connected to the input end of the drive signal generating module, and the logic processing module is used to generate a conduction signal with a high level indicating the conduction status of the rectifier tube from the current zero-crossing comparison signal.

[0013] According to one embodiment of the present invention, the compensation drive circuit of the power converter also includes a primary drive signal sampling module, whose output end is connected to the input end of the logic processing module, and the primary drive signal sampling module is used to sample the primary drive signal of the power converter, and after synchronous alignment, output the primary drive signal to the logic processing module.

[0014] According to one embodiment of the present invention, the compensation drive circuit of the power converter also includes an over-resonance mode judgment module, whose output end is connected to the input end of the logic processing module, and the over-resonance mode judgment module is used to output an over-resonance mode judgment signal to the logic processing module.

[0015] According to one embodiment of the present invention, the logic processing module is specifically used to generate a conduction signal with a high level indicating the conduction status of the rectifier tube according to the current zero-crossing comparison signal, the over-resonance mode judgment signal and the aligned primary drive signal.

[0016] According to an embodiment of the present invention, the compensation time calculation module includes a turn-off time detection module and a turn-off step adjustment module. The input end of the turn-off time detection module is connected to the output end of the drive signal generation module. The output end of the turn-off time detection module is connected to the input end of the turn-off step adjustment module. The output end of the turn-off step adjustment module is connected to the input end of the drive signal generation module.

[0017] The current zero-crossing comparison signals include a first current zero-crossing comparison signal and a second current zero-crossing comparison signal whose valid levels do not overlap and the sum of the duty cycles of the two valid levels is less than or equal to 1. The sampled drive signals include a first sampled drive signal and a second sampled drive signal whose valid levels do not overlap and the sum of the duty cycles of the two valid levels is less than or equal to 1.

[0018] The turn-off time detection module is configured to detect a first time length T1_ad of the high level of the first current zero-crossing comparison signal, a second time length T1_bc of the high level of the second current zero-crossing comparison signal, a third time length T2_ad from the rising edge of the first current zero-crossing comparison signal to the falling edge of the first sampled drive signal, and a fourth time length T2_bc from the rising edge of the second current zero-crossing comparison signal to the falling edge of the second sampled drive signal.

[0019] The turn-off step adjustment module is configured to calculate a first compensation time Δt_ad according to the difference ΔT_ad between the first time length T1_ad and the third time length T2_ad, and calculate a second compensation time Δt_bc according to the difference ΔT_bc between the second time length T1_bc and the fourth time length T2_bc.

[0020] According to an embodiment of the present invention, when the turn-off step adjustment module calculates the first compensation time Δt_ad according to the difference ΔT_ad between the first time length T1_ad and the third time length T2_ad, it specifically is used for:

[0021] When ΔT_ad > Tdrive_latency + Thyst, the value of Δt_ad is Δt_ad 上 + Tstep;

[0022] When ΔT_ad < Tdrive_latency, the value of Δt_ad is Δt_ad 上 + ΔT_ad - Tdrive_latency - Thyst;

[0023] When Tdrive_latency ≤ ΔT_ad ≤ Tdrive_latency + Thyst, the value of Δt_ad is Δt_ad 上 ;

[0024] Among them, the initial value of Δt_ad is 0, Δt_ad 上 It represents the Δt_ad value of the previous cycle, Tdrive_latency represents the hardware delay of the drive circuit, Tstep represents the step size of the step adjustment, and Thyst represents the hysteresis time.

[0025] According to an embodiment of the present invention, the rising edge of the driving signal is the same as the rising edge of the conduction signal, and the falling edge of the driving signal is a delay compensation time of the falling edge of the conduction signal.

[0026] The second embodiment of the present invention provides a power converter, which uses the compensation drive circuit of the power converter provided by the first embodiment of the present invention.

[0027] The technical solution of the embodiment of the present invention drives the rectifier tube according to the compensation time and the conduction signal, and can compensate for the delay caused by the driving circuit, so that the current of the rectifier output is balanced through the compensation drive. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 This is the topology diagram of the CLLC bidirectional converter.

[0029] Figure 2 4 is a structural block diagram of a compensation driving circuit of a power converter according to an embodiment of the present invention.

[0030] Figure 3 This is a flow chart of calculating the first compensation time according to an example of the present invention.

[0031] Figure 4 The flowchart of rising edge advance compensation according to an example of the present invention.

[0032] Figure 5 The figure is a schematic diagram of an over-resonance mode waveform of an example of the present invention.

[0033] Figure 6 FIG. 1 is a schematic diagram of a sub-resonance mode waveform according to an example of the present invention. DETAILED DESCRIPTION

[0034] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0035] The embodiments of the present invention can be applied to any power converter requiring synchronous rectification. Figure 1In the present invention, taking a CLLC bidirectional converter as an example, the present invention is applied to a high voltage output DC / DC converter.

[0036] like Figure 1 As shown in the figure, the bidirectional CLLC topology in the input-output parallel scenario, wherein Qpa1, Qpb1, Qpc1, Qpd1, Qpa2, Qpb2, Qpc2, Qpd2 are primary inverter network switch MOS; Qsa1, Qsb1, Qsc1, Qsd1, Qsa2, Qsb2, Qsc2, Qsd2 are secondary rectifier network switch MOS; CRp1, CRp2 are primary resonant capacitors; CRs1, CRs2: secondary resonant capacitors; LR1, LR2: resonant inductors; CTp1, CTp2: primary current transformers; CTp1, CTp2: secondary current transformers; T1, T2: resonant transformers; C1, C2: output filter capacitors; Vin: DC voltage source.

[0037] Figure 2 4 is a structural block diagram of a compensation driving circuit of a power converter according to an embodiment of the present invention.

[0038] like Figure 2 As shown, the compensation driving circuit of the power converter includes a compensation time calculation module 1, a driving signal generating module 2 and a driving circuit 3, the compensation time calculation module 1 is connected to the driving signal generating module 2, the output end of the driving signal generating module 2 is connected to the driving circuit 3, and the output end of the driving circuit 3 is connected to the rectifier tube ( Figure 2 connected to the substrate 100 (not shown).

[0039] The compensation time calculation module 1 is used to obtain a current zero-crossing comparison signal reflecting the conduction status of the rectifier tube on the output side of the power converter and a sampling drive signal of the rectifier bridge on the output side of the power converter, and calculate the compensation time based on the current zero-crossing comparison signal and the sampling drive signal; the drive signal generation module 2 is used to obtain a conduction signal represented by a high level to indicate the conduction status of the rectifier tube, generate a final drive signal based on the conduction signal and the compensation time, and output it to the drive circuit.

[0040] The current zero-crossing comparison signal includes a first current zero-crossing comparison signal Vsr_p and a second current zero-crossing comparison signal Vsr_n (the low level of Vsr_p indicates that the ad tube is turned on, and the high level of Vsr_n indicates that the bc tube is turned on), whose effective levels do not overlap and whose effective levels add up to a duty cycle of less than or equal to 1, and the conduction signal includes a first conduction signal Vg_ad and a second conduction signal Vg_bc (representing the drive signals of the ad tube and the bc tube before compensation, respectively), whose effective levels do not overlap and whose effective levels add up to a duty cycle of less than or equal to 1. The sampling drive signal includes a first sampling drive signal Vs_drive_ad1 and a second sampling drive signal Vs_drive_bc1 (representing the drive signals of the ad tube and the bc tube after compensation, respectively), whose effective levels do not overlap and whose effective levels add up to a duty cycle of less than or equal to 1.

[0041] Among them, AD tube refers to Figure 1 The rectifier tubes Qsa1, Qsa2, Qsd1, Qsd2, and bc tubes in the circuit are Figure 1 The effective level refers to the high level or low level when the current flows through. Taking the embodiment of the present invention as an example, the current sampling signal of the ad tube is actually effective at a low level, and the current sampling signal of the bc tube is actually effective at a high level.

[0042] The conduction signals Vg_ad and Vg_bc can be obtained according to the input current of the rectifier bridge at the output side of the power converter. Vs_drive_ad1 and Vs_drive_bc1 are obtained by sampling.

[0043] Specifically, the input current of the rectifier bridge on the output side of the power converter can be sampled, and the current zero-crossing comparison signal Vsr_p and Vsr_n whose effective levels do not overlap and whose effective level duty ratios are added together to be less than or equal to 1 can be obtained by comparing the current zero-crossing comparison; the drive signal of the rectifier tube of the rectifier bridge on the output side of the power converter can be sampled to obtain the sampling drive signals Vs_drive_ad1 and Vs_drive_bc1 whose effective levels do not overlap and whose effective level duty ratios are added together to be less than or equal to 1. The sampling is completed inside the FPGA, and the sampling clock cycle is 10ns. Vs_drive_ad is generated 10ns after Vs_drive_ad1 is sampled in the previous cycle. At the same time, the Vs_drive_ad of this cycle is used as the new Vs_drive_ad1 sampled in this cycle to generate the Vs_drive_ad of the next cycle.

[0044] The compensation time calculation module 1 calculates the first compensation time Δt_ad according to Vsr_p and Vs_drive_ad1 , calculates the second compensation time Δt_bc according to Vsr_n and Vs_drive_bc1 , and outputs Δt_ad and Δt_bc to the drive signal generation module 2 .

[0045] The drive signal generating module 2 obtains or receives the conduction signals Vg_ad and Vg_bc which are high level to indicate the conduction status of the rectifier tube, and generates the final first drive signal Vs_drive_ad according to Vg_ad and Δt_ad, and generates the final second drive signal Vs_drive_bc according to Vg_bc and Δt_bc.

[0046] The embodiment of the present invention calculates the compensation time according to the current zero-crossing comparison signal and the sampled drive signal, and generates a drive signal according to the compensation time and the conduction signal to perform compensation drive of the rectifier tube. It can meet the requirements of high voltage output of the rectifier, realize adaptive compensation correction of the offset of the drive signal caused by the delay of the drive circuit, and prevent the complementary oscillation of the parallel circuit current for the rectifier circuit with an output parallel structure. Therefore, when applied to the topology of the output parallel structure composed of wide bandgap devices, the current balance of the two rectifier outputs can be guaranteed.

[0047] Therefore, the compensation driving circuit of the power converter according to the embodiment of the present invention drives the rectifier tube according to the compensation time and the conduction signal, and can compensate for the delay caused by the driving circuit, and balance the current of the rectifier output through the compensation driving.

[0048] In one embodiment, referring to Figure 2 The compensation driving circuit of the power converter also includes a current sampling circuit 4 and a current zero-crossing comparison circuit 5. The input end of the current sampling circuit 4 is connected between the resonant capacitor on the output side of the power converter and the input end of the rectifier bridge, and the input end of the current zero-crossing comparison circuit 5 is connected to the output end of the current sampling circuit 4.

[0049] The current sampling circuit 4 is used to sample the input current of the rectifier bridge on the output side of the power converter and output a voltage signal proportional to the amplitude of the input current; the current zero-crossing comparison circuit 5 is used to compare the voltage signal with a preset threshold voltage to generate a current zero-crossing comparison signal reflecting the conduction status of the rectifier tube on the output side of the power converter.

[0050] Specifically, the current sampling circuit 3 samples the input current of the rectifier bridge at the output side of the power converter, and outputs a voltage signal Vi_sample proportional to the input current amplitude, and outputs it to the current zero-crossing comparison circuit 4 .

[0051] The zero-crossing current comparison circuit 4 compares the voltage signal Vi_sample with the preset threshold voltages Vth_on_p, Vth_off_p, Vth_on_n, and Vth_on_p to generate zero-crossing current comparison signals Vsr_p and Vsr_n that reflect the conduction conditions of the rectifier diodes on the output side of the power converter. Among them, Vth_on_p > Vth_off_p > 0; Vth_on_n < Vth_off_n < 0. Specifically:

[0052] When Vi_sample > Vth_on_p, Vsr_p output by the zero-crossing current comparison circuit 4 is at a low level;

[0053] When Vi_sample < Vth_off_p, Vsr_p output by the zero-crossing current comparison circuit 4 is at a high level;

[0054] When Vi_sample < Vth_on_n, Vsr_n output by the zero-crossing current comparison circuit 4 is at a high level;

[0055] When Vi_sample > Vth_off_n, Vsr_n output by the zero-crossing current comparison circuit 4 is at a low level.

[0056] In an example, referring to Figure 2 , the compensation drive circuit of the power converter further includes a logic processing module 6. The input end of the logic processing module 6 is connected to the output end of the zero-crossing current comparison circuit 5, and the output end of the logic processing module 6 is connected to the input end of the drive signal generation module 2. The logic processing module 6 is used to generate a conduction signal representing the conduction condition of the rectifier diode with a high level from the zero-crossing current comparison signal.

[0057] Further, referring to Figure 2 , the compensation drive circuit of the power converter further includes a primary drive signal sampling module 7, and its output end is connected to the input end of the logic processing module. The primary drive signal sampling module 7 is used to sample the primary drive signal of the sampling power converter, and after synchronously aligning the primary drive signal, output it to the logic processing module 6.

[0058] Referring to Figure 2 , the compensation drive circuit of the power converter further includes a resonant mode discrimination module 8, and its output end is connected to the input end of the logic processing module 6. The resonant mode discrimination module 8 is used to obtain a resonant mode discrimination signal and output it to the logic processing module 6.

[0059] Among them, both the resonant mode discrimination signal and the primary drive signal are input according to specific requirements.

[0060] Furthermore, the logic processing module 6 is specifically used to generate a conduction signal with a high level indicating the conduction status of the rectifier tube according to the current zero-crossing comparison signal, the over-resonance mode determination signal and the aligned primary drive signal.

[0061] Specifically, when the over-resonance mode discrimination signal is at a high level, the first conduction signal is inverted with the first current zero-crossing comparison signal, and the second conduction signal is in phase with the second current zero-crossing comparison signal; when the over-resonance mode discrimination signal is at a low level, the first conduction signal is the logical AND of the inverted signal of the first conduction signal and the aligned primary drive signal, and the second conduction signal is the logical AND of the in-phase signal of the second conduction signal and the aligned primary drive signal. That is:

[0062] When H_freq_mode is high, Vg_ad is in phase with Vsr_p, and Vg_bc is in phase with Vsr_n.

[0063] When H_freq_mode is low, Vg_ad takes the value of Vsr_p inverted and Vp_drv_ad to make a logical AND, and Vg_bc takes the value of Vsr_n in phase and Vp_drv_bc to make a logical AND.

[0064] In one embodiment, referring to Figure 2 The compensation time calculation module 1 includes a turn-off time detection module 11 and a turn-off step adjustment module 12. The input end of the turn-off time detection module 11 is connected to the output end of the drive signal generation module 2, the output end of the turn-off time detection module 11 is connected to the input end of the turn-off step adjustment module 12, and the output end of the turn-off step adjustment module 12 is connected to the input end of the drive signal generation module 2.

[0065] In one embodiment, referring to Figure 2 The compensation time calculation module 1 includes a turn-off time detection module 11 and a turn-off step adjustment module 12 .

[0066] Reference Figure 2 , the primary side driving signal sampling module 7, the logic processing module 6, the turn-off time detection module 11, the turn-off step adjustment module 12 and the driving signal generating module 2 are integrated into an FPGA (Field Programmable Gate Array) controller.

[0067] The input end of the off-time detection module 11 is connected to the output end of the driving signal generating module 2 , the output end of the off-time detection module 11 is connected to the input end of the off-step adjustment module 12 , and the output end of the off-step adjustment module 12 is connected to the input end of the driving signal generating module 2 .

[0068] The turn-off time detection module 11 is used to detect the first time length T1_ad of the high level of the first current zero-crossing comparison signal (assuming that the sampling signals are all high-level valid, representing that there is current flowing through the corresponding switching tube), the second time length T1_bc of the high level of the second current zero-crossing comparison signal, the third time length T2_ad from the rising edge of the first current zero-crossing comparison signal to the falling edge of the first sampling drive signal, and the fourth time length T2_bc from the rising edge of the second current zero-crossing comparison signal to the falling edge of the second sampling drive signal.

[0069] The turn-off step adjustment module 12 is used to calculate the first compensation time Δt_ad according to the difference ΔT_ad between the first time length T1_ad and the third time length T2_ad, and calculate the second compensation time Δt_bc according to the difference ΔT_bc between the second time length T1_bc and the fourth time length T2_bc.

[0070] Further, as Figure 3 shown, taking the calculation of the first compensation time Δt_ad in the current cycle as an example, the turn-off step adjustment module 12, when calculating the first compensation time Δt_ad according to the difference ΔT_ad between the first time length T1_ad and the third time length T2_ad, is specifically used for:

[0071] When ΔT_ad > Tdrive_latency + Thyst, the value of Δt_ad is Δt_ad 上 + Tstep;

[0072] When ΔT_ad < Tdrive_latency, the value of Δt_ad is Δt_ad 上 + ΔT_ad - Tdrive_latency - Thyst;

[0073] When Tdrive_latency ≤ ΔT_ad ≤ Tdrive_latency + Thyst, the value of Δt_ad remains unchanged, that is, Δt_ad = Δt_ad 上 ;

[0074] Among them, the initial value of Δt_ad is 0, Δt_ad 上 represents the value of Δt_ad in the previous cycle, and the calculation method of the value of Δt_ad in each cycle can be the same. Tdrive_latency represents the hardware delay of the drive circuit, Tstep represents the step size of the step adjustment, and Thyst represents the hysteresis time. Tdrive_latency = 200ns, Tstep = 10ns, Thyst = 100ns, and the values of Tdrive_latency, Tstep, and Thyst can be modified according to different circuit parameters.

[0075] The value of ΔT_bc is similar and will not be elaborated here.

[0076] In one embodiment, the rising edge of the driving signal is the same as the rising edge of the conduction signal, and the falling edge of the driving signal is delayed by the compensation time of the falling edge of the conduction signal.

[0077] Specifically, the final drive signal includes a first drive signal Vs_drive_ad and a second drive signal Vs_drive_bc, whose effective levels do not overlap and whose effective level duty ratios are summed to be less than or equal to 1. The first drive signal Vs_drive_ad is generated according to the first conduction signal Vg_ad and the first compensation time Δt_ad, and the second drive signal Vs_drive_bc is generated according to the second conduction signal Vg_bc and the second compensation time Δt_bc.

[0078] Take the generation of the first drive signal Vs_drive_ad as an example for explanation. The rising edge of Vs_drive_ad is the same as the rising edge of Vg_ad, and the falling edge of Vs_drive_ad is the falling edge of Vg_ad delayed by Δt_ad. That is, if Δt_ad>0, the falling edge of Vs_drive_ad is the falling edge of Vg_ad delayed by |Δt_ad|; if Δt_ad<0, the falling edge of Vs_drive_ad is the falling edge of Vg_ad advanced by |Δt_ad|.

[0079] Figure 4 The leading compensation of the rising edge is shown in Figure 4 As shown, in the over-resonance mode, i.e., when H_freq_mode=1, when the falling edge of the CT signal (conduction signal) corresponding to the rectifier tube ad (or bc) is detected, a delay of 100ns is made to send the rising edge of the synchronous rectification drive of the rectifier tube bc (or ad); in the under-resonance mode, the rising edge of the primary drive is sent and the corresponding rectifier tube drive rising edge is sent at the same time. Among them, the falling edge of the CT signal of the ad tube is the rising edge of Vsr_p, and the falling edge of the CT signal of the bc tube is the falling edge of Vsr_n.

[0080] The process of generating Vs_drive_bc is similar and will not be repeated here.

[0081] When the compensation driving circuit of the embodiment of the present invention is used for compensation driving, the waveforms in the over-resonance mode and the under-resonance mode are respectively as follows: Figure 5 , Figure 6 shown. Figure 5The various labels in the figure are as follows: ① According to the falling edge of the CT signal of the bc tube, a delay of 100ns is inserted; ② The driving falling edge leads the falling edge of the CT signal by 0ns, and the leading amount is less than 250ns. The sampling and logic delays are less than 30ns, which are not reflected in the figure; ③ The driving pulse width is reduced by 350+0ns. It is assumed that the driving falling edge leads the falling edge of the CT signal by 400ns, and the leading amount is greater than 350ns; ④ The driving pulse width is increased by 100ns. It is assumed that the driving falling edge leads the falling edge of the CT signal by 300ns, and the leading amount is greater than 250ns and less than 350ns; ⑤ The driving pulse width remains unchanged; ⑥ The hardware driving delay is 250ns; ⑦ The hardware driving delay is 250ns; ⑧ The driving falling edge lags behind the current zero crossing point.

[0082] Figure 6 The various labels in the figure are as follows: ① It is turned on at the same time as the primary side drive signal; ② The driving falling edge leads the falling edge of the CT signal by 0ns, and the leading amount is less than 250ns. The sampling and logic delays are less than 30ns, which are not reflected in the figure; ③ The driving pulse width is reduced by 350+0ns, and the falling edge leads the falling edge of the CT signal by 400ns, and the leading amount is greater than 350ns; ④ The driving pulse width is increased by 100ns, and the leading edge of the falling edge of the CT signal is assumed to be 300ns, and the leading amount is greater than 250ns and less than 350ns; ⑤ The driving pulse width remains unchanged; ⑥ The hardware drive delay is 250ns; ⑦ The hardware drive delay is 250ns; ⑧ The driving falling edge lags behind the current zero crossing point.

[0083] In summary, the embodiment of the present invention proposes a method for advanced sampling signal compensation driving, which compensates and corrects the synchronous driving signal offset caused by the delay of the driving circuit through an adaptive method. Its advantages are: the drive shutdown compensation is performed for the delay caused by the hardware driving circuit, and the anti-backflow capability is strong; it has the effect of suppressing current oscillation in the output parallel structure circuit using wide bandgap devices; the actual shutdown point is close to the current zero point, and the loss caused by early shutdown is low; it is not affected by the deviation of the circuit resonance parameters, and has strong adaptability to the output voltage.

[0084] An embodiment of the present invention provides a power converter, which uses the compensation driving circuit of the power converter.

[0085] The power converter of the embodiment of the present invention drives the rectifier tube according to the compensation time and the conduction signal through the compensation drive circuit of the above-mentioned power converter, and can also compensate for the delay caused by the drive circuit, so that the current of the rectifier output is balanced through the compensation drive.

[0086] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Although the embodiments of the present invention have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be construed as limitations on the present invention, and those of ordinary skill in the art can change, modify, replace and modify the above embodiments within the scope of the present invention.

Claims

1. A compensation driving circuit for a power converter, characterized in that: It includes a compensation time calculation module, a drive signal generation module and a drive circuit, wherein the compensation time calculation module is connected to the drive signal generation module, the output end of the drive signal generation module is connected to the drive circuit, and the output end of the drive circuit is connected to the rectifier tube of the rectifier bridge at the output side of the power converter, The compensation time calculation module is used to obtain a current zero-crossing comparison signal reflecting the conduction status of the rectifier tube at the output side of the power converter and a sampling drive signal of the rectifier bridge at the output side of the power converter, and calculate the compensation time according to the current zero-crossing comparison signal and the sampling drive signal; The driving signal generating module is used to obtain a conduction signal whose high level indicates the conduction status of the rectifier tube, generate a final driving signal according to the conduction signal and the compensation time, and output it to the driving circuit.

2. The compensation driving circuit of the power converter according to claim 1, characterized in that: It also includes a current sampling circuit and a current zero-crossing comparison circuit, wherein the input end of the current sampling circuit is connected between the resonant capacitor at the output side of the power converter and the input end of the rectifier bridge, and the input end of the current zero-crossing comparison circuit is connected to the output end of the current sampling circuit. The current sampling circuit is used to sample the input current of the rectifier bridge at the output side of the power converter and output a voltage signal proportional to the amplitude of the input current; The current zero-crossing comparison circuit is used to compare the voltage signal with a preset threshold voltage to generate a current zero-crossing comparison signal reflecting the conduction status of the rectifier tube at the output side of the power converter.

3. The compensation driving circuit of the power converter according to claim 2, characterized in that: It also includes a logic processing module, the input end of the logic processing module is connected to the output end of the current zero-crossing comparison circuit, the output end of the logic processing module is connected to the input end of the drive signal generating module, and the logic processing module is used to generate a conduction signal with a high level indicating the conduction status of the rectifier tube from the current zero-crossing comparison signal.

4. The compensation driving circuit of the power converter according to claim 3, characterized in that: It also includes a primary drive signal sampling module, whose output end is connected to the input end of the logic processing module. The primary drive signal sampling module is used to sample the primary drive signal of the power converter, and output the primary drive signal to the logic processing module after synchronous alignment.

5. The compensation driving circuit of the power converter according to claim 4, characterized in that: It also includes an over-resonance mode discrimination module, whose output end is connected to the input end of the logic processing module. The over-resonance mode determination module is used to output an over-resonance mode determination signal to the logic processing module.

6. The compensation driving circuit of the power converter according to claim 5, characterized in that: The logic processing module is specifically used for: A conduction signal is generated according to the current zero-crossing comparison signal, the over-resonance mode determination signal and the aligned primary drive signal, the conduction signal of the rectifier tube being represented by a high level.

7. The compensation driving circuit of the power converter according to claim 1, characterized in that: The compensation time calculation module includes a turn-off time detection module and a turn-off step adjustment module, wherein the input end of the turn-off time detection module is connected to the output end of the drive signal generation module, the output end of the turn-off time detection module is connected to the input end of the turn-off step adjustment module, and the output end of the turn-off step adjustment module is connected to the input end of the drive signal generation module. The current zero-crossing comparison signal includes a first current zero-crossing comparison signal and a second current zero-crossing comparison signal whose effective levels do not overlap and whose effective level duty ratios are added together to be less than or equal to 1, and the sampling drive signal includes a first sampling drive signal and a second sampling drive signal whose effective levels do not overlap and whose effective level duty ratios are added together to be less than or equal to 1. The off time detection module is used to detect a first time length T1_ad of a high level of the first current zero-crossing comparison signal, a second time length T1_bc of a high level of the second current zero-crossing comparison signal, a third time length T2_ad from a rising edge of the first current zero-crossing comparison signal to a falling edge of the first sampling drive signal, and a fourth time length T2_bc from a rising edge of the second current zero-crossing comparison signal to a falling edge of the second sampling drive signal; The shut-off step adjustment module is used to calculate the first compensation time Δt_ad according to the difference ΔT_ad between the first time length T1_ad and the third time length T2_ad, and calculate the second compensation time Δt_bc according to the difference ΔT_bc between the second time length T1_bc and the fourth time length T2_bc.

8. The compensation driving circuit of the power converter according to claim 7, characterized in that: The shut-off step adjustment module, when calculating the first compensation time Δt_ad according to the difference ΔT_ad between the first time length T1_ad and the third time length T2_ad, is specifically used to: When ΔT_ad>Tdrive_latency+Thyst, Δt_ad takes the value of Δt_ad 上 +Tstep; When ΔT_ad < Tdrive_latency, the value of Δt_ad is Δt_ad 上 + ΔT_ad - Tdrive_latency - Thyst; When Tdrive_latency≤ΔT_ad≤Tdrive_latency+Thyst, Δt_ad takes the value of Δt_ad 上 ; Among them, the initial value of Δt_ad is 0, Δt_ad 上 It represents the Δt_ad value of the previous cycle, Tdrive_latency represents the hardware delay of the drive circuit, Tstep represents the step size of the step adjustment, and Thyst represents the hysteresis time.

9. The compensation driving circuit of the power converter according to claim 1, characterized in that: The rising edge of the driving signal is the same as the rising edge of the conduction signal, and the falling edge of the driving signal is a delay compensation time of the falling edge of the conduction signal.

10. A power converter, characterized in that: A compensation drive circuit for a power converter using any one of claims 1 to 9.

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