Low-noise amplification chip, low-noise amplifier and radio frequency front-end module

Abstract

The invention provides a low-noise amplification chip, which comprises a chip, a first power supply port arranged on the chip, a control module, a low-noise amplification module and a first voltage stabilization unit, and is characterized in that the control module comprises an interface unit and a decoding unit; the first power supply port is connected to the power supply end of the interface unit and the power supply end of the decoding unit, the signal input end of the interface unit is configured to receive clock signals and data signals, and the signal output end of the interface unit is connected with the signal input end of the decoding unit. The decoding unit comprises a plurality of signal output ends, the plurality of signal output ends of the decoding unit are connected to the plurality of control ends in the low-noise amplification module, and the first voltage stabilizing unit is connected to a connection path between the first power supply port and the power supply end of the decoding unit; therefore, jittering of the control signal finally output to the low-noise amplification module by the decoding unit is avoided, and the noise performance of the low-noise amplification chip is improved.

Description

Technical Field

[0001] The present invention relates to the field of radio frequency technology, and in particular to a low-noise amplifier chip, a low-noise amplifier and a radio frequency front-end module. Background Art

[0002] With the rapid development of modern wireless communication technology, the performance requirements for RF front-end circuits are becoming higher and higher. As a key component of the front end of the RF receiver, the performance of the low noise amplifier directly affects the sensitivity and communication quality of the entire receiving system. However, in the design and application of low noise amplifiers, there are some problems that need to be solved. Summary of the invention

[0003] The purpose of the present invention is to provide a low noise amplifier chip, a low noise amplifier and a radio frequency front-end module to improve the poor noise performance of the low noise amplifier chip.

[0004] A low-noise amplifier chip comprises a chip, a first power supply port, a control module, a low-noise amplifier module and a first voltage stabilizing unit arranged on the chip, the control module comprises an interface unit and a decoding unit; the first power supply port is respectively connected to the power supply end of the interface unit and the power supply end of the decoding unit, the signal input end of the interface unit is configured to receive a clock signal and a data signal, the signal output end of the interface unit is connected to the signal input end of the decoding unit, the decoding unit comprises a plurality of signal output ends, the plurality of signal output ends of the decoding unit are connected to a plurality of control ends in the low-noise amplifier module, and the first voltage stabilizing unit is connected to the connection path between the first power supply port and the power supply end of the decoding unit.

[0005] A low-noise amplifier chip comprises a chip, a first power supply port, a control module, a low-noise amplifier module and a second voltage stabilizing unit arranged on the chip, the control module comprises an interface unit and a decoding unit; the first power supply port is respectively connected to the power supply end of the interface unit and the power supply end of the decoding unit, the signal input end of the interface unit is configured to receive a clock signal and a data signal, the signal output end of the interface unit is connected to the signal input end of the decoding unit, the decoding unit comprises a plurality of signal output ends, the plurality of signal output ends of the decoding unit are connected to a plurality of control ends in the low-noise amplifier module, and the second voltage stabilizing unit is connected to the connection path between the first power supply port and the power supply end of the interface unit.

[0006] A low-noise amplifier comprises a first power supply port, a control module, a low-noise amplifier circuit and a first voltage stabilizing unit, wherein the control module comprises an interface unit and a decoding unit; the first power supply port is respectively connected to a power supply end of the interface unit and a power supply end of the decoding unit, the signal input end of the interface unit is configured to receive a clock signal and a data signal, the signal output end of the interface unit is connected to the signal input end of the decoding unit, the decoding unit comprises a plurality of signal output ends, and the plurality of signal output ends of the decoding unit are connected to a plurality of switch units in the low-noise amplifier circuit to control the conduction or disconnection of the plurality of switch units; the first voltage stabilizing unit is connected to the connection path between the first power supply port and the power supply end of the decoding unit.

[0007] A radio frequency front-end module, a first power supply port, a control module, a switch module and a first voltage stabilizing unit, the control module comprising an interface unit and a decoding unit; the first power supply port is respectively connected to the power supply end of the interface unit and the power supply end of the decoding unit, the signal input end of the interface unit is configured to receive a clock signal and a data signal, the signal output end of the interface unit is connected to the signal input end of the decoding unit, the decoding unit comprises a plurality of signal output ends, the plurality of signal output ends of the decoding unit are connected to control ends corresponding to a plurality of different switch units in the switch module, and the first voltage stabilizing unit is connected to the connection path between the first power supply port and the power supply end of the decoding unit.

[0008] In the present embodiment, a low noise amplifier chip includes a chip, a first power supply port, a control module, a low noise amplifier module and a first voltage stabilizing unit arranged on the chip, the control module includes an interface unit and a decoding unit; the first power supply port is respectively connected to the power supply end of the interface unit and the power supply end of the decoding unit, the signal input end of the interface unit is configured to receive a clock signal and a data signal, the signal output end of the interface unit is connected to the signal input end of the decoding unit, the decoding unit includes a plurality of signal output ends, the plurality of signal output ends of the decoding unit are connected to a plurality of control ends in the low noise amplifier module, and the first voltage stabilizing unit is connected to the connection path between the first power supply port and the power supply end of the decoding unit; in the present embodiment, by connecting the first voltage stabilizing unit to the connection path between the first power supply port and the power supply end of the decoding unit, the first voltage stabilizing unit can block the voltage fluctuation output by the first power supply port, and can also filter the voltage fluctuation output by the first power supply port to the ground, so as to avoid the voltage fluctuation output by the first power supply port being transmitted to the power supply end of the decoding unit, thereby avoiding the control signal finally output by the decoding unit to the low noise amplifier module from jittering, thereby improving the noise performance of the low noise amplifier chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and, together with the description, serve to explain the principles of the invention. In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor. Figure 1 A schematic diagram of the structure of a low-noise amplifier chip of the present invention; Figure 2 Another structural schematic diagram of a low-noise amplifier chip of the present invention; Figure 3 Another structural schematic diagram of a low-noise amplifier chip of the present invention; Figure 4 Another structural schematic diagram of a low-noise amplifier chip of the present invention; Figure 5 Another structural schematic diagram of a low-noise amplifier chip of the present invention; Figure 6 A schematic diagram of the structure of a low noise amplifier of the present invention; Figure 7 A schematic diagram of the structure of the radio frequency front-end module of the present invention. DETAILED DESCRIPTION

[0010] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0011] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0012] In addition, the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0013] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0014] It should be noted that all directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of the present invention are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0015] In addition, the descriptions of "first", "second", etc. in the present invention are only used for descriptive purposes and cannot be understood as indicating or implying their relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in the field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0016] The low-noise amplifier chip provided in the embodiment of the present application can be applied to mobile phones, tablet computers, wearable devices, vehicle-mounted devices, laptop computers, and other terminal devices, and can also be applied to the RF front-end modules of these terminal devices. This embodiment does not impose any restrictions on the specific type of terminal devices.

[0017] This embodiment provides a low noise amplifier chip as follows Figure 1As shown, it includes a chip, a first power supply port, a control module, a low-noise amplification module and a first voltage stabilizing unit arranged on the chip, the control module includes an interface unit and a decoding unit; the first power supply port is respectively connected to the power supply end of the interface unit and the power supply end of the decoding unit, the first power supply port is configured to be connected to a first power supply, the signal input end of the interface unit is configured to receive a clock signal and a data signal, the signal output end of the interface unit is connected to the signal input end of the decoding unit, the decoding unit includes a plurality of signal output ends, the plurality of signal output ends of the decoding unit are connected to a plurality of control ends in the low-noise amplification module, and the first voltage stabilizing unit is connected to the connection path between the first power supply port and the power supply end of the decoding unit.

[0018] In at least one embodiment, the low-noise amplifier chip can be a chip of any process type such as SiGe HBT process, GaAspHEMT process, CMOS process, etc. The low-noise amplifier chip includes a chip 100, a first power supply port VIO, a control module 10, a low-noise amplifier module 20 and a voltage stabilizing unit arranged on the chip. Among them, the control module 10 can be used to control the working state of the low-noise amplifier module to ensure the normal operation of the low-noise amplifier module. For example: the control module 10 can control the on or off of the switch in the low-noise amplifier module 20 to selectively activate the amplification branch or bypass branch of a specific frequency band; it can also control the state of the bias circuit in the low-noise amplifier module 20, and dynamically adjust the gain of the low-noise amplifier module 20 to adapt to input signals of different strengths, etc. This embodiment can improve the integration of the circuit by integrating the control module 10 and the low-noise amplifier module 20 on a chip.

[0019] In at least one embodiment, the control module includes an interface unit and a decoding unit. The interface unit is also referred to as a MIPI (Mobile Industry Processor Interface) unit. The interface unit transmits clock signals and data signals by using two signal lines (SCLK and SDATA). In order to ensure that the interface unit drives the clock signals and data signals normally and that the decoding unit works normally, both the interface unit and the decoding unit need to be powered by a power supply (VIO). In this embodiment, the interface unit and the decoding unit share a first power supply. The power supply end of the interface unit and the power supply end of the decoding unit are both connected to a first power supply port on the chip, and the first power supply port is configured to be connected to the first power supply (VIO). The first power supply transmits the power supply voltage to the power supply end of the interface unit and the power supply end of the decoding unit through the first power supply port, and supplies power to the interface unit and the decoding unit to ensure that the interface unit and the decoding unit work normally. In this embodiment, the voltage transmitted by the first power supply VIO to the power supply end of the interface unit and the power supply end of the decoding unit can be a voltage of 1.8V. In at least one embodiment, the low noise amplifier chip is an insulating silicon chip.

[0020] In at least one embodiment, the decoding unit includes a plurality of signal output terminals, and the plurality of signal output terminals of the decoding unit are connected to a plurality of control terminals in the low noise amplification module. It should be noted that, in this embodiment, the number of signal output terminals of the decoding unit and the number of control terminals in the low noise amplification module may be the same or different. Each signal output terminal of the decoding unit may be connected to a corresponding control terminal in the low noise amplification module one by one, that is, many-to-many; each signal output terminal in the decoding unit may also be connected to a plurality of control terminals in the low noise amplification module, that is, one-to-many; the plurality of signal output terminals in the decoding unit may also be connected to a control terminal in the low noise amplification module, that is, many-to-one. The relationship between the plurality of signal output terminals of the decoding unit and the plurality of control terminals in the low noise amplification module may be a one-to-one relationship, a many-to-one relationship, or a one-to-many relationship.

[0021] In at least one embodiment, the decoding unit (Decoder) is a common digital logic circuit, and its function is to convert the input coded signal into a corresponding output signal through decoding and transmit it to the low noise amplifier module. The working principle of the decoding unit is to map the input signal of the signal input end to a specific output signal through a combinational logic circuit. Its core components include AND gates, OR gates and inverters. The decoding unit includes multiple signal output ends, each signal output end corresponds to outputting a control signal, and multiple signal output ends can output multiple control signals. Different control signals are independent of each other, and multiple different control signals are used to control multiple different control ends in the low noise amplifier module. For example: the decoding unit includes four signal output ends, and the four signal output ends correspond to outputting four control signals, which are 00, 10, 11, and 01 respectively. The four control signals (00, 10, 11, and 01) are used to control the control ends of four different switches in the low noise amplifier module to control the working states of the four different switches.

[0022] In at least one embodiment, the low noise amplifier chip further includes a first connecting wire and a second connecting wire, the first connecting wire is configured to connect the first power supply port and the power supply end of the decoding unit, and the second connecting wire is configured to connect the first power supply port and the power supply end of the interface unit. The first connecting wire can be equivalent to a first wire resistance, and the second connecting wire can be equivalent to a second wire resistance. The first wire resistance and the second wire resistance can also reduce the voltage fluctuation transmitted from the first power supply port to the power supply end of the decoding unit to a certain extent.

[0023] In a specific embodiment, since the two signal lines (SCLK and SDATA) at the input end of the interface unit for transmitting the clock signal and the data signal usually adopt an open-drain drive mode, the two signal lines (SCLK and SDATA) are pulled high by pull-up resistors. When the master device or the slave device actively pulls down the two signal lines (SCLK and SDATA), a dynamic current is generated, wherein the magnitude of the dynamic current is directly related to the frequency of the clock signal. The higher the frequency of the clock signal, the faster the signal switching rate, the higher the charge and discharge frequency, and the dynamic current also increases accordingly. In addition, during the data transmission of the clock signal and the data signal, since the clock signal and the data signal continuously switch the logic level (high / low), each level switching will cause the charging and discharging of the parasitic capacitance, resulting in transient current consumption; the higher the density of data signal transmission (that is, the more logic flips on the signal line), the greater the dynamic current consumption. When transmitting a large amount of commands and data, more current will be consumed, so that the interface unit will draw current from the first power supply port, which will cause the power supply voltage output by the first power supply port to produce voltage fluctuations, thereby affecting the normal operation of the decoding unit, so that the control signal finally output by the decoding unit to the low-noise amplifier module also jitters; resulting in deterioration of the noise performance of the low-noise amplifier, for example: the low-noise amplifier has a phenomenon of noise spikes at certain specific frequencies.

[0024] To this end, the present application connects a first voltage stabilizing unit on the connection path between the first power supply port and the power supply end of the decoding unit. The first voltage stabilizing unit can block the voltage fluctuations output by the first power supply port, and can also filter the voltage fluctuations output by the first power supply port to the ground, thereby avoiding the voltage fluctuations output by the first power supply port from being transmitted to the power supply end of the decoding unit, thereby avoiding jitter in the control signal that the decoding unit ultimately outputs to the low-noise amplifier module, thereby improving the noise performance of the low-noise amplifier chip.

[0025] In addition, by connecting the first voltage stabilizing unit to the connection path between the first power supply port and the power supply end of the decoding unit, compared with the technical solution in the related art that connects the voltage stabilizing unit to the path between the output end of the control module and the control end in the low-noise amplifier module, the present embodiment can solve the problem of deterioration of the noise performance of the low-noise amplifier with fewer voltage stabilizing units, and there is no need to connect the voltage stabilizing unit to each connection path between each output end of the control module and the corresponding control end in the low-noise amplifier module, which can greatly save the number of components and save costs.

[0026] In at least one embodiment, the first voltage stabilizing unit may include at least any one or combination of a capacitor unit, a resistor unit and an inductor unit. For example: the first voltage stabilizing unit includes a resistor unit, and the resistor unit is connected in series in the connection path between the first power supply port and the power supply end of the decoding unit. Alternatively, the first voltage stabilizing unit includes a capacitor unit, a first end of the capacitor unit is connected to the power supply end of the decoding unit, and a second end of the capacitor unit is grounded. Alternatively, the first voltage stabilizing unit may include a capacitor unit and a resistor unit, the resistor unit is connected in series in the connection path between the first power supply port and the power supply end of the decoding unit, the first end of the capacitor unit is connected to the power supply end of the decoding unit, and the second end of the capacitor unit is grounded.

[0027] In the present embodiment, a low noise amplifier chip includes a chip, a first power supply port, a control module, a low noise amplifier module and a first voltage stabilizing unit arranged on the chip, the control module includes an interface unit and a decoding unit; the first power supply port is respectively connected to the power supply end of the interface unit and the power supply end of the decoding unit, the signal input end of the interface unit is configured to receive a clock signal and a data signal, the signal output end of the interface unit is connected to the signal input end of the decoding unit, the decoding unit includes a plurality of signal output ends, the plurality of signal output ends of the decoding unit are connected to a plurality of control ends in the low noise amplifier module, and the first voltage stabilizing unit is connected to the connection path between the first power supply port and the power supply end of the decoding unit; in the present embodiment, by connecting the first voltage stabilizing unit to the connection path between the first power supply port and the power supply end of the decoding unit, the first voltage stabilizing unit can block the voltage fluctuation output by the first power supply port, and can also filter the voltage fluctuation output by the first power supply port to the ground, so as to avoid the voltage fluctuation output by the first power supply port being transmitted to the power supply end of the decoding unit, thereby avoiding the control signal finally output by the decoding unit to the low noise amplifier module from jittering, thereby improving the noise performance of the low noise amplifier chip.

[0028] In a specific embodiment, the first voltage stabilizing unit is configured to reduce voltage fluctuations transmitted to a power supply terminal of the decoding unit.

[0029] In at least one embodiment, since the interface unit draws current from the first power supply port during operation, the power supply voltage VIO has dynamic current consumption, which causes voltage fluctuations in the power supply voltage output by the first power supply voltage VIO and transmitted to the decoding unit through the first power supply port, thereby affecting the control signal output by the decoding unit to the low-noise amplifier module, resulting in the deterioration of the noise performance of the low-noise amplifier module. In view of this, the present embodiment connects the first voltage stabilizing unit to the connection path between the first power supply port and the power supply end of the decoding unit, and the first voltage stabilizing unit is configured to reduce the voltage fluctuation transmitted to the power supply end of the decoding unit, thereby reducing the jitter of the control signal output by the decoding unit to the low-noise amplifier module, thereby improving the noise performance of the low-noise amplifier chip.

[0030] In a specific embodiment, the first voltage stabilizing unit includes a first capacitor C1 , a first end of the first capacitor C1 is connected to a power supply end of the decoding unit, and a second end of the first capacitor C1 is grounded.

[0031] In at least one embodiment, the first capacitor C1 can be any type of capacitor unit such as a M0M capacitor, a MOS capacitor or an SMD capacitor. The first end of the first capacitor C1 is connected to the power supply end of the decoding unit, and the second end of the first capacitor is grounded. The first capacitor is configured to filter out the voltage fluctuation of the first power supply due to the influence of the interface unit to the ground, so that the power supply voltage output by the first power supply voltage VIO and transmitted to the decoding unit through the first power supply port is not doped with voltage fluctuations, thereby avoiding jitter in the control signal finally output by the decoding unit to the low-noise amplifier module, thereby improving the noise performance of the low-noise amplifier chip.

[0032] In a specific embodiment, the first voltage stabilizing unit includes a first resistor R1 , a first end of the first resistor R1 is connected to the first power supply port, and a second end of the first resistor is connected to the power supply end of the decoding unit.

[0033] In at least one embodiment, the first resistor R1 can be any type of resistor unit such as a polysilicon resistor, a metal resistor, etc. The first end of the first resistor R1 is connected to the first power supply port, and the second end of the first resistor is connected to the power supply end of the decoding unit. The first resistor is configured to block the voltage fluctuation of the first power supply caused by the influence of the interface unit from being transmitted to the decoding unit, so that the power supply voltage output by the first power supply voltage VIO and transmitted to the decoding unit through the first power supply port has no doped voltage fluctuation, thereby avoiding jitter of the control signal finally output by the decoding unit to the low-noise amplifier module, thereby improving the noise performance of the low-noise amplifier chip.

[0034] In a specific embodiment, the first voltage stabilizing unit includes a first capacitor C1 and a first resistor R1, the first end of the first capacitor is connected to the power supply end of the decoding unit, and the second end of the first capacitor is grounded; the first end of the first resistor R1 is connected to the first power supply port, and the second end of the first resistor is connected to the power supply end of the decoding unit; the first capacitor is configured to filter out voltage fluctuations of the first power supply due to the influence of the interface unit to the ground, and the first resistor is configured to block the voltage fluctuations of the first power supply due to the influence of the interface unit from being transmitted to the decoding unit; under the joint action of the first resistor and the first capacitor, the voltage fluctuations transmitted to the decoding unit can be more effectively filtered, thereby avoiding jitter in the control signal finally output by the decoding unit to the low-noise amplifier module, thereby improving the noise performance of the low-noise amplifier chip.

[0035] In a specific embodiment, the resistance of the first resistor is in the range of [5 ohms, 500 ohms].

[0036] In at least one embodiment, the resistance of the first resistor is in any at least one range of [5 ohms, 50 ohms], (50 ohms, 100 ohms], (100 ohms, 200 ohms], (200 ohms, 300 ohms], (300 ohms, 400 ohms], (400 ohms, 500 ohms], etc.

[0037] Preferably, the first resistor is a polysilicon resistor, so as to improve the stability of the circuit and achieve high-precision resistance value adjustment.

[0038] In a specific embodiment, the first capacitor is a MOM capacitor, and the capacitance of the first capacitor is in the range of [1pF, 10pF].

[0039] In at least one embodiment, the capacitance of the first capacitor is within any at least one range of [1pF, 3pF], (3pF, 5pF], (5pF, 8pF], (8pF, 10pF], etc.

[0040] Preferably, the first capacitor is a MOM capacitor. Since the first voltage stabilizing unit in this embodiment is integrated in the chip, the first capacitor is a MOM capacitor, which can reduce the occupied area while ensuring performance.

[0041] The first capacitor in this embodiment adopts an interdigital capacitor (MOM capacitor). Compared with the technical solution in the related art that connects the grounded capacitor to the path between the output end of the control module and the control end in the low-noise amplifier module, the first capacitor of this application adopts a MOM capacitor instead of a MIM capacitor, and the capacitance value of the first capacitor is in the range of [1pF, 10pF]. It should be noted that the capacitance value of the grounded capacitor connected to the path between the output end of the control module and the control end in the low-noise amplifier module in the related art needs to be less than 1pF, so it is usually implemented using a MIM capacitor. If the capacitance value of the grounded capacitor connected to the path between the output end of the control module and the control end in the low-noise amplifier module is greater than or equal to 1pF, the flipping of the output of the decoding unit will be slowed down, thereby causing the gear switching time of the low-noise amplifier module to be slowed down, thereby affecting the normal operation of the low-noise amplifier module. The present application connects a grounded first capacitor to the connection path between the first power supply port and the power supply end of the decoding unit. The first capacitor adopts an interdigital capacitor (MOM capacitor), and the capacitance of the first capacitor can be set in the range of [1pF, 10pF]. This can not only improve the noise performance of the low-noise amplifier chip, but also save the number of components and costs, and will not affect the gear switching time of the low-noise amplifier module.

[0042] In a specific embodiment, the low noise amplifier chip further includes a second voltage stabilizing unit, and the second voltage stabilizing unit is connected to the connection path between the first power supply port and the power supply end of the interface unit. Figure 3 shown.

[0043] In at least one embodiment, since the signal input end of the interface unit receives a data signal (DATA) and a clock signal (CLK), and the clock signal and the data signal continuously switch logic levels (high / low), the interface unit generates a noise signal (e.g., repeatedly draws current), and the noise signal leaks or flows back from the power supply end of the interface unit to the first power supply port, so that the first power supply connected to the first power supply port generates voltage fluctuations, thereby affecting the normal operation of the decoding unit. In view of this, the present application connects a second voltage stabilizing unit to the connection path between the first power supply port and the power supply end of the interface unit, and the second voltage stabilizing unit is configured to block the noise signal leaked from the interface unit to the first power supply port; thereby preventing the first power supply from generating a fluctuating voltage and affecting the normal operation of the decoding unit; thereby improving the noise performance of the low-noise amplifier chip.

[0044] In at least one embodiment, the second voltage stabilizing unit may adopt a circuit structure similar to that of the first voltage stabilizing unit. For example, the second voltage stabilizing unit may include at least any one or a combination of a capacitor unit, a resistor unit, and an inductor unit.

[0045] In a specific embodiment, the second voltage stabilizing unit includes a second capacitor, a first end of the second capacitor is connected to the power supply end of the interface unit, and a second end of the second capacitor is grounded. The second capacitor is configured to filter out the clutter signal generated by the interface unit to the ground.

[0046] In a specific embodiment, the second voltage stabilizing unit includes a second resistor, a first end of the second resistor is connected to the first power supply port, and a second end of the second resistor is connected to the power supply end of the interface unit. The second resistor is configured to block the clutter signal generated by the interface unit to prevent the clutter signal generated by the interface unit from flowing back or leaking to the first power supply port.

[0047] In a specific embodiment, the second voltage stabilizing unit includes a second capacitor and a second resistor, the first end of the second capacitor is connected to the power supply end of the interface unit, the second end of the second capacitor is grounded, the first end of the second resistor is connected to the first power supply port, and the second end of the second resistor is connected to the power supply end of the interface unit. The second capacitor is configured to filter the clutter signal generated by the interface unit to the ground, and the second resistor is configured to block the clutter signal generated by the interface unit. Under the joint action of the second capacitor and the second resistor, the clutter signal generated by the interface unit can be better blocked from flowing back or leaking to the first power supply port, so as to prevent the clutter signal generated by the interface unit from affecting the normal power supply of the first power supply to the decoding unit and the interface unit.

[0048] It should be noted that the implementation method of the second capacitor in this embodiment is similar to the implementation method of the first capacitor, and the implementation method of the second resistor is similar to the implementation method of the first resistor, which will not be redundantly described here.

[0049] In a specific embodiment, the low noise amplifier module includes a plurality of switch units, and a plurality of signal output terminals of the decoding unit are connected to a plurality of control terminals corresponding to the plurality of switch units to respectively control the on or off of the plurality of switch units.

[0050] In at least one embodiment, the low-noise amplification module includes a plurality of switch units. For example, the switch unit may be a switch unit in a bypass branch, a switch unit in an amplification branch, or any switch unit in a low-noise amplification module such as a switch unit in a gain adjustment circuit. Since the working states of the switch units at different connection positions in the low-noise amplification module are different, multiple independent control signals are required to respectively control the states of the corresponding switch units in the low-noise amplification module, that is, the multiple signal output ends of the decoding unit are respectively connected to the control ends of the corresponding switch units in the low-noise amplification module through multiple connection paths to meet the normal working requirements of the noise amplification module. In this embodiment, by connecting the first voltage stabilizing unit on the connection path between the first power supply port and the power supply end of the decoding unit, rather than connecting multiple first voltage stabilizing units on the connection path between the multiple signal output ends of the decoding unit and the corresponding control ends of the switch units in the low-noise amplification module, the noise performance of the low-noise amplifier can be improved, which greatly saves chip space and saves costs.

[0051] In a specific embodiment, as follows Figure 4 As shown, the multiple signal output ends of the decoding unit include a first signal output end and a second signal output end, the low-noise amplification module includes an amplification unit 301 and a bypass unit, the amplification unit 301 is connected between the RF input end and the RF output end, and is used to amplify the first RF signal input from the RF input end, the bypass unit is connected between the RF input end and the RF output end, the bypass unit includes a bypass switch S301 and a pull-down switch S302, the bypass switch S301 is connected in series between the RF input end and the RF output end, the first end of the pull-down switch S302 is connected to the bypass switch, and the second end of the pull-down switch S302 is grounded, the first signal output end of the decoding unit is connected to the control end of the bypass switch, and the second signal output end of the decoding unit is connected to the control end of the pull-down switch.

[0052] In at least one embodiment, the state of the bypass switch S301 and the state of the pull-down switch S302 are controlled by two independent control signals. The state of the bypass switch S301 is controlled by a first control signal output from a first signal output terminal of the decoding unit, and the state of the pull-down switch S302 is controlled by a second control signal output from a second signal output terminal of the decoding unit.

[0053] In at least one embodiment, the amplifying unit includes a first amplifying transistor and a second amplifying transistor, the base (gate) of the first amplifying transistor is connected to the signal input terminal, the collector (source) of the first amplifying transistor is connected to the emitter (drain) of the second amplifying transistor, and the emitter (drain) of the first amplifying transistor is grounded. The base (gate) of the second amplifying transistor is connected to the bias control terminal, the collector (source) is connected to the signal output terminal, and is connected to the feed power port VDD through a load inductor. In at least one embodiment, the feed voltage received by the feed power port VDD can be 1.2 voltage.

[0054] When the amplifying unit 301 is configured to be in a working state, the first control signal (00) outputted from the first signal output terminal of the decoding unit controls the bypass switch S301 to be disconnected, and the second control signal outputted from the second signal output terminal of the decoding unit controls the pull-down switch S302 to be closed (11); when the amplifying unit 301 is configured to be in a non-working state, the first control signal (11) outputted from the first signal output terminal of the decoding unit controls the bypass switch S301 to be closed, and the second control signal (00) outputted from the second signal output terminal of the decoding unit controls the pull-down switch S302 to be disconnected; in this embodiment, by connecting the first voltage stabilizing unit to the connection path between the first power supply port and the power supply terminal of the decoding unit, jitter of the first control signal outputted from the first signal output terminal of the decoding unit and the second control signal outputted from the second signal output terminal of the decoding unit can be effectively avoided, thereby improving the noise performance of the low-noise amplifier chip.

[0055] In a specific embodiment, as follows Figure 5As shown, the multiple signal output terminals of the decoding unit include a first signal output terminal, a second signal output terminal, a third signal output terminal and a fourth signal output terminal, the low-noise amplification module includes a first signal amplification unit and a second signal amplification unit, the first output node of the first signal amplification unit and the second output node of the second signal amplification unit are connected, the first signal amplification unit includes a first amplification transistor 201, a first switching switch S201 and a first isolation switch S203, and the second signal amplification unit includes a second amplification transistor 202, a second switching switch S202 and a second isolation switch S204. The first end of the first amplifying transistor is connected to the first end of the first switching switch and the first end of the first isolating switch; the second end of the first amplifying transistor is connected to the ground end, and the third end of the first amplifying transistor is connected to the first input node of the first signal amplifying unit; the second end of the first isolating switch is connected to the ground end, and the second end of the first switching switch is connected to the first output node of the first signal amplifying unit; the first end of the second amplifying transistor is connected to the first end of the second switching switch and the first end of the second isolating switch, the second end of the second amplifying transistor is connected to the ground end, the third end of the second amplifying transistor is connected to the second input node of the second signal amplifying unit, the second end of the second isolating switch is grounded, and the second end of the second switching switch is connected to the first output node of the first signal amplifying unit. The first signal output end of the decoding unit is connected to the control end of the first switching switch, the second signal output end of the decoding unit is connected to the control end of the first isolating switch, the third signal output end of the decoding unit is connected to the control end of the second switching switch, and the fourth signal output end of the decoding unit is connected to the control end of the second isolating switch.

[0056] In at least one embodiment, when the first signal amplifying unit is in a signal amplifying state and the second signal amplifying unit is in a shut-off state, the first control signal output from the first signal output end of the decoding unit controls the first switching switch to be turned on, the first control signal output from the second signal output end of the decoding unit controls the first isolating switch to be turned off, and the third control signal output from the third signal output end of the decoding unit controls the second switching switch to be turned off, and the fourth control signal output from the fourth signal output end of the decoding unit controls the second isolating switch to be turned on. Since the second switching switch is turned off, in an ideal state, no signal passes through the second signal amplifying unit, but since the switch is actually equivalent to a capacitor in the shut-off state, in actual application, the RF signal in the first signal amplifying unit will still leak into the second amplifying transistor through the second switching switch in the shut-off state, so that the second amplifying transistor is slightly in a slightly turned-on state. Therefore, by connecting a second isolating switch to the ground at the first end of the second amplifying transistor, and when the second switching switch is turned off, the second isolating switch is turned on, and the second isolating switch in the on state can pull the voltage of the first end of the second amplifying transistor to the ground potential end, so as to release the RF signal leaked from the first signal amplifying unit to the ground, prevent the signal in the first signal amplifying unit from leaking to the second amplifying transistor, thereby avoiding the phenomenon of micro-conduction of the second amplifying transistor, so as to improve the isolation between the first signal amplifying unit and the second signal amplifying unit, and further ensure the working stability of the first signal amplifying unit.

[0057] In at least one embodiment, when the second signal amplifying unit is in a signal amplifying state and the first signal amplifying unit is in an off state, a first control signal output from a first signal output terminal of the decoding unit controls the first switching switch to be turned off, a second control signal output from a second signal output terminal of the decoding unit controls the first isolating switch to be turned on, and a third control signal output from a third signal output terminal of the decoding unit controls the second switching switch to be turned on, and a fourth control signal output from a fourth signal output terminal of the decoding unit controls the second isolating switch to be turned off. Ideally, no signal passes through the first signal amplifying unit, but since the switch is actually equivalent to a capacitor in the off state, in actual application, the RF signal in the second signal amplifying unit will still leak into the first amplifying transistor through the first switching switch in the off state, causing the first amplifying transistor to be in a slightly turned-on state. By connecting a first isolating switch to the ground at the first end of the first amplifying transistor, and turning on the first isolating switch when the first switching switch is turned off, the first isolating switch in the turned-on state can pull the voltage of the first end of the first amplifying transistor to the ground potential end, so as to release the radio frequency signal leaked from the second signal amplifying unit to the ground, prevent the signal in the second signal amplifying unit from leaking to the first amplifying transistor, thereby avoiding the phenomenon of micro-conduction of the first amplifying transistor, so as to improve the isolation between the first signal amplifying unit and the second signal amplifying unit, and further ensure the working stability of the second signal amplifying unit.

[0058] This embodiment connects the first voltage stabilizing unit on the connection path between the first power supply port and the power supply end of the decoding unit, thereby effectively avoiding jitter of the first control signal output by the first signal output end of the decoding unit, the second control signal output by the second signal output end of the decoding unit, the third control signal output by the third signal output end of the decoding unit, and the fourth control signal output by the fourth signal output end of the decoding unit, thereby improving the noise performance of the low-noise amplifier chip.

[0059] The present application also provides a low noise amplifier chip, such as Figure 2 As shown, it includes a chip 100, a first power supply port, a control module 10, a low-noise amplification module 20 and a second voltage stabilizing unit arranged on the chip, the control module includes an interface unit and a decoding unit; the first power supply port is respectively connected to the power supply end of the interface unit and the power supply end of the decoding unit, the signal input end of the interface unit is configured to receive a clock signal and a data signal, the signal output end of the interface unit is connected to the signal input end of the decoding unit, the decoding unit includes a plurality of signal output ends, the plurality of signal output ends of the decoding unit are connected to a plurality of control ends in the low-noise amplification module, and the second voltage stabilizing unit is connected to the connection path between the first power supply port and the power supply end of the interface unit.

[0060] In at least one embodiment, since the signal input end of the interface unit receives a data signal (DATA) and a clock signal (CLK), and the clock signal and the data signal continuously switch logic levels (high / low), the interface unit generates a noise signal (e.g., repeatedly draws current), and the noise signal leaks or flows back from the power supply end of the interface unit to the first power supply port, so that the first power supply connected to the first power supply port generates voltage fluctuations, thereby affecting the normal operation of the decoding unit. In view of this, the present application connects a second voltage stabilizing unit to the connection path between the first power supply port and the power supply end of the interface unit, and the second voltage stabilizing unit is configured to block the noise signal leaked from the interface unit to the first power supply port; thereby preventing the first power supply from generating a fluctuating voltage and affecting the normal operation of the decoding unit; thereby improving the noise performance of the low-noise amplifier chip.

[0061] In a specific embodiment, the second voltage stabilizing unit includes a second capacitor, a first end of the second capacitor is connected to the power supply end of the interface unit, and a second end of the second capacitor is grounded. The second capacitor is configured to filter out the clutter signal generated by the interface unit to the ground.

[0062] In a specific embodiment, the second voltage stabilizing unit includes a second resistor, a first end of the second resistor is connected to the first power supply port, and a second end of the second resistor is connected to the power supply end of the interface unit. The second resistor is configured to block the clutter signal generated by the interface unit to prevent the clutter signal generated by the interface unit from flowing back or leaking to the first power supply port.

[0063] In a specific embodiment, the second voltage stabilizing unit includes a second capacitor and a second resistor, the first end of the second capacitor is connected to the power supply end of the interface unit, the second end of the second capacitor is grounded, the first end of the second resistor is connected to the first power supply port, and the second end of the second resistor is connected to the power supply end of the interface unit. The second capacitor is configured to filter the clutter signal generated by the interface unit to the ground, and the second resistor is configured to block the clutter signal generated by the interface unit. Under the joint action of the second capacitor and the second resistor, the clutter signal generated by the interface unit can be better blocked from flowing back or leaking to the first power supply port, so as to prevent the clutter signal generated by the interface unit from affecting the normal power supply of the first power supply to the decoding unit and the interface unit.

[0064] It should be noted that the implementation method of the second capacitor in this embodiment is similar to the implementation method of the first capacitor, and the implementation method of the second resistor is similar to the implementation method of the first resistor, which will not be redundantly described here.

[0065] The present application also provides a low noise amplifier, such as Figure 7 As shown, it includes a first power supply port, a control module, a low-noise amplifier circuit and a first voltage stabilizing unit, the control module includes an interface unit and a decoding unit; the first power supply port is respectively connected to the power supply end of the interface unit and the power supply end of the decoding unit, the signal input end of the interface unit is configured to receive a clock signal and a data signal, the signal output end of the interface unit is connected to the signal input end of the decoding unit, the decoding unit includes a plurality of signal output ends, and the plurality of signal output ends of the decoding unit are connected to a plurality of switch units in the low-noise amplifier circuit to control the conduction or disconnection of the plurality of switch units; the first voltage stabilizing unit is connected to the connection path between the first power supply port and the power supply end of the decoding unit.

[0066] In at least one embodiment, the control module and the low-noise amplifier circuit can be integrated on one chip, or they can be integrated on different chips. For example, the control module and the low-noise amplifier circuit are both integrated on a GaAs chip, or the control module is integrated on a CMOS chip, and the low-noise amplifier circuit is integrated on a GaAs chip.

[0067] In at least one embodiment, the first voltage stabilizing unit may be disposed on a substrate, or may be integrated with the control module on a chip.

[0068] In a specific embodiment, the invention further comprises a substrate, and a metal oxide semiconductor chip (CMOS chip), an insulator silicon chip (SOI chip) and a first voltage stabilizing unit arranged on the substrate; the control module is integrated on the metal oxide semiconductor chip (CMOS chip), and the low noise amplifier circuit is integrated on the insulator silicon chip (SOI chip.

[0069] In at least one embodiment, the low noise amplifier circuit generally includes a plurality of switch units, for example: a bypass switch and a pull-down switch in a bypass branch; an isolation switch and a switching switch in an amplifier branch; an adjustment switch in a gain adjustment circuit, etc. The working states of the switch units at different connection positions in the low noise amplifier module are different, so a plurality of independent control signals are required to respectively control the states of the corresponding switch units in the low noise amplifier module, that is, the plurality of signal output ends of the decoding unit are respectively connected to the control ends of the corresponding switch units in the low noise amplifier module through a plurality of connection paths to meet the normal working requirements of the noise amplifier module. In this embodiment, by connecting the first voltage stabilizing unit on the connection path between the first power supply port and the power supply end of the decoding unit, rather than connecting a plurality of first voltage stabilizing units on the connection path between the plurality of signal output ends of the decoding unit and the corresponding control ends of the switch units in the low noise amplifier module, the noise performance of the low noise amplifier can be improved, and the chip space and cost can be greatly saved.

[0070] In a specific embodiment, the first voltage stabilizing unit includes a first capacitor C1 , a first end of the first capacitor C1 is connected to a power supply end of the decoding unit, and a second end of the first capacitor C1 is grounded.

[0071] In at least one embodiment, the first capacitor C1 can be any type of capacitor unit such as a MOM capacitor, a MOS capacitor or an SMD capacitor. The first end of the first capacitor C1 is connected to the power supply end of the decoding unit, and the second end of the first capacitor is grounded. The first capacitor is configured to filter out the voltage fluctuation of the first power supply due to the influence of the interface unit to the ground, so that the power supply voltage output by the first power supply voltage VIO and transmitted to the decoding unit through the first power supply port is free of doped voltage fluctuations, thereby avoiding jitter in the control signal finally output by the decoding unit to the low-noise amplifier module, thereby improving the noise performance of the low-noise amplifier chip.

[0072] In a specific embodiment, the first voltage stabilizing unit includes a first resistor R1 , a first end of the first resistor R1 is connected to the first power supply port, and a second end of the first resistor is connected to the power supply end of the decoding unit.

[0073] In at least one embodiment, the first resistor R1 can be any type of resistor unit such as a polysilicon resistor, a metal resistor, etc. The first end of the first resistor R1 is connected to the first power supply port, and the second end of the first resistor is connected to the power supply end of the decoding unit. The first resistor is configured to block the voltage fluctuation of the first power supply caused by the influence of the interface unit from being transmitted to the decoding unit, so that the power supply voltage output by the first power supply voltage VIO and transmitted to the decoding unit through the first power supply port has no doped voltage fluctuation, thereby avoiding jitter of the control signal finally output by the decoding unit to the low-noise amplifier module, thereby improving the noise performance of the low-noise amplifier chip.

[0074] In at least one embodiment, the first voltage stabilizing unit includes a first capacitor C1 and a first resistor R1, the first end of the first capacitor is connected to the power supply end of the decoding unit, and the second end of the first capacitor is grounded; the first end of the first resistor R1 is connected to the first power supply port, and the second end of the first resistor is connected to the power supply end of the decoding unit; the first capacitor is configured to filter out voltage fluctuations of the first power supply due to the influence of the interface unit to the ground, and the first resistor is configured to block the voltage fluctuations of the first power supply due to the influence of the interface unit from being transmitted to the decoding unit; under the joint action of the first resistor and the first capacitor, the voltage fluctuations transmitted to the decoding unit can be more effectively filtered, thereby avoiding jitter in the control signal finally output by the decoding unit to the low-noise amplifier module, thereby improving the noise performance of the low-noise amplifier chip.

[0075] The present application also provides a radio frequency front-end module, such as Figure 7 As shown, a first power supply port, a control module 10, a switch module 30 and a first voltage stabilizing unit, the control module includes an interface unit and a decoding unit; the first power supply port is respectively connected to the power supply end of the interface unit and the power supply end of the decoding unit, the signal input end of the interface unit is configured to receive a clock signal and a data signal, the signal output end of the interface unit is connected to the signal input end of the decoding unit, the decoding unit includes a plurality of signal output ends, the plurality of signal output ends of the decoding unit are connected to the control ends corresponding to a plurality of different switch units in the switch module, and the first voltage stabilizing unit is connected to the connection path between the first power supply port and the power supply end of the decoding unit.

[0076] In at least one embodiment, the control module and the switch module may be integrated on one chip, or may be integrated on different chips. For example, the control module and the switch module are both integrated on an insulator silicon chip (SOI chip), or the control module is integrated on a metal oxide semiconductor chip (CMOS chip), and the switch module is integrated on an insulator silicon chip (SOI chip).

[0077] In at least one embodiment, the RF front-end module generally includes a plurality of different switch units. For example: a frequency band selection switch unit, an ASM switch unit or a tuning switch unit. The working states of the switch units at different connection positions in the RF front-end module are different, so a plurality of independent control signals are required to respectively control the states of the corresponding switch units, that is, the plurality of signal output ends of the decoding unit are respectively connected to the control ends of the corresponding switch units through a plurality of connection paths to meet the normal working requirements of the RF front-end module. In this embodiment, by connecting the first voltage stabilizing unit on the connection path between the first power supply port and the power supply end of the decoding unit, rather than connecting a plurality of first voltage stabilizing units on the connection path between the plurality of signal output ends of the decoding unit and the control end of the corresponding switch unit, the noise performance of the RF front-end module can be improved, thereby greatly saving chip space and cost.

[0078] In a specific embodiment, the first voltage stabilizing unit includes a first capacitor C1 , a first end of the first capacitor C1 is connected to a power supply end of the decoding unit, and a second end of the first capacitor C1 is grounded.

[0079] In at least one embodiment, the first capacitor C1 can be any type of capacitor unit such as a MOM capacitor, a MOS capacitor or an SMD capacitor. The first end of the first capacitor C1 is connected to the power supply end of the decoding unit, and the second end of the first capacitor is grounded. The first capacitor is configured to filter out the voltage fluctuation of the first power supply due to the influence of the interface unit to the ground, so that the power supply voltage output by the first power supply voltage VIO and transmitted to the decoding unit through the first power supply port is free of doped voltage fluctuations, thereby avoiding jitter in the control signal finally output by the decoding unit to the switch module, thereby improving the noise performance of the switch module.

[0080] In a specific embodiment, the first voltage stabilizing unit includes a first resistor R1 , a first end of the first resistor R1 is connected to the first power supply port, and a second end of the first resistor is connected to the power supply end of the decoding unit.

[0081] In at least one embodiment, the first resistor R1 can be any type of resistor unit such as a polysilicon resistor, a metal resistor, etc. The first end of the first resistor R1 is connected to the first power supply port, and the second end of the first resistor is connected to the power supply end of the decoding unit. The first resistor is configured to block the voltage fluctuation of the first power supply caused by the influence of the interface unit from being transmitted to the decoding unit, so that the power supply voltage output by the first power supply voltage VIO and transmitted to the decoding unit through the first power supply port is free of doped voltage fluctuations, thereby avoiding jitter in the control signal finally output by the decoding unit to the switch module, thereby improving the noise performance of the switch module.

[0082] In at least one embodiment, the first voltage stabilizing unit includes a first capacitor C1 and a first resistor R1, the first end of the first capacitor is connected to the power supply end of the decoding unit, and the second end of the first capacitor is grounded; the first end of the first resistor R1 is connected to the first power supply port, and the second end of the first resistor is connected to the power supply end of the decoding unit; the first capacitor is configured to filter out voltage fluctuations generated by the first power supply due to the influence of the interface unit to the ground, and the first resistor is configured to block the voltage fluctuations generated by the first power supply due to the influence of the interface unit from being transmitted to the decoding unit; under the joint action of the first resistor and the first capacitor, the voltage fluctuations transmitted to the decoding unit can be more effectively filtered, thereby avoiding jitter in the control signal finally output by the decoding unit to the switch module, thereby improving the noise performance of the switch module.

[0083] In a specific embodiment, the RF front-end module further includes a second voltage stabilizing unit, and the second voltage stabilizing unit is connected to a connection path between the first power supply port and a power supply end of the interface unit.

[0084] In at least one embodiment, since the signal input end of the interface unit receives a data signal (DATA) and a clock signal (CLK), and the clock signal and the data signal continuously switch logic levels (high / low), the interface unit generates a noise signal (for example, repeatedly drawing current), and the noise signal leaks or flows back from the power supply end of the interface unit to the first power supply port, so that the first power supply connected to the first power supply port generates voltage fluctuations, thereby affecting the normal operation of the decoding unit. In view of this, the present application connects a second voltage stabilizing unit to the connection path between the first power supply port and the power supply end of the interface unit, and the second voltage stabilizing unit is configured to block the noise signal leaked from the interface unit to the first power supply port; thereby avoiding the first power supply from generating a fluctuating voltage and affecting the normal operation of the decoding unit; thereby improving the noise performance of the RF front-end module.

[0085] In at least one embodiment, the second voltage stabilizing unit may adopt a circuit structure similar to that of the first voltage stabilizing unit. For example, the second voltage stabilizing unit may include at least any one or a combination of a capacitor unit, a resistor unit, and an inductor unit.

[0086] In a specific embodiment, the second voltage stabilizing unit includes a second resistor, and the second resistor is connected in series on a connection path between the first power supply port and a power supply end of the interface unit.

[0087] And / or, the voltage stabilizing unit includes a second capacitor, a first end of the second capacitor is connected to a connection path between the first power supply port and a power supply end of the interface unit, and a second end of the second capacitor is grounded.

[0088] In a specific embodiment, the second voltage stabilizing unit includes a second capacitor, a first end of the second capacitor is connected to the power supply end of the interface unit, and a second end of the second capacitor is grounded. The second capacitor is configured to filter out the clutter signal generated by the interface unit to the ground.

[0089] In a specific embodiment, the second voltage stabilizing unit includes a second resistor, a first end of the second resistor is connected to the first power supply port, and a second end of the second resistor is connected to the power supply end of the interface unit. The second resistor is configured to block the clutter signal generated by the interface unit to prevent the clutter signal generated by the interface unit from flowing back or leaking to the first power supply port.

[0090] In a specific embodiment, the second voltage stabilizing unit includes a second capacitor and a second resistor, the first end of the second capacitor is connected to the power supply end of the interface unit, the second end of the second capacitor is grounded, the first end of the second resistor is connected to the first power supply port, and the second end of the second resistor is connected to the power supply end of the interface unit. The second capacitor is configured to filter the clutter signal generated by the interface unit to the ground, and the second resistor is configured to block the clutter signal generated by the interface unit. Under the joint action of the second capacitor and the second resistor, the clutter signal generated by the interface unit can be better blocked from flowing back or leaking to the first power supply port, so as to prevent the clutter signal generated by the interface unit from affecting the normal power supply of the first power supply to the decoding unit and the interface unit.

[0091] It should be noted that the implementation method of the second capacitor in this embodiment is similar to the implementation method of the first capacitor, and the implementation method of the second resistor is similar to the implementation method of the first resistor, which will not be redundantly described here.

[0092] The foregoing is merely a specific embodiment of the present invention, which enables those skilled in the art to understand or implement the present invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features claimed herein.

Claims

1. A low noise amplifier chip, characterized in that: It includes: a chip, a first power supply port, a control module, a low-noise amplification module and a first voltage stabilizing unit arranged on the chip, the control module includes an interface unit and a decoding unit; the first power supply port is respectively connected to the power supply end of the interface unit and the power supply end of the decoding unit, the signal input end of the interface unit is configured to receive a clock signal and a data signal, the signal output end of the interface unit is connected to the signal input end of the decoding unit, the decoding unit includes multiple signal output ends, the multiple signal output ends of the decoding unit are connected to multiple control ends in the low-noise amplification module, and the first voltage stabilizing unit is connected to the connection path between the first power supply port and the power supply end of the decoding unit.

2. The low noise amplifier chip according to claim 1, characterized in that: The first voltage stabilizing unit is configured to reduce voltage fluctuation transmitted to a power supply terminal of the decoding unit.

3. The low noise amplifier chip according to claim 1, characterized in that: The first voltage stabilizing unit includes a first capacitor, a first end of the first capacitor is connected to the power supply end of the decoding unit, and a second end of the first capacitor is grounded.

4. The low noise amplifier chip according to claim 1 or 3, characterized in that: The first voltage stabilizing unit includes a first resistor, a first end of the first resistor is connected to the first power supply port, and a second end of the first resistor is connected to the power supply end of the decoding unit.

5. The low noise amplifier chip as claimed in claim 4, characterized in that: The resistance value of the first resistor is in the range of [5 ohms, 500 ohms].

6. The low noise amplifier chip as claimed in claim 3, characterized in that: The first capacitor is an interdigital capacitor, and the capacitance of the first capacitor is in the range of [1pF, 10pF].

7. The low noise amplifier chip according to claim 1, characterized in that: The low-noise amplifier chip further includes a second voltage stabilizing unit connected to a connection path between the first power supply port and a power supply end of the interface unit.

8. The low noise amplifier chip as claimed in claim 7, characterized in that: The second voltage stabilizing unit is configured to reduce a clutter signal leaked from the interface unit to the first power supply port.

9. The low noise amplifier chip as claimed in claim 7, characterized in that: The second voltage stabilizing unit includes a second capacitor, a first end of the second capacitor is connected to the power supply end of the interface unit, and a second end of the second capacitor is grounded.

10. The low noise amplifier chip according to claim 8 or 9, characterized in that: The second voltage stabilizing unit includes a second resistor, a first end of the second resistor is connected to the first power supply port, and a second end of the second resistor is connected to the power supply end of the interface unit.

11. The low noise amplifier chip according to claim 1, characterized in that: The low noise amplifier module includes a plurality of switch units, and a plurality of signal output terminals of the decoding unit are connected to a plurality of control terminals corresponding to the plurality of switch units to respectively control the on or off of the plurality of switch units.

12. The low noise amplifier chip according to claim 1, characterized in that: The multiple signal output ends of the decoding unit include a first signal output end and a second signal output end, the low-noise amplification module includes an amplification unit and a bypass unit, the amplification circuit is connected between the RF input end and the RF output end, and is used to amplify the first RF signal input from the RF input end, the bypass unit is connected between the RF input end and the RF output end, the bypass unit includes a bypass switch and a pull-down switch, the bypass switch is connected in series between the RF input end and the RF output end, the first end of the pull-down switch is connected to the bypass switch, and the second end of the pull-down switch is grounded, the first signal output end of the decoding unit is connected to the control end of the bypass switch, and the second signal output end of the decoding unit is connected to the control end of the pull-down switch.

13. The low noise amplifier chip according to claim 1, characterized in that: The multiple signal output terminals of the decoding unit include a first signal output terminal, a second signal output terminal, a third signal output terminal and a fourth signal output terminal. The low-noise amplification module includes a first signal amplification unit and a second signal amplification unit. The first output node of the first signal amplification unit is connected to the second output node of the second signal amplification unit. The first signal amplification unit includes a first amplification transistor, a first switching switch and a first isolation switch. The second signal amplification unit includes a second amplification transistor, a second switching switch and a second isolation switch. The first end of the first amplification transistor is connected to the first end of the first switching switch and the first end of the first isolation switch. The second end of the first amplification transistor is connected to the ground terminal, and the third end of the first amplification transistor is connected to the first input node of the first signal amplification unit. The second end of the first isolation switch is connected to the ground terminal. The second end of the first switching switch is connected to the first output node of the first signal amplifying unit; the first end of the second amplifying transistor is connected to the first end of the second switching switch and the first end of the second isolating switch, the second end of the second amplifying transistor is connected to the ground end, the third end of the second amplifying transistor is connected to the second input node of the second signal amplifying unit, the second end of the second isolating switch is grounded, the second end of the second switching switch is connected to the first output node of the first signal amplifying unit, the first signal output end of the decoding unit is connected to the control end of the first switching switch, the second signal output end of the decoding unit is connected to the control end of the first isolating switch, the third signal output end of the decoding unit is connected to the control end of the second switching switch, and the fourth signal output end of the decoding unit is connected to the control end of the second isolating switch.

14. The low noise amplifier chip according to claim 1, characterized in that: The low noise amplifier chip is an insulating silicon chip.

15. A low noise amplifier chip, characterized in that: The invention comprises: a chip, a first power supply port, a control module, a low-noise amplification module and a second voltage stabilization unit arranged on the chip, the control module comprising an interface unit and a decoding unit; the first power supply port is respectively connected to the power supply end of the interface unit and the power supply end of the decoding unit, the signal input end of the interface unit is configured to receive a clock signal and a data signal, the signal output end of the interface unit is connected to the signal input end of the decoding unit, the decoding unit comprises a plurality of signal output ends, the plurality of signal output ends of the decoding unit are connected to a plurality of control ends in the low-noise amplification module, and the second voltage stabilization unit is connected to the connection path between the first power supply port and the power supply end of the interface unit.

16. A low noise amplifier, characterized in that: include: A first power supply port, a control module, a low-noise amplifier circuit and a first voltage stabilizing unit, wherein the control module includes an interface unit and a decoding unit; The first power supply port is respectively connected to the power supply end of the interface unit and the power supply end of the decoding unit, the signal input end of the interface unit is configured to receive a clock signal and a data signal, the signal output end of the interface unit is connected to the signal input end of the decoding unit, the decoding unit includes a plurality of signal output ends, and the plurality of signal output ends of the decoding unit are connected to a plurality of switch units in the low-noise amplifier circuit to control the conduction or shutdown of the plurality of switch units; the first voltage stabilizing unit is connected to the connection path between the first power supply port and the power supply end of the decoding unit.

17. The low noise amplifier according to claim 16, wherein: The first voltage stabilizing unit comprises a first capacitor, a first end of the first capacitor is connected to the power supply end of the decoding unit, and a second end of the first capacitor is grounded; And / or, the first voltage stabilizing unit includes a first resistor, a first end of the first resistor is connected to the first power supply port, and a second end of the first resistor is connected to a power supply end of the decoding unit.

18. The low noise amplifier according to claim 16, wherein: It also includes a substrate, and a metal oxide semiconductor chip, an insulating silicon chip and a first voltage stabilizing unit arranged on the substrate; the control module is integrated on the metal oxide semiconductor chip, and the low-noise amplifier circuit is integrated on the insulating silicon chip.

19. A radio frequency front-end module, characterized in that: include: A first power supply port, a control module, a switch module and a first voltage stabilizing unit, wherein the control module includes an interface unit and a decoding unit; the first power supply port is respectively connected to the power supply end of the interface unit and the power supply end of the decoding unit, the signal input end of the interface unit is configured to receive a clock signal and a data signal, the signal output end of the interface unit is connected to the signal input end of the decoding unit, the decoding unit includes a plurality of signal output ends, the plurality of signal output ends of the decoding unit are connected to the control ends corresponding to a plurality of different switch units in the switch module, and the first voltage stabilizing unit is connected to the connection path between the first power supply port and the power supply end of the decoding unit.

20. The radio frequency front-end module according to claim 19, characterized in that: The first voltage stabilizing unit comprises a first resistor, and the first resistor is connected in series on a connection path between the first power supply port and the power supply end of the decoding unit; And / or, the voltage stabilizing unit includes a first capacitor, a first end of the first capacitor is connected to a connection path between the first power supply port and a power supply end of the decoding unit, and a second end of the first capacitor is grounded.

21. The radio frequency front-end module according to claim 19, characterized in that: The RF front-end module also includes a second voltage stabilizing unit, which is connected to a connection path between the first power supply port and a power supply end of the interface unit.

22. The radio frequency front-end module according to claim 21, characterized in that: The second voltage stabilizing unit comprises a second resistor, and the second resistor is connected in series on a connection path between the first power supply port and the power supply end of the interface unit; And / or, the voltage stabilizing unit includes a second capacitor, a first end of the second capacitor is connected to a connection path between the first power supply port and a power supply end of the interface unit, and a second end of the second capacitor is grounded.

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