Interrupt control method, device and equipment
By determining the interrupt suspend interval in the pulse width modulated pulse signal and suspending interrupts within the interval, the problem of inflexible interrupt triggering in the prior art is solved, and more efficient processor time utilization and accuracy of interrupt execution is achieved.
Patent Information
- Application Number
- CN202411559629.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-01
- Publication Date
- 2025-03-11
AI Technical Summary
In the prior art, the interrupt triggering of pulse width modulation pulses is not flexible enough, resulting in a poor time utilization of the processor.
By determining the interrupt suspend start and end values in the interrupt suspend register, the interrupt suspend interval is suspended within the interval, and the interrupt is executed in a time period outside the interval, thereby achieving flexible control of interrupt triggering.
Improves flexibility of interrupt triggering, enhances processor time utilization, and ensures accuracy and reliability of interrupt execution.
Smart Images
Figure CN119602763A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of pulse width modulation technology, and in particular to an interrupt control method, device and equipment. Background Art
[0002] At present, pulse width modulation is an analog control method that modulates the bias of the transistor base or MOS tube gate according to the change of the corresponding load to achieve the change of the transistor or MOS tube conduction time, thereby achieving the change of the output of the switching regulated power supply. This method can keep the output voltage of the power supply constant when the working conditions change, and is a very effective technology for controlling analog circuits using the digital signal of the microprocessor.
[0003] In the prior art, the existing PWM pulse generation mechanism is usually a counter that counts up or down or increases or decreases the count, compares the count value count with the first data in the comparison register, and implements a high and low level flip based on the comparison result, thereby realizing PWM pulse signals with different duty cycles.
[0004] However, in the prior art, the interrupt triggering of the pulse width modulation pulse is not flexible enough. Summary of the invention
[0005] The embodiments of the present application provide an interrupt control method, apparatus and device to achieve the effect of improving the flexibility of interrupt triggering.
[0006] In a first aspect, an embodiment of the present application provides an interrupt control method, including:
[0007] Generate a pulse width modulation pulse signal according to the count value of the counter and the first data pre-stored in the comparison register;
[0008] Determining an interrupt suspension interval in the pulse width modulation pulse signal according to an interrupt suspension start value and an interrupt suspension end value pre-stored in an interrupt suspension register;
[0009] The interrupt is suspended in the interrupt suspension interval, and the interrupt is executed in a time period outside the interrupt suspension interval in the pulse width modulation pulse.
[0010] The triggering of the interrupt and interrupt suspension is related to the counter that generates the pulse width modulation pulse signal, so the time of the interrupt and interrupt suspension triggering is more accurate.
[0011] In a possible implementation manner, the time period outside the interrupt suspension interval in the pulse width modulation pulse signal includes a first time period and a second time period;
[0012] The first time period is a time period between a start value of the counter and a start value of the interrupt suspension, and the second time period is a time period between an end value of the interrupt suspension and an automatic reload value of the counter.
[0013] In a possible implementation manner, executing an interrupt in a time period outside the interrupt suspension interval in the pulse width modulation pulse includes:
[0014] Interruptions are performed in the first time period and the second time period of the signal in the pulse width modulation pulse, respectively.
[0015] In a possible implementation, the driving circuit includes a plurality of switch circuits composed of a plurality of MOS tubes, the pulse width modulation pulse is used to control the opening and closing of the MOS tubes; the interruption includes current detection; the first data is between the interruption suspension start value and the interruption suspension end value; and the interruption is executed in a time period outside the interruption suspension interval in the pulse width modulation pulse signal, including:
[0016] Interruptions are respectively performed in the first time period and the second time period in the pulse width modulation pulse signal.
[0017] The current detection of the motor is suspended in the interrupt suspension interval and is executed in the first time period and the second time period respectively. This can avoid the interference current caused by the pulse width modulation pulse controlling the opening and closing of the MOS tube during the current detection, and the detection result is more reliable.
[0018] In a possible implementation, the method further includes:
[0019] Obtain a first setting request, and set other interrupts and execution time of the other interrupts according to the first setting request; wherein the execution time of the other interrupts is between the interrupt suspension start value and the interrupt suspension end value;
[0020] After suspending the interrupt in the interrupt suspension interval, the method further includes:
[0021] In the interrupt suspension interval, the other interrupt is executed according to the execution time of the other interrupt.
[0022] In a possible implementation manner, executing the other interrupts according to the execution time of the other interrupts within the interrupt suspension interval includes:
[0023] If multiple other interrupts are included, sorting the multiple other interrupts according to the priority of each other interrupt to obtain a sorted list of other interrupts;
[0024] In the interrupt suspension interval, other interrupts are executed in sequence according to the other interrupt list and the execution time of each other interrupt in the other interrupt list.
[0025] In a possible implementation, the method further includes:
[0026] Obtain a second setting request; wherein the second setting request is used to set an interrupt suspension start value and an interrupt suspension end value, and the setting request includes the interrupt suspension start value and the interrupt suspension end value;
[0027] If it is determined that the interrupt suspension start value is equal to the interrupt suspension end value, it is determined that the interrupt suspension interval is empty.
[0028] In a second aspect, an embodiment of the present application provides an interrupt control device, including:
[0029] An acquisition module, used for generating a pulse width modulation pulse signal according to the count value of the counter and the first data pre-stored in the comparison register;
[0030] A determination module, used to determine the interrupt suspension interval in the pulse width modulation pulse according to the interrupt suspension start value and the interrupt suspension end value pre-stored in the interrupt suspension register;
[0031] A suspend module, used for suspending interrupts within the interrupt suspending interval;
[0032] The first execution module is used to execute an interrupt in a time period outside the interrupt suspension interval in the pulse width modulation pulse.
[0033] In a possible implementation manner, the time period outside the interrupt suspension interval in the pulse width modulation pulse includes a first time period and a second time period;
[0034] The first time period is a time period between a start value of the counter and a start value of the interrupt suspension, and the second time period is a time period between an end value of the interrupt suspension and an automatic reload value of the counter.
[0035] In a possible implementation manner, the first execution module is specifically configured to:
[0036] Interruptions are respectively performed in the first time period and the second time period in the pulse width modulation pulse signal.
[0037] In a possible implementation manner, the device is further specifically used for:
[0038] Obtain a first setting request, and set other interrupts and execution time of the other interrupts according to the first setting request; wherein the execution time is between the interrupt suspension start value and the interrupt suspension end value;
[0039] The device also includes:
[0040] The second execution module is used for executing the other interrupts according to the execution time of the other interrupts within the interrupt suspension interval after suspending the interrupt within the interrupt suspension interval.
[0041] In a possible implementation manner, the second execution module is specifically configured to:
[0042] If multiple other interrupts are included, sorting the multiple other interrupts according to the priority of each other interrupt to obtain a sorted list of other interrupts;
[0043] In the interrupt suspension interval, other interrupts are executed in sequence according to the other interrupt list and the execution time of each other interrupt in the other interrupt list.
[0044] In a possible implementation manner, the device is further specifically used for:
[0045] Obtain a second setting request; wherein the second setting request is used to set an interrupt suspension start value and an interrupt suspension end value, and the setting request includes the interrupt suspension start value and the interrupt suspension end value;
[0046] If it is determined that the interrupt suspension start value is equal to the interrupt suspension end value, it is determined that the interrupt suspension interval is empty.
[0047] In a third aspect, an embodiment of the present application provides a microprocessor, wherein the microprocessor chip is used to execute the interrupt control method as described in the first aspect.
[0048] In a fourth aspect, an embodiment of the present application provides an electronic device, which is used to execute various possible implementations of the first aspect above.
[0049] In a fifth aspect, an embodiment of the present application provides a computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, they are used to implement the first aspect above and / or various possible implementations of the first aspect.
[0050] In a sixth aspect, an embodiment of the present application provides a computer program product, including a computer program, which, when executed by a processor, implements the above first aspect and / or various possible implementation methods of the first aspect.
[0051] The interrupt control method, device and equipment provided in the embodiment of the present application generate a pulse width modulated pulse signal according to the count value of the counter and the first data pre-stored in the comparison register. According to the interrupt suspension start value and the interrupt suspension end value in the interrupt suspension register, the interrupt suspension interval is determined in the pulse width modulated pulse signal. The interrupt is suspended within the interrupt suspension interval, and the interrupt is executed in the time period outside the interrupt suspension interval in the pulse width modulated pulse. In this scheme, the interrupt suspension interval is determined by the interrupt suspension start value and the interrupt suspension end value, and the continuous interrupt control is divided by the interrupt suspension interval, and the interrupt suspension and execution are realized according to the interrupt suspension interval, and the execution sequence of the interrupt suspension and execution is customized, and the free control of the interrupt execution is realized, so that the interrupt triggering is more flexible, and the flexibility of the interrupt triggering is improved. BRIEF DESCRIPTION OF THE DRAWINGS
[0052] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.
[0053] Figure 1 A flowchart of an interrupt control method provided by the present application;
[0054] Figure 2 A schematic diagram of a scenario of an interrupt control method provided by this application;
[0055] Figure 3 A schematic diagram of another interrupt control method provided by the present application;
[0056] Figure 4 A flowchart of another interrupt control method provided by the present application;
[0057] Figure 5 A schematic diagram of another interrupt control method provided by the present application;
[0058] Figure 6 A schematic diagram of another interrupt control method provided by the present application;
[0059] Figure 7 A schematic diagram of the structure of an interrupt control device provided by the present application;
[0060] Figure 8 A schematic diagram of the structure of another interrupt control device provided by the present application;
[0061] Fig. 9 A schematic diagram of the structure of an electronic device provided in this application.
[0062] The above drawings have shown clear embodiments of the present application, which will be described in more detail later. These drawings and text descriptions are not intended to limit the scope of the present application in any way, but to illustrate the concept of the present application to those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION
[0063] Here, exemplary embodiments will be described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Instead, they are only examples of devices and methods consistent with some aspects of the present application.
[0064] At present, pulse width modulation is an analog control method that modulates the bias of the transistor base or MOS tube gate according to the change of the corresponding load to achieve the change of the transistor or MOS tube conduction time, thereby achieving the change of the output of the switching regulated power supply. This method can keep the output voltage of the power supply constant when the working conditions change, and is a very effective technology for controlling analog circuits using the digital signal of the microprocessor.
[0065] In one example, the existing pulse width modulation pulse generation mechanism is usually a counter that counts up or down or increases or decreases the count, compares the count value count with the first data in the comparison register, and implements a high and low level flip according to the comparison result, thereby realizing a pulse width modulation pulse signal wave with different duty cycles. However, in the prior art, the interrupt triggering of the pulse width modulation pulse is not flexible enough.
[0066] In one example, when an interrupt is suspended, the processor is in an idle state. If the number of suspended interrupts is large or the time taken is long, poor time utilization of the processor will result.
[0067] In combination with the above-mentioned prior art, it can be known that in the prior art, there are technical problems such as insufficient flexibility in interrupt triggering and poor time utilization of the processor.
[0068] The interrupt control method provided by the present application determines the interrupt suspension interval through the interrupt suspension start value and the interrupt suspension end value, and divides the continuous interrupt control through the interrupt suspension interval, realizes interrupt suspension and execution according to the interrupt suspension interval, realizes customized adjustment of the execution timing of suspension and execution of interrupts, realizes free control of interrupt execution, makes interrupt triggering more flexible, and achieves the effect of improving the flexibility of interrupt triggering.
[0069] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.
[0070] Figure 1 A flowchart of an interrupt control method provided in this application is shown in FIG. Figure 1 As shown, the method includes:
[0071] Step S201, generating a pulse width modulation pulse signal according to the count value of the counter and the first data pre-stored in the comparison register.
[0072] For example, the execution subject of this embodiment may be an electronic device, or a terminal device, or an interrupt control device or device, or other devices or equipment that can execute this embodiment, and there is no limitation on this. In this embodiment, the execution subject is described as an electronic device.
[0073] First, the electronic device is provided with a counter, a comparison register and an interrupt suspension register. Among them, the counter can count according to the clock signal, and the counting method may include up counting, down counting or increasing and decreasing counting, etc. Up counting means that the count value starts from 0 and increases by 1 one by one. After the count value reaches the maximum value, the counter starts counting from 0 again; down counting means that the count value starts from the maximum value and decreases by 1 one by one. After the count value reaches 0, the counter starts counting from the maximum value again; increasing and decreasing counting means that the count value starts from 0 and increases by 1 one by one. After the count value reaches the maximum value, it decreases by 1 one by one.
[0074] The comparison register is used to store the first data, and output the pulse width modulation pulse signal according to the relationship between the count value and the first data. The interrupt suspension register is used to store the interrupt suspension start value sp1 and the interrupt suspension end value sp2. When the count value is between the interrupt suspension start value sp1 and the interrupt suspension end value sp2, the interrupt is suspended; when the count value is outside the interrupt suspension start value sp1 and the interrupt suspension end value sp2, the interrupt is executed.
[0075] In this step, the count value of the counter is obtained through a preset counting method, and the count value and the first data are compared through a comparison register. If the count value is equal to the first data, the current pulse width modulated pulse signal is flipped for the first time. If the count value reaches the automatic reload value, the counter counts again and flips the current pulse width modulated pulse signal for the second time. The flip can be a low level flip to a high level, or a high level flip to a low level, and there is no limitation on this.
[0076] Step S202: Determine an interrupt suspension interval in a pulse width modulation pulse according to an interrupt suspension start value sp1 and an interrupt suspension end value sp2 pre-stored in an interrupt suspension register.
[0077] Exemplarily, the interrupt suspension register stores the interrupt suspension start value sp1 and the interrupt suspension end value sp2. The electronic device directly determines the position corresponding to the interrupt suspension start value sp1 and the position corresponding to the interrupt suspension end value sp2 in the pulse width modulated pulse signal, and then determines that the interrupt suspension interval is between sp1 and sp2.
[0078] Step S203: Suspend the interruption within the interruption suspension interval, and execute the interruption in a time period outside the interruption suspension interval in the pulse width modulation pulse.
[0079] For example, taking upward counting as an example, according to the count value and the pre-stored first data, a pulse width modulation pulse signal is output as follows: Figure 2 As shown, Figure 2 A schematic diagram of a scenario of an interrupt control method provided in this application, according to Figure 2 It can be seen that when the count value is equal to the first data, the pulse width modulation pulse signal is inverted from a low level to a high level, and when the count value is equal to the automatic reload value, the pulse width modulation pulse signal is inverted from a high level to a low level. Figure 3 A schematic diagram of another interrupt control method provided by this application, such as Figure 3 As shown, when the count value is between the interrupt suspension start value sp1 and the interrupt suspension end value sp2, the interrupt is suspended. Figure 3 The interrupt status is indicated by a low level; when the count value is outside the interrupt suspension start value sp1 and the interrupt suspension end value sp2, the interrupt is executed. Figure 3 The interrupt status is represented by a high level.
[0080] The interrupt control method provided in the embodiment of the present application generates a pulse width modulated pulse signal according to the count value of the counter and the first data pre-stored in the comparison register. According to the interrupt suspension start value sp1 and the interrupt suspension end value sp2 pre-stored in the interrupt suspension register, the interrupt suspension interval is determined in the pulse width modulated pulse signal. The interrupt is suspended in the interrupt suspension interval, and the interrupt is executed in the time period outside the interrupt suspension interval in the pulse width modulated pulse. In this scheme, the interrupt suspension interval is determined by the interrupt suspension start value sp1 and the interrupt suspension end value sp2, and the continuous interrupt control is divided by the interrupt suspension interval, and the interrupt suspension and execution are realized according to the interrupt suspension interval, and the execution sequence of the interrupt suspension and execution is customized, and the free control of the interrupt execution is realized, so that the interrupt triggering is more flexible, and the effect of improving the flexibility of the interrupt triggering is achieved. In addition, the interrupt and interrupt suspension of this scheme are both related to the pulse width modulated pulse, and the effect of more precise interrupt execution is achieved.
[0081] Figure 4 A flowchart of another interrupt control method provided by this application is shown in FIG. Figure 4 As shown, in this embodiment Figure 1 Based on the embodiment, the interrupt control method is described in detail, and the method includes:
[0082] Step S301, generating a pulse width modulation pulse signal according to the count value of the counter and the first data pre-stored in the comparison register.
[0083] For example, this step can be referred to Figure 1 Step S201 in will not be repeated here.
[0084] Step S302, obtaining a second setting request; wherein the second setting request is used to set an interrupt suspension register interrupt suspension start value sp1 and an interrupt suspension end value sp2, and the setting request includes the interrupt suspension start value sp1 and the interrupt suspension end value sp2.
[0085] Exemplarily, the electronic device obtains a second setting request, the second setting request is used to set an interrupt suspension register interrupt suspension start value sp1 and an interrupt suspension end value sp2, and the setting request includes the interrupt suspension start value sp1 and the interrupt suspension end value sp2.
[0086] Step S303: If it is determined that the interrupt suspension start value sp1 is equal to the interrupt suspension end value sp2, it is determined that the interrupt suspension interval is empty.
[0087] Exemplarily, the electronic device directly updates the existing interrupt suspension start value sp1 and interrupt suspension end value sp2 according to the determined interrupt suspension start value sp1 and interrupt suspension end value sp2. If the updated interrupt suspension start value sp1 and interrupt suspension end value sp2 are equal, it is determined that the interrupt suspension interval is empty, that is, the interrupt suspension interval is cancelled.
[0088] Step S304: determine the interrupt suspension interval in the pulse width modulation pulse according to the interrupt suspension start value sp1 and the interrupt suspension end value sp2 in the interrupt suspension register.
[0089] For example, this step can be referred to Figure 1 Step S202 in will not be repeated here.
[0090] Step S305: Suspend the interrupt within the interrupt suspension interval.
[0091] Exemplarily, the electronic device may suspend an interrupt between the interrupt suspension sections sp1 and sp2.
[0092] Step S306 , obtaining a first setting request, and setting other interrupts and execution times of other interrupts according to the first setting request; wherein the execution time of other interrupts is between the interrupt suspension start value sp1 and the interrupt suspension end value sp2 .
[0093] For example, the interrupt suspension start value sp1 and the interrupt suspension end value sp2 can be customized, and the interrupt suspension interval can be used to execute new interrupts or other codes, and the new interrupt can run in the interrupt suspension interval. Therefore, the electronic device can trigger a new interrupt through the interrupt suspension start value sp1 and the interrupt suspension end value sp2 to adjust the timing relationship of different interrupts.
[0094] Step S307: Execute other interrupts in the interrupt suspension interval according to the execution time of other interrupts.
[0095] In one example, step S307 includes: if multiple other interrupts are included, sort the multiple other interrupts according to the priority of each other interrupt to obtain a sorted other interrupt list; within the interrupt suspension interval, execute the other interrupts in sequence according to the other interrupt list and the execution time of each other interrupt in the other interrupt list.
[0096] Exemplarily, interrupt suspension can be used to replace the code loop in interrupt execution, that is, in the time interval that needs to wait, the interrupt is suspended to execute other code solutions. Specifically, if multiple other interrupts to be executed are included, the multiple other interrupts are sorted according to the priority of each other interrupt to obtain a sorted list of other interrupts. In the interrupt suspension interval, other interrupts are executed in sequence according to the other interrupt list and the execution time of each other interrupt in the other interrupt list. If other interrupts with higher priority appear when an interrupt is being executed, the interrupt suspension can also be used to suspend the interrupt being executed, execute a new interrupt, and continue to execute the originally suspended interrupt after the new interrupt is executed. Therefore, by triggering a new interrupt in the interrupt suspension interval of the suspended interrupt, it is possible to improve the utilization of the processor and adjust the interrupt priority.
[0097] Step S308: Execute an interrupt in a time period outside the interrupt suspension interval in the pulse width modulation pulse.
[0098] In one example, the time period outside the interrupt suspension interval in the pulse width modulation pulse includes a first time period and a second time period; the first time period is the time period between the starting value of the counter and the interrupt suspension starting value sp1, and the second time period is the time period between the interrupt suspension end value sp2 and the automatic reload value of the counter.
[0099] In one example, step S308 includes: executing interruption in the first time period and the second time period of the pulse width modulation pulse respectively.
[0100] Exemplarily, the counter divides the high level of the pulse width modulation pulse signal into three sections for the interrupt suspension interval composed of the interrupt suspension start value sp1 and the interrupt suspension end value sp2 for counting up. The first time period is the time period between the counter start value and the interrupt suspension start value sp1, the second time period is the time period between the interrupt suspension end value sp2 and the automatic reload value of the counter, and the third time period is the time period between sp1 and sp2. It should be noted that the counter can also count down or increase or decrease. At this time, the first time period and the second time period refer to the above content and will not be repeated here.
[0101] Therefore, in order to better connect with the interrupt in the next cycle, some of the running code needs to run at the end of the pulse width modulation pulse signal cycle, that is, run in the second time period. For example, the rotor position control interrupt of the motor, the running code includes position application and position detection. Figure 5 A schematic diagram of another interrupt control method provided in this application, according to Figure 5 It can be seen that the position application is executed in the first time period and the position detection is executed in the second time period, so that the position detection can be closer to the control information of the next cycle, and then the pulse width modulation pulse of the next cycle can be generated. Therefore, the interrupt suspension function makes the position detection closer to the position application of the next cycle in time, making the motor control more accurate.
[0102] In another example, in order to avoid the error caused by current detection, it can be controlled by a device that can avoid the error, and there is no limitation on this. Here, motor control is used as an example for explanation. The motor usually includes a circuit composed of multiple MOS tube switches, and the motor is powered by the opening and closing of the MOS tube. When the multi-channel circuit is detected, the opening and closing moment of the MOS tube may cause the detected current to be unstable, so the current detection needs to avoid the opening and closing timing of the MOS tube. Therefore, the pre-stored first data needs to be set between the interrupt suspension start value sp1 and the interrupt suspension end value sp2, and the interrupt is executed in the first time period and the second time period in the pulse width modulation pulse signal, respectively. Figure 6 A schematic diagram of another interrupt control method provided in this application, according to Figure 6 It can be seen that the pulse width modulation pulse signal is used to control the opening and closing of the MOS tube. The interrupt suspension function is used to avoid current detection at the moment of opening and closing of the MOS tube. Therefore, the interrupt suspension function and the pulse width modulation pulse generation mechanism share a counter, which can make the timing of opening and closing of the MOS tube within the interrupt suspension interval, thereby ensuring that the current detection avoids the timing of the MOS tube switch.
[0103] The interrupt control method provided by the embodiment of the present application generates a pulse width modulated pulse signal according to the count value of the counter and the first data pre-stored in the comparison register. A second setting request is obtained, wherein the second setting request is used to set the interrupt suspension start value sp1 and the interrupt suspension end value sp2 in the interrupt suspension register, and the setting request includes the interrupt suspension start value sp1 and the interrupt suspension end value sp2. If it is determined that the interrupt suspension start value sp1 is equal to the interrupt suspension end value sp2, the interrupt suspension interval is determined to be empty, otherwise, according to the interrupt suspension start value sp1 and the interrupt suspension end value sp2 in the interrupt suspension register, the interrupt suspension interval is determined in the pulse width modulated pulse. Suspend the interrupt in the interrupt suspension interval. Obtain the first setting request, and set other interrupts and the execution time of other interrupts according to the first setting request; wherein the execution time of other interrupts is between the interrupt suspension start value sp1 and the interrupt suspension end value sp2. In the interrupt suspension interval, execute other interrupts according to the execution time of other interrupts. Execute the interrupt in the time period outside the interrupt suspension interval in the pulse width modulated pulse. In this scheme, the interrupt suspension interval is determined by the interrupt suspension start value sp1 and the interrupt suspension end value sp2, and the continuous interrupt control is divided by the interrupt suspension interval. Interrupt suspension and execution are realized according to the interrupt suspension interval, and the execution timing of the suspension and execution interrupts is customized. Free control of interrupt execution is realized, making interrupt triggering more flexible, thereby achieving the effect of improving the flexibility of interrupt triggering.
[0104] Figure 7 The schematic diagram of the structure of the interrupt control device provided by this application is as follows: Figure 7 As shown, the interrupt control device 40 provided in this embodiment includes:
[0105] The acquisition module 41 is used for the acquisition module, and is used to generate a pulse width modulation pulse signal according to the count value of the counter and the first data in the comparison register.
[0106] The determination module 42 is used to determine the interrupt suspension interval in the pulse width modulation pulse signal according to the interrupt suspension start value sp1 and the interrupt suspension end value sp2 in the interrupt suspension register.
[0107] The suspend module 43 is used to suspend the interrupt within the interrupt suspend interval.
[0108] The first execution module 44 is used to execute an interrupt in a time period outside the interrupt suspension interval in the pulse width modulation pulse.
[0109] The interrupt control device provided in this embodiment can execute the method provided in the above method embodiment. Its implementation principle and technical effect are similar, and this embodiment will not be described in detail here.
[0110] Figure 8A schematic diagram of another device structure provided in an embodiment of the present application, in Figure 7 Based on the embodiment shown, Figure 8 As shown, the time period outside the interrupt suspension interval in the pulse width modulation pulse includes a first time period and a second time period.
[0111] The first time period is a time period between the start value of the counter and the interrupt suspension start value sp1, and the second time period is a time period between the interrupt suspension end value sp2 and the automatic reload value of the counter.
[0112] In a possible implementation, the first execution module 44 is specifically configured to:
[0113] Interruptions are respectively performed in the first time period and the second time period in the pulse width modulation pulse.
[0114] In a possible implementation, the motor includes a circuit composed of multiple MOS tube switches, and the interrupt includes current detection of the circuit of the motor; the pre-stored first data is located between the interrupt suspension start value sp1 and the interrupt suspension end value sp2.
[0115] The first execution module 44 is specifically used for:
[0116] Interruptions are respectively performed in the first time period and the second time period in the pulse width modulation pulse signal.
[0117] In a possible implementation, the device is further specifically used for:
[0118] A first setting request is obtained, and other interrupts and execution times of other interrupts are set according to the first setting request; wherein the execution time of the other interrupts is between an interrupt suspension start value sp1 and an interrupt suspension end value sp2.
[0119] The device also includes:
[0120] The second execution module 45 is used for executing other interrupts according to the execution time of other interrupts within the interrupt suspension interval after suspending the interrupt within the interrupt suspension interval.
[0121] In a possible implementation, the second execution module 45 is specifically configured to:
[0122] If multiple other interrupts are included, the multiple other interrupts are sorted according to the priority of each other interrupt to obtain a sorted other interrupt list.
[0123] In the interrupt suspension interval, other interrupts are executed in sequence according to other interrupt lists and the execution time of each other interrupt in the other interrupt lists.
[0124] In a possible implementation, the device is further specifically used for:
[0125] A second setting request is obtained; wherein the second setting request is used to set an interrupt suspension start value sp1 and an interrupt suspension end value sp2, and the setting request includes the interrupt suspension start value sp1 and the interrupt suspension end value sp2.
[0126] If it is determined that the interrupt suspension start value sp1 is equal to the interrupt suspension end value sp2, it is determined that the interrupt suspension interval is empty.
[0127] In one example, the present application provides a microprocessor, which includes the microprocessor chip of the above solution. The microprocessor chip can be, for example, an MCU, DSP, MPU, micro CPU, etc., which can process digital signals, analog signals, or perform signal control functions, instruction processing and calculation functions, etc., a micro central control chip, an on-chip system chip, etc., without limitation.
[0128] Fig. 9 This is a schematic diagram of the structure of an electronic device provided in this application. Fig. 9 As shown, the electronic device 50 provided in this embodiment includes: at least one processor 501 and a memory 502. Optionally, the device 50 also includes a communication component 503. The processor 501, the memory 502 and the communication component 503 are connected via a bus 504.
[0129] In a specific implementation process, at least one processor 501 executes the computer-executable instructions stored in the memory 502, so that at least one processor 501 executes the above method.
[0130] The specific implementation process of the processor 501 can be found in the above method embodiment, and its implementation principle and technical effect are similar, so this embodiment will not be repeated here.
[0131] In the above embodiments, it should be understood that the processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), etc. A general-purpose processor may be a microprocessor or any conventional processor. The steps of the method disclosed in the invention may be directly implemented as being executed by a hardware processor, or may be executed by a combination of hardware and software modules in the processor.
[0132] The memory may include a high-speed memory (Random Access Memory, RAM), and may also include a non-volatile memory (Non-volatile Memory, NVM), such as at least one disk memory.
[0133] The bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, or an Extended Industry Standard Architecture (EISA) bus, etc. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, the bus in the drawings of the present application is not limited to only one bus or one type of bus.
[0134] The present application also provides a computer program product, including a computer program, which implements the above method when executed by a processor.
[0135] The present application also provides a computer-readable storage medium, in which computer-executable instructions are stored. When a processor executes the computer-executable instructions, the above method is implemented.
[0136] The above-mentioned readable storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as static random access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk or optical disk. The readable storage medium can be any available medium that can be accessed by a general or special-purpose computer.
[0137] An exemplary readable storage medium is coupled to a processor so that the processor can read information from the readable storage medium and write information to the readable storage medium. Of course, the readable storage medium can also be a component of the processor. The processor and the readable storage medium can be located in an application specific integrated circuit (Application Specific Integrated Circuits, referred to as: ASIC). Of course, the processor and the readable storage medium can also exist in the device as discrete components.
[0138] The division of units is only a logical function division, and there may be other divisions in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interface, device or unit, which can be electrical, mechanical or other forms.
[0139] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
[0140] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
[0141] If the function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods of each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.
[0142] Those skilled in the art can understand that all or part of the steps of implementing the above-mentioned method embodiments can be completed by hardware related to program instructions. The aforementioned program can be stored in a computer-readable storage medium. When the program is executed, the steps of the above-mentioned method embodiments are executed; and the aforementioned storage medium includes: ROM, RAM, disk or optical disk and other media that can store program codes.
[0143] Finally, it should be noted that those skilled in the art will readily conceive of other embodiments of the present invention after considering the specification and practicing the invention disclosed herein. The present invention is intended to cover any variations, uses or adaptations of the present invention, which follow the general principles of the present invention and include common knowledge or customary technical means in the art not disclosed by the present invention, are not limited to the precise structure described above and shown in the drawings, and may be modified and changed in various ways without departing from the scope thereof. The scope of the present invention is limited only by the appended claims.
Claims
1. An interrupt control method, characterized in that: include: Generate a pulse width modulation pulse signal according to the count value of the counter and the first data pre-stored in the comparison register; Determining an interrupt suspension interval in the pulse width modulation pulse signal according to an interrupt suspension start value and an interrupt suspension end value pre-stored in an interrupt suspension register; The interrupt is suspended within the interrupt suspension interval, and the interrupt is executed during a time period outside the interrupt suspension interval in the pulse width modulation pulse signal.
2. The method according to claim 1, characterized in that The time period outside the interrupt suspension interval in the pulse width modulation pulse includes a first time period and a second time period; The first time period is a time period between a start value of the counter and a start value of the interrupt suspension, and the second time period is a time period between an end value of the interrupt suspension and an automatic reload value of the counter.
3. The method according to claim 2, characterized in that During a time period outside the interrupt suspension interval in the pulse width modulation pulse, an interrupt is executed, comprising: Interruptions are respectively performed in the first time period and the second time period in the pulse width modulation pulse signal.
4. The method according to claim 2, characterized in that: The driving circuit includes a plurality of switch circuits composed of a plurality of MOS tubes, and the pulse width modulation pulse is used to control the opening and closing of the MOS tubes; the interruption includes current detection; the first data is between the interrupt suspension start value and the interrupt suspension end value; Executing an interrupt in a time period outside the interrupt suspension interval in the pulse width modulation pulse signal includes: Interruptions are respectively performed in the first time period and the second time period in the pulse width modulation pulse signal.
5. The method according to claim 1, characterized in that The method further comprises: Obtain a first setting request, and set other interrupts and execution time of the other interrupts according to the first setting request; wherein the execution time of the other interrupts is between the interrupt suspension start value and the interrupt suspension end value; After suspending the interrupt in the interrupt suspension interval, the method further includes: In the interrupt suspension interval, the other interrupt is executed according to the execution time of the other interrupt.
6. The method according to claim 5, characterized in that Executing the other interrupts according to the execution time of the other interrupts within the interrupt suspension interval includes: If multiple other interrupts are included, sorting the multiple other interrupts according to the priority of each other interrupt to obtain a sorted other interrupt list; In the interrupt suspension interval, other interrupts are executed in sequence according to the other interrupt list and the execution time of each other interrupt in the other interrupt list.
7. The method according to any one of claims 1 to 6, characterized in that: The method further comprises: Obtain a second setting request; wherein the second setting request is used to set an interrupt suspension start value and an interrupt suspension end value, and the setting request includes the interrupt suspension start value and the interrupt suspension end value; If it is determined that the interrupt suspension start value is equal to the interrupt suspension end value, it is determined that the interrupt suspension interval is empty.
8. An interruption control device, characterized in that: include: An acquisition module, used for generating a pulse width modulation pulse signal according to the count value of the counter and the first data pre-stored in the comparison register; A determination module, configured to determine an interrupt suspension interval in the pulse width modulation pulse according to an interrupt suspension start value and an interrupt suspension end value in an interrupt suspension register; A suspend module, used for suspending interrupts within the interrupt suspending interval; The first execution module is used to execute an interrupt in a time period outside the interrupt suspension interval in the pulse width modulation pulse.
9. A microprocessor, characterized in that: The microprocessor chip is used to execute the interrupt control method as described in claims 1-7 above.
10. An electronic device, characterized in that: The electronic device is used to execute the method as described in any one of claims 1 to 7 above.