ATE equipment high-speed AC signal calibration system and method

Abstract

The invention relates to the technical field of semiconductor detection, and discloses an ATE equipment high-speed AC signal calibration system and method, and the system comprises at least one FPGA module which is provided with a plurality of channels for bidirectional signal transmission; each PE module is correspondingly positioned on one channel of the FPGA and is used for receiving the driving signal output by the FPGA and an external input signal and sending a feedback signal to the FPGA module according to the driving signal; the signal calibration module is located in the FPGA and used for receiving the feedback signals and comparing time delays between the feedback signals input from different channels; the delay compensation module is positioned in the FPGA and is configured to adjust the time delay of each channel based on the comparison result of the signal calibration module so as to realize the synchronization of the signals of the plurality of channels; and when a plurality of FPGAs exist, the system also comprises a PLL module, and the PLL module is configured to provide synchronous clock signals with the same frequency and fixed phase to the plurality of FPGAs at the same time, so as to ensure that the internal clocks of the FPGAs are synchronous.

Description

Technical Field

[0001] The present application relates to the field of semiconductor testing technology, and in particular to a high-speed AC signal calibration system and method for ATE equipment. Background Art

[0002] ATE (Automatic Test Equipment) is an automatic test equipment, which is a system that performs automated testing on integrated circuits through computing combined with special equipment. Semiconductor chip testing ATE is used to detect the integrity of integrated circuit functions and performance, and is an important equipment to ensure the quality of integrated circuits in the integrated circuit manufacturing process.

[0003] High-speed signal calibration of traditional ATE equipment is basically implemented using TDC (Time-to-digital converters) chips. This measurement method is difficult to commercialize in large ATE systems because the external circuit of this method is complex and too many TDC chips cannot be placed on the tester head when the tester system is large. At the same time, this method relies on the measurement accuracy of the TDC chip, which introduces the measurement error of the TDC chip itself. In addition, in this method, the calibrated link is to the location of the TDC chip, which is different from the link in the actual usage scenario, and requires strict equal length in the design, which is difficult to achieve.

[0004] With the continuous development of integrated circuits, the integration scale and types of integrated circuits are constantly increasing, which makes the testing requirements of integrated circuits constantly changing. It is very common for large-scale SOC (System on Chip) testers to require thousands of communication high-speed signals for alignment. Therefore, there is an urgent need for a technical solution that can be used for complex ATE systems to calibrate AC signals with high precision. Summary of the invention

[0005] In view of the defects in the prior art, the present application proposes a high-speed AC signal calibration system and method for ATE equipment. Through the signal calibration module and delay compensation module integrated in the FPGA, the calibration module receives and compares the time delay of the feedback signal of each channel, and the delay compensation module makes adjustments according to the time delay of different channels. The calibration system of this embodiment uses the links and measurement paths required in the actual test process, does not increase the cumulative error, and eliminates the system error. At the same time, it avoids the introduction of the TDC chip, thereby eliminating the measurement error of the TDC chip itself. The calibration link and the actual test link are of equal length, which avoids the need to re-design the equal length of the link after the introduction of the TDC chip, thereby reducing the complexity of the system design.

[0006] To solve the above problems, on the one hand, the present application provides a high-speed AC signal calibration system for ATE equipment, the system comprising:

[0007] at least one FPGA module having a plurality of channels for bidirectionally transmitting signals;

[0008] Multiple PE modules, each PE module is located on a channel of the FPGA, and is used to receive a driving signal output by the FPGA, and send a feedback signal to the FPGA module according to the driving signal;

[0009] A signal calibration module, located inside the FPGA, is used to receive feedback signals and compare the time delays between feedback signals fed back from different channels;

[0010] The delay compensation module, located inside the FPGA, is configured to adjust the time delay of each channel based on the comparison result of the signal calibration module to achieve synchronization of multiple channel signals.

[0011] Further, the PE module includes a transmitter and a receiver;

[0012] The transmitter receives the driving signal output by the FPGA and transmits it to: a receiver in the PE module where the transmitter is located and a receiver in the PE module connected to another channel;

[0013] The receiver receives the driving signal transmitted by the transmitter, and sends a feedback signal to the FPGA module through the channel where the receiver is located.

[0014] Furthermore, if there are multiple FPGA modules, a PLL module is also included, and the PLL module is configured to simultaneously provide synchronous clock signals with the same frequency and fixed phase to multiple FPGAs to ensure internal clock synchronization of each FPGA.

[0015] Furthermore, it also includes: at least one relay module, which is located at the output end of the drive signal of each channel of the FPGA module and is configured to control the transmission direction and on-off of the drive signal between different channels.

[0016] Furthermore, the relay module includes a plurality of relay units, each of which is electrically connected to two different channels of the FPGA, and is used to control the transmission direction and on-off of the driving signal between different channels.

[0017] Further, in the relay module, a plurality of relay units are sequentially connected in a closed loop in series;

[0018] Among the multiple channels, two adjacent channels and the first and last two channels are connected by a relay unit;

[0019] To realize the on and off of the transmission of the control drive signal between two different channels.

[0020] Furthermore, it also includes: at least one device under test connection node, connected between the PE module and the relay module through a channel, and used for transmitting a driving signal.

[0021] Furthermore, the device under test connection node is also configured to externally connect the device under test to connect the device under test to each channel.

[0022] On the other hand, the present application provides a method for calibrating a high-speed AC signal of an ATE device, which is applied to the high-speed AC signal calibration system of the ATE device as described above, and the method comprises the following steps:

[0023] S1. Divide a plurality of channels for bidirectional signal transmission into a group of two each, wherein each group of channels includes a channel A and a channel B, and connects the channel A and the channel B in each group of channels;

[0024] S2. Sending a driving signal through channel A at a first time point through FPGA, and recording the time points Ta1 and Tb1 at which the FPGA module receives the feedback signal of the PE module on channel A and channel B respectively through the signal calibration module;

[0025] The FPGA sends a driving signal through the B channel at a second time point, and the signal calibration module records the time points Tb2 and Ta2 at which the FPGA module receives the feedback signals of the PE modules on the B channel and the A channel, respectively;

[0026] S3. Calculate through the signal calibration module: the time delay of the receiver in channel B relative to the receiver in channel A is ΔRX=0.5*((Ta2+Ta1)-(Tb1+Tb2)); the time delay of the transmitter in channel B relative to the transmitter in channel A is ΔTX=0.5*((Ta1+Tb1)-(Ta2+Tb2));

[0027] S4. The delay compensation module makes corresponding adjustments according to the time delays of the receiver and the transmitter in the B channel of the ΔRX and ΔTX groups, so as to synchronize the signals of the B channel and the A channel.

[0028] Further, in “S1. Divide the multiple channels for bidirectional signal transmission into a group of two each, each group of channels includes channel A and channel B, and connects channel A and channel B”, specifically includes: sorting the multiple channels corresponding to each FPGA module in sequence and grouping them in pairs in ascending order according to the serial number, correspondingly connecting the corresponding channel A and channel B in each group; then executing S2, S3, and S4 for each group of channels in sequence;

[0029] Sort the multiple channels corresponding to each FPGA module in sequence and divide the head and tail channels into the first group. The remaining channels are still grouped in pairs according to the serial numbers from small to large. The corresponding A channels and B channels in each group are connected accordingly, and then S2, S3, and S4 are executed in sequence.

[0030] Compared with the prior art, this application has the following advantages and beneficial effects:

[0031] Through the signal calibration module and delay compensation module integrated in the FPGA, the calibration module receives and compares the time delay of the feedback signal of each channel, and the delay compensation module makes adjustments according to the time delay of different channels; the calibration system of this embodiment uses the links and measurement paths required in the actual test process, does not increase the cumulative error, and eliminates the system error; at the same time, avoids the introduction of the TDC chip, thereby eliminating the measurement error of the TDC chip itself, the calibration link and the actual test link are of equal length, avoids the need to re-design the equal length of the link after the introduction of the TDC chip, and reduces the complexity of the system design. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0033] Figure 1 Schematic diagram of the connection structure of each group of channels;

[0034] Figure 2 It is a connection structure of an FPGA module and its corresponding multiple channels and a schematic diagram of the first grouping;

[0035] Figure 3 It is a connection structure of an FPGA module and its corresponding multiple channels and a second grouping diagram;

[0036] Figure 4 A schematic diagram of the connection structure when multiple FPGAs are provided;

[0037] Figure 5 A schematic diagram of a high-speed AC signal calibration method for ATE equipment;

[0038] Figure 6 A simplified schematic diagram of a high-speed AC signal calibration system for ATE equipment. DETAILED DESCRIPTION

[0039] In the following, various embodiments of the present disclosure will be described more fully. The present disclosure may have various embodiments, and adjustments and changes may be made therein. However, it should be understood that there is no intention to limit the various embodiments of the present disclosure to the specific embodiments disclosed herein, but rather the present disclosure should be understood to cover all adjustments, equivalents and / or alternatives that fall within the spirit and scope of the various embodiments of the present disclosure.

[0040] Hereinafter, the terms "include" or "may include" used in various embodiments of the present disclosure indicate the presence of disclosed functions, operations, or elements, and do not limit the addition of one or more functions, operations, or elements. In addition, as used in various embodiments of the present disclosure, the terms "include", "have", and their cognates are intended only to indicate specific features, numbers, steps, operations, elements, components, or a combination of the foregoing, and should not be understood as first excluding the presence of one or more other features, numbers, steps, operations, elements, components, or a combination of the foregoing or the possibility of adding one or more features, numbers, steps, operations, elements, components, or a combination of the foregoing.

[0041] In various embodiments of the present disclosure, the expression "or" or "at least one of A or / and B" includes any combination or all combinations of the words listed at the same time. For example, the expression "A or B" or "at least one of A or / and B" may include A, may include B, or may include both A and B.

[0042] The expressions (such as "first", "second", etc.) used in the various embodiments of the present disclosure may modify the various constituent elements in the various embodiments, but may not limit the corresponding constituent elements. For example, the above expressions do not limit the order and / or importance of the elements. The above expressions are only used for the purpose of distinguishing one element from other elements. For example, the first user device and the second user device indicate different user devices, although both are user devices. For example, without departing from the scope of the various embodiments of the present disclosure, the first element may be referred to as the second element, and similarly, the second element may also be referred to as the first element.

[0043] It should be noted that if it is described that one component element is “connected” to another component element, the first component element may be directly connected to the second component element, and a third component element may be “connected” between the first component element and the second component element. Conversely, when one component element is “directly connected” to another component element, it can be understood that there is no third component element between the first component element and the second component element.

[0044] The term “user” used in various embodiments of the present disclosure may indicate a person using an electronic device or a device (eg, an artificial intelligence electronic device) using the electronic device.

[0045] The terms used in the various embodiments of the present disclosure are only used for the purpose of describing specific embodiments and are not intended to limit the various embodiments of the present disclosure. As used herein, the singular form is intended to also include the plural form, unless the context clearly indicates otherwise. Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as the meanings commonly understood by ordinary technicians in the field to which the various embodiments of the present disclosure belong. The terms (such as the terms defined in the generally used dictionary) will be interpreted as having the same meaning as the contextual meaning in the relevant technical field and will not be interpreted as having an idealized meaning or an overly formal meaning, unless clearly defined in the various embodiments of the present disclosure.

[0046] Note: In this disclosure, FPGA stands for Field-Programmable Gate Array; TDC stands for Time-to-Digital Converters; PLL stands for Phase Locked Loop; the transmitter symbol is TX, and the receiver symbol is RX; PE is a pin driver, and a PE contains one or more PE modules, and a TX and a RX together constitute a processor module; the drive signal is the Drive signal, the feedback signal is the Compare signal, and the synchronous clock signal is the SYNC_CLK signal; the connection node of the device under test is DUT_CN, where DUT stands for Device Under Test and CN stands for Connection Node.

[0047] Embodiment 1:

[0048] This embodiment provides a high-speed AC signal calibration system for ATE equipment, such as Figures 1 to 4 and Figure 6 As shown, the system includes:

[0049] like Figure 2 and Figure 3 As shown, at least one FPGA module has multiple channels for bidirectional transmission of signals;

[0050] Multiple PE modules, each PE module is located on a channel of the FPGA, and is used to receive a driving signal output by the FPGA, and send a feedback signal to the FPGA module according to the driving signal;

[0051] A signal calibration module, located inside the FPGA, is used to receive feedback signals and compare the time delays between feedback signals fed back from different channels;

[0052] The delay compensation module, located inside the FPGA, is configured to adjust the time delay of each channel based on the comparison result of the signal calibration module to achieve synchronization of multiple channel signals.

[0053] Beneficial effects: Through the signal calibration module and delay compensation module integrated in the FPGA, the calibration module receives and compares the time delay of the feedback signal of each channel, and the delay compensation module makes adjustments according to the time delay of different channels; the calibration system of this embodiment uses the links and measurement paths required in the actual test process, does not increase the cumulative error, and eliminates the system error; at the same time, avoids the introduction of the TDC chip, thereby eliminating the measurement error of the TDC chip itself, the calibration link and the actual test link are of equal length, avoids the need to re-design the equal length of the link after the introduction of the TDC chip, and reduces the complexity of the system design.

[0054] Further, such as Figure 1 As shown, each PE module includes a transmitter and a receiver;

[0055] The transmitter receives the driving signal output by the FPGA and transmits it to: a receiver in the PE module where the transmitter is located and a receiver in the PE module connected to another channel;

[0056] The receiver receives the driving signal transmitted by the transmitter, and sends a feedback signal to the FPGA module through the channel where the receiver is located.

[0057] Beneficial effects: This structure receives the driving signal transmitted from the FPGA through the transmitter and sends a feedback signal to the receiver of the same channel or another channel; receives the driving signal sent by the transmitter in the PE module on the same channel and another channel through the receiver, and sends a feedback signal through the channel where the receiver is located; realizes bidirectional transmission and cross-channel transmission of signals, which is convenient for accurately detecting and recording the time delay of each channel to improve the accuracy of signal calibration.

[0058] Further, such as Figure 4 As shown, if there are multiple FPGA modules, a PLL module is also included. The PLL module is configured to simultaneously provide synchronous clock signals with the same frequency and fixed phase to multiple FPGAs to ensure internal clock synchronization of each FPGA.

[0059] Beneficial effects: The PLL module provides multiple synchronous clock signals with the same frequency and fixed phase, which realizes clock synchronization across FPGAs, keeps the internal clocks of multiple FPGAs in the system synchronized, and ensures the accuracy and stability of large-scale multi-channel signal calibration in complex ATE systems.

[0060] Furthermore, it also includes: at least one relay module, which is located at the output end of the drive signal of each channel of the FPGA module and is configured to control the transmission direction and on-off of the drive signal between different channels.

[0061] Beneficial effects: By setting a relay module at the output end of the drive signal of each channel, the connectivity between different channels is controlled, and flexible switching and flow control of the drive signal are achieved, thereby improving system flexibility and simplifying the management of the drive signal transmission path.

[0062] Further, such as Figures 2 to 4 As shown, the relay module includes a plurality of relay units, such as Figures 1 to 4 As shown, each relay unit is electrically connected to two different channels of the FPGA, respectively, to control the transmission direction and on-off of the driving signal between different channels.

[0063] Beneficial effects: Each relay unit in the relay module is connected to two different channels respectively, which is used to control the transmission direction and on-off state of the driving signal, thereby improving the flexibility and operability of multi-channel signal calibration;

[0064] Further, such as Figures 2 to 4 As shown, in the relay module, multiple relay units are connected in series in a closed loop;

[0065] Among the multiple channels, ends of two adjacent channels and ends of two channels at the head and tail are connected through a relay unit;

[0066] To realize the on and off of the transmission of the control drive signal between two different channels.

[0067] Beneficial effect: A plurality of series closed-loop relay units are connected in series to form a relay module, so that adjacent channels and the head and tail channels can be connected through the relay units, realizing flexible control of closed-loop signal transmission. The series closed-loop structure simplifies the system architecture and effectively improves the efficiency of signal calibration.

[0068] Furthermore, it also includes: at least one device under test connection node, connected between the PE module and the relay module through the channel, for transmitting the driving signal. The device under test connection node is also configured to be able to externally connect the device under test to connect the device under test to each channel.

[0069] Embodiment 2:

[0070] This application also provides a method for calibrating a high-speed AC signal of an ATE device, such as Figure 5 As shown, the method is applied to the ATE equipment high-speed AC signal calibration system in the above embodiment 1, and includes the following steps:

[0071] S1. Divide a plurality of channels for bidirectional signal transmission into a group of two each, wherein each group of channels includes a channel A and a channel B, and connects the channel A and the channel B in each group of channels;

[0072] S2. Sending a driving signal through channel A at a first time point through FPGA, and recording the time points Ta1 and Tb1 at which the FPGA module receives the feedback signal of the PE module on channel A and channel B respectively through the signal calibration module;

[0073] The FPGA sends a driving signal through the B channel at a second time point, and the signal calibration module records the time points Tb2 and Ta2 at which the FPGA module receives the feedback signals of the PE modules on the B channel and the A channel, respectively;

[0074] S3. Calculate through the signal calibration module: the time delay of the receiver in channel B relative to the receiver in channel A is ΔRX=0.5*((Ta2+Ta1)-(Tb1+Tb2)); the time delay of the transmitter in channel B relative to the transmitter in channel A is ΔTX=0.5*((Ta1+Tb1)-(Ta2+Tb2));

[0075] S4. The delay compensation module makes corresponding adjustments according to the time delays of the receiver and the transmitter in the B channel of the ΔRX and ΔTX groups, so as to synchronize the signals of the B channel and the A channel.

[0076] Beneficial effects: By selecting channel A and channel B, driving signals are sent at different times respectively, the time points of feedback signals are recorded, and the time delay between channels is calculated according to the time delay formula. Finally, the time delay of the channels is adjusted by the demonstration compensation module. This method realizes signal synchronization of multiple channels in a column through precise delay calculation and compensation, avoiding the introduction of TDC chips to increase redundant measurement errors and system errors caused by unequal lengths of calibration links and test links.

[0077] Further, in “S1. Divide the multiple channels for bidirectional signal transmission into a group of two each, each group of channels includes channel A and channel B, and connects channel A and channel B”, specifically includes: sorting the multiple channels corresponding to each FPGA module in sequence and grouping them in pairs in ascending order according to the serial number, correspondingly connecting the corresponding channel A and channel B in each group; then executing S2, S3, and S4 for each group of channels in sequence;

[0078] Sort the multiple channels corresponding to each FPGA module in sequence and divide the head and tail channels into the first group. The remaining channels are still grouped in pairs according to the serial numbers from small to large. The corresponding A channels and B channels in each group are connected accordingly, and then S2, S3, and S4 are executed in sequence.

[0079] Specifically, Figure 2The first grouping method is shown in Figure 1. The multiple channels corresponding to each FPGA are sorted from 1 to n, and then grouped again - channels with serial numbers 1 and 2 are grouped together, channels with serial numbers 3 and 4 are grouped together, and so on, channels with serial numbers n-1 and n are grouped together. Figure 1 The maximum sequence number n is 32, so it can be divided into 16 groups at most. Then, the A channel and the B channel in each group of channels are connected through the relay module, and S2, S3, and S4 are executed for each group of channels.

[0080] like Figure 3 The figure shows the second grouping method. The multiple channels corresponding to each FPGA are sorted from 1 to n in sequence, and then grouped again - the channel with the largest sequence number n and the smallest sequence number 1 is grouped together, the channels with sequence numbers 2 and 3 are grouped together, ..., the channels with sequence numbers n-2 and n-1 are grouped together, Figure 1 The maximum sequence number n is 32, so it can be divided into 16 groups at most. Then, the A channel and the B channel in each group of channels are connected in sequence through the relay module, and S2, S3, and S4 are executed in each group of channels.

[0081] in, Figure 1 A simplified schematic diagram of each group of channels is shown. In step S2, the FPGA first transmits a signal to the transmitter on the channel through channel A at a first time point. Figure 1 The TX end of channel A sends a driving signal, and the TX end of channel A sends a driving signal to the receiver on channel A, that is, the RX end of channel A, and to the receiver on channel B, that is, the RX end of channel B. After the RX ends on channel A and channel B are triggered at the same time, they send feedback signals to the signal calibration module of FPGA through their own channels, and the signal calibration module records the time points Ta1 and Tb1 when the FPGA module receives the feedback signals sent by the receiving end RX of the PE module on channel A and channel B respectively;

[0082] Then, at the second time point, the FPGA sends a driving signal through channel B to the transmitter on the channel. Figure 1 The TX end of the B channel sends a driving signal, and the TX end of the B channel simultaneously sends a driving signal to the receiver on the B channel, that is, the RX end of the B channel, and to the receiver on the A channel, that is, the RX end of the A channel. After the RX ends on the B channel and the A channel are triggered at the same time, they respectively send feedback signals to the signal calibration module of the FPGA through their own channels. The signal calibration module records the time points Tb2 and Ta2 when the FPGA module receives the feedback signals sent by the RX ends of the PE modules on the B channel and the A channel respectively;

[0083] By grouping twice, the time delay of multiple channels corresponding to one FPGA module can be kept consistent, and the signal synchronization of each channel can be achieved. Figure 4As shown, a synchronous clock signal with the same frequency and fixed phase is first sent to each FPGA simultaneously through the PLL module, so that the internal clock in each FPGA module remains synchronized; then each FPGA module calibrates and compensates the multiple channels corresponding to itself through steps S1, S2, S3, and S4, so that each channel between multiple FPGA modules can achieve signal synchronization.

[0084] Through the above embodiment, the actual link and measurement path used when testing the device to be tested are adopted, the cumulative error is not increased, the system error is eliminated, and the calibration process does not introduce the TDC chip, only the fixed relay is used, so the measurement error of the TDC chip itself is not introduced, and there is no need to redesign the product link to be equal in length, which greatly reduces the complexity of the system. The calibration scheme in this embodiment can achieve the signal alignment accuracy of each channel to the accuracy of a carry chain inside the FPGA module, which is about 40 picoseconds; compared with the scheme using the TDC chip calibration accuracy of more than 100 picoseconds, it has achieved great accuracy.

[0085] Those skilled in the art will appreciate that the accompanying drawings are merely schematic diagrams of a preferred implementation scenario, and the modules or processes in the accompanying drawings are not necessarily required for implementing the present invention.

[0086] Those skilled in the art will appreciate that the modules in the device in the implementation scenario can be distributed in the device in the implementation scenario according to the implementation scenario description, or can be changed accordingly and located in one or more devices different from the implementation scenario. The modules in the above implementation scenario can be combined into one module, or can be further split into multiple sub-modules.

[0087] The above serial numbers of the present invention are only for description and do not represent the advantages or disadvantages of the implementation scenarios.

[0088] The above disclosure is only a few specific implementation scenarios of the present invention, but the present invention is not limited thereto, and any changes that can be conceived by those skilled in the art should fall within the protection scope of the present invention.

Claims

1. A high-speed AC signal calibration system for ATE equipment, characterized in that: The system comprises: at least one FPGA module having a plurality of channels for bidirectionally transmitting signals; A plurality of PE modules, each of which is located on one of the channels of the FPGA and is used to receive a driving signal output by the FPGA and send a feedback signal to the FPGA module according to the driving signal; A signal calibration module, located inside the FPGA, for receiving the feedback signal and comparing the time delay between the feedback signals fed back from different channels; The delay compensation module is located inside the FPGA and is configured to adjust the time delay of each of the channels based on the comparison result of the signal calibration module to achieve synchronization of multiple channel signals.

2. The ATE equipment high-speed AC signal calibration system according to claim 1, characterized in that: The PE module includes a transmitter and a receiver; The transmitter receives the driving signal output by the FPGA, and transmits the driving signal to: the receiver in the PE module where the transmitter is located, and the receiver in the PE module connected to another channel; The receiver receives the driving signal transmitted by the transmitter, and sends a feedback signal to the FPGA module through the channel where the receiver is located.

3. The ATE equipment high-speed AC signal calibration system according to claim 2, characterized in that: If there are multiple FPGA modules, a PLL module is also included. The PLL module is configured to simultaneously provide synchronous clock signals with the same frequency and fixed phase to the multiple FPGAs to ensure internal clock synchronization of each FPGA.

4. The ATE equipment high-speed AC signal calibration system according to any one of claims 2 or 3, characterized in that: Also includes: At least one relay module, the relay module is located at the output end of the drive signal of each channel of the FPGA module, and is configured to control the transmission direction and on-off of the drive signal between different channels.

5. The ATE equipment high-speed AC signal calibration system according to claim 4, characterized in that: The relay module includes a plurality of relay units, each of which is electrically connected to two different channels of the FPGA, and is used to control the transmission direction and on-off of the drive signal between different channels.

6. The ATE equipment high-speed AC signal calibration system according to claim 5, characterized in that: In the relay module, a plurality of the relay units are connected in series in a closed loop; Among the plurality of channels, two adjacent channels and the first and last two channels are connected by one relay unit; This is to realize the control of the transmission on and off of the driving signal between the two different channels.

7. The ATE equipment high-speed AC signal calibration system according to claim 2, characterized in that: Also includes: At least one device under test connection node is connected between the PE module and the relay module through the channel and is used to transmit the driving signal.

8. The ATE equipment high-speed AC signal calibration system according to claim 7, characterized in that: The device under test connection node is further configured to externally connect the device under test to connect the device under test to each of the channels.

9. A method for calibrating high-speed AC signals of ATE equipment, characterized in that: Applied to the ATE equipment high-speed AC signal calibration system according to any one of claims 2 to 8, the method comprises the following steps: S1. Divide a plurality of channels for bidirectional signal transmission into a group of two each, wherein each group of channels includes a channel A and a channel B, and connects the channel A and the channel B in each group of channels; S2. The FPGA sends a driving signal through the A channel at a first time point, and the signal calibration module records the time points Ta1 and Tb1 at which the FPGA module receives the feedback signals of the PE modules on the A channel and the B channel, respectively; Sending a driving signal through the B channel at a second time point by the FPGA, and correspondingly recording time points Tb2 and Ta2 at which the FPGA module receives feedback signals from the PE modules on the B channel and the A channel respectively by the signal calibration module; S3. Calculate respectively through the signal calibration module: the time delay of the receiver in the B channel relative to the receiver in the A channel is ΔRX=0.5*((Ta2+Ta1)-(Tb1+Tb2)); the time delay of the transmitter in the B channel relative to the transmitter in the A channel is ΔTX=0.5*((Ta1+Tb1)-(Ta2+Tb2)); S4. The delay compensation module makes corresponding adjustments to the time delays of the receiver and the transmitter in the B channel according to the ΔRX and ΔTX groups, so as to synchronize the signals of the B channel and the A channel.

10. The ATE equipment high-speed AC signal calibration method according to claim 9, characterized in that: In "S1. Divide the plurality of channels for bidirectional signal transmission into a group of two each, wherein each group of channels includes a channel A and a channel B, and the channels A and B are connected", the method specifically includes: sequentially sorting the plurality of channels corresponding to each FPGA module and sequentially grouping them in pairs from small to large numbers, and correspondingly connecting the corresponding channels A and B in each group; and then sequentially executing S2, S3, and S4 for each group of channels; Sort the multiple channels corresponding to each FPGA module in sequence and divide the head and tail channels into the first group. The remaining channels are still grouped in pairs according to the serial numbers from small to large. The corresponding A channels and B channels in each group are connected accordingly, and then S2, S3, and S4 are executed in sequence.

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