Decoding circuit, data processing method, chip and equipment

Abstract

The invention discloses a decoding circuit, a data processing method, a chip and equipment, and belongs to the technical field of electronics. The decoding circuit comprises a first statistical unit which is used for counting the total amount of first data according to the data volume used by the decoding unit for at least one time of decoding, wherein the data volume used by the decoding unit for each time of decoding is not fixed; the cache unit is used for removing decoded first data from the stored data under the condition that the total amount of the first data meets a removal condition, and the length of the first data is a first bit width; and obtaining to-be-decoded second data with the length being the first bit width, and storing the second data. When the total amount of the first data meets the removal condition, the stored first data is removed, the data removal frequency is low, and the circuit power consumption is low. Even if the amount of data used for decoding is not fixed, the length of the first data removed by the cache unit is the fixed first bit width, and the design complexity of the cache unit for removing the first data with the fixed bit width is low.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of electronic technology, and in particular to a decoding circuit, a data processing method, a chip and a device. Background Art

[0002] In the field of electronic technology, entropy coding refers to a lossless coding method based on the entropy principle during the coding process. In the process of entropy coding of data, long code stream coding is used for data with low frequency of occurrence, and short code stream coding is used for data with high frequency of occurrence. Since the entropy coding process uses code streams of different lengths for encoding based on the frequency of occurrence of data, the data amounts of multiple encoding results obtained by entropy coding are inconsistent, and the amount of data used by the decoding circuit during the decoding process is also inconsistent. Summary of the invention

[0003] The embodiments of the present application provide a decoding circuit, a data processing method, a chip and a device, which can be used to cache data to be decoded when there is a difference in the amount of data used for decoding. The technical solution is as follows:

[0004] On the one hand, an embodiment of the present application provides a decoding circuit, the decoding circuit comprising a first statistical unit, a cache unit and a decoding unit, the first statistical unit is connected to the decoding unit, the cache unit is connected to the decoding unit;

[0005] The decoding unit is used to read the data stored in the cache unit and decode the read data, and the amount of data decoded by the decoding unit each time is not fixed;

[0006] The first statistical unit is used to count the total amount of first data according to the amount of data used for at least one decoding by the decoding unit;

[0007] The cache unit is used to remove the decoded first data from the stored data when the total amount of the first data meets the removal condition, and the length of the first data is the first bit width;

[0008] The cache unit is further used to obtain second data to be decoded with a length of the first bit width from an external storage module, and store the second data.

[0009] In a possible implementation, the first statistical unit is further configured to send identification information to the cache unit when the first total amount of data meets a removal condition;

[0010] The cache unit is used to determine whether the first total amount of data meets a removal condition based on the identification information.

[0011] In a possible implementation, the first statistics unit is configured to receive first indication data sent by the decoding unit, where the first indication data indicates a first data amount used by the decoding unit in decoding ended at a current moment;

[0012] The first total amount of data is determined based on the first amount of data and a second amount of data, where the second amount of data is determined based on an amount of data used in decoding ended by the decoding unit at a historical moment.

[0013] In a possible implementation, the first statistical unit includes an arithmetic unit and a trigger unit;

[0014] the arithmetic unit is configured to receive the second indication data indicating the second data amount sent by the trigger unit and the first indication data sent by the decoding unit, calculate the first data total amount according to the first data amount and the second data amount, and send data indicating the first data total amount to the trigger unit;

[0015] The trigger unit is used to store the data indicating the total amount of the first data sent by the arithmetic unit;

[0016] The arithmetic unit is further used to update the total amount of first data stored in the trigger unit when the decoding unit completes the next decoding.

[0017] In a possible implementation, the first total amount of data includes a first total amount, the first total amount indicates a data amount of decoded data stored in the cache unit, and the removal condition includes that the first total amount is greater than the first bit width;

[0018] Alternatively, the first total amount of data includes a second total amount, the second total amount indicates the amount of undecoded data stored in the cache unit, and the removal condition includes that the second total amount is less than a second bit width, and the second bit width is the difference between the total memory capacity of the cache unit and the first bit width.

[0019] In a possible implementation, the decoding circuit further includes a control unit;

[0020] The control unit is used to control the cache unit to receive the second data to be decoded when the total amount of the first data meets the removal condition.

[0021] In a possible implementation, the decoding circuit further includes a second statistical unit, the second statistical unit being configured to count a second total amount of data according to an amount of data used for at least one decoding by the decoding unit, the second total amount of data indicating an amount of decoded data stored in the cache unit;

[0022] The cache unit is further configured to determine third data to be decoded from the stored data according to the total amount of the second data, and send the third data to the decoding unit.

[0023] In a possible implementation, when the first total amount of data satisfies a removal condition, a value of a least significant bit of the third data is equal to a difference between the second total amount of data and the first bit width.

[0024] In a possible implementation, when the first total amount of data does not satisfy a removal condition, the value of the least significant bit of the third data is equal to the second total amount of data.

[0025] On the other hand, a data processing method is provided, the method comprising:

[0026] Acquire data to be decoded, and decode the data to be decoded, wherein the amount of data decoded each time is not fixed;

[0027] Counting the first total amount of data according to the amount of data used for at least one decoding;

[0028] When the total amount of the first data satisfies a removal condition, removing the decoded first data from the stored data with decoding requirements, the length of the first data being the first bit width;

[0029] Acquire second data to be decoded having a length equal to the first bit width from an external storage module, and store the second data.

[0030] In a possible implementation manner, the counting of the first total amount of data according to the amount of data used for at least one decoding includes:

[0031] Obtaining a first data amount used in decoding that ends at a current moment;

[0032] The first total amount of data is determined based on the first amount of data and a second amount of data, where the second amount of data is determined based on an amount of data used in decoding that ends at a historical moment.

[0033] In a possible implementation, the first total amount of data includes a first total amount, the first total amount indicates a data amount of the stored decoded data, and the removal condition includes that the first total amount is greater than the first bit width;

[0034] Alternatively, the first total amount of data includes a second total amount, the second total amount indicates the amount of stored undecoded data, and the removal condition includes that the second total amount is less than a second bit width, and the second bit width is the difference between the total amount of stored data and the first bit width.

[0035] In a possible implementation, the method further includes:

[0036] Counting a second total amount of data according to the amount of data used for the at least one decoding, where the second total amount of data indicates the amount of stored decoded data;

[0037] The third data to be decoded is determined from the stored data according to the second total amount of data.

[0038] In a possible implementation, when the first total amount of data satisfies the removal condition, the value of the least significant bit of the third data is equal to the difference between the second total amount of data and the first bit width.

[0039] In a possible implementation, when the first total amount of data does not satisfy the removal condition, the value of the least significant bit of the third data is equal to the second total amount of data.

[0040] On the other hand, an electronic device is provided, which includes a decoding circuit and a storage module, wherein the decoding circuit is used to execute the data processing method in any possible implementation manner described above, and read the second data from the storage module.

[0041] In a possible implementation, the storage module includes SRAM (Static Random Access Memory).

[0042] On the other hand, a chip is provided, the chip comprising a decoding circuit, and the decoding circuit is used to execute the data processing method in any possible implementation manner described above.

[0043] The technical solution provided by this application brings at least the following beneficial effects:

[0044] The first statistical unit counts the amount of data used for decoding by the decoding unit, and only removes the stored first data when the total amount of the first data meets the removal condition. The frequency of data removal is low, which reduces the working time of the decoding circuit and has low power consumption. Moreover, even if the amount of data used by the decoding unit for each decoding is not fixed, and the decoding circuit is applied to the scenario of variable-length decoding, each removal by the cache unit is a fixed-length removal, and the length of the first data removed is a fixed first bit width. The cache unit only needs to support the removal operation of one amount of data, and the design complexity is low. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0046] Figure 1 is a structural schematic diagram of a decoding circuit provided in an embodiment of the present application;

[0047] Figure 2 is a schematic diagram of the structure of another decoding circuit provided in an embodiment of the present application;

[0048] Figure 3 It is a structural diagram of a cache module provided in an embodiment of the present application;

[0049] Figure 4 is a structural diagram of a first statistical unit provided in an embodiment of the present application;

[0050] Figure 5 It is a structural diagram of another cache module provided in an embodiment of the present application;

[0051] Figure 6 It is a schematic diagram of a data storage provided by an embodiment of the present application;

[0052] Figure 7 This is a schematic diagram of a data removal process provided by an embodiment of the present application;

[0053] Figure 8 is a schematic diagram of the structure of another cache module provided in an embodiment of the present application;

[0054] Fig. 9 is a structural diagram of another cache module provided in an embodiment of the present application;

[0055] Fig.10 This is another schematic diagram of a data removal process provided by an embodiment of the present application;

[0056] Fig.11 It is a structural diagram of another cache module provided in an embodiment of the present application;

[0057] Fig.12 It is a flow chart of a data processing method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0058] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0059] With the development of electronic technology, more and more application scenarios involve the use of entropy coding. For example, in 2018, VESA (Video Electronics Standards Association) released a more advanced version of the image compression algorithm VDC-M (VESAdisplay compression-M) than DSC (display stream compression). VDC-M can achieve real-time compression and decoding of image data, and can achieve a lossy compression ratio of 5:1. In the VDC-M algorithm, the data encoding part uses entropy coding technology. The data to be encoded is grouped through the data module, and variable-length entropy coding is performed on each group to obtain encoding results of different lengths.

[0060] The data module can be grouped in 8*2 mode or in other module grouping modes, which is not limited in the present embodiment. Regardless of the entropy coding mode, the decoding side has a corresponding entropy decoding algorithm for decoding data of different lengths.

[0061] In the related art, multiple data obtained by entropy coding are cached in a buffer (buff) area. Based on the situation that the data obtained by entropy coding is variable-length data, the decoding module on the decoding side reads the variable-length data from the buff area for decoding each time. Since the data read by the decoding module each time is variable-length data, after each decoding, the buff area will remove the decoded data and continue to decode the remaining data. If the amount of data remaining in the buff area is less than the amount of data read by the decoding module, other data to be decoded will be read and cached in the buff area.

[0062] In the above method, after each decoding is completed, the buff area needs to remove the cached data once, and the removal times are large, which consumes a lot of power. In addition, the removed data are decoded data of different lengths, and the buff area needs to perform data removal of different lengths, which has high operation complexity.

[0063] Based on this, an embodiment of the present application provides a decoding circuit for caching data to be decoded during a decoding process. Figure 1 A decoding circuit provided in an embodiment of the present application, see Figure 1The decoding circuit includes a first statistical unit 11, a cache unit 12 and a decoding unit 13, wherein the first statistical unit 11 is connected to the cache unit 12 and the decoding unit 13 respectively, and the cache unit 12 is also connected to the decoding unit 13. The decoding unit 13 is used to decode data, and the first statistical unit 11 and the cache unit 12 are used to cache data according to the amount of data used for decoding by the decoding unit 13. In some cases, the decoding unit 13 can be understood as a unit in the decoding module, and the first statistical unit 11 and the cache unit 12 can be as follows Figure 1 Shown as a unit in a cache module.

[0064] In one possible case, the decoding circuit performs decoding based on a look-up table during the decoding process, and the decoding circuit includes a decoding unit 13 for storing the look-up table. Since the size of the look-up table will also be large when the maximum code length of the encoding result is very long, the decoding circuit can use a decoding unit 13 to store a look-up table, and repeatedly use a look-up table in multiple decoding tasks to obtain decoding results of multiple data in sequence.

[0065] Optionally, since there is a requirement for the decoding rate in the decoding process using the decoding circuit, a decoding unit 13 included in the decoding circuit can be added, and multiple decoding units 13 can be used for parallel decoding to improve the decoding rate. The multiple decoding units included in the decoding circuit are as follows: Figure 2 shown.

[0066] Whether Figure 1 A decoding unit 13 is shown, or Figure 2 Among the multiple decoding units shown, the decoding unit 13 is connected to the cache unit 12. Therefore, the decoding unit 13 can read data from the cache unit 12 based on the connection relationship with the cache unit 12 and decode the read data. Optionally, the length of the data read by the decoding unit 13 from the cache unit 12 is a second bit width, and the second bit width is determined based on the maximum code length of the encoding result, wherein the maximum code length refers to the maximum code length of each encoding result obtained by entropy coding, and the process of determining the second bit width according to the maximum code length is, for example, determining the maximum code length in each encoding result as the second bit width, or setting a second bit width larger than the maximum code length.

[0067] If the data read by the decoding unit 13 does not include a complete encoding result, for example, the length of the encoding result is A bits, and the length of the data read by the decoding unit 13 is B bits, A is less than B, and the data obtained by the decoding unit 13 is a partial encoding result, which is the data of the first B bits of the encoding result. Based on the incomplete encoding result, the decoding unit 13 cannot successfully decode. In addition, since the code lengths of the multiple encoding results obtained after the data is encoded by entropy coding are different, the decoding unit 13 can determine the maximum code length among the code lengths of the multiple encoding results as the second bit width. In this case, regardless of whether the code length of the encoding result decoded by the decoding unit 13 is equal to the maximum code length or less than the maximum code length, the amount of data read by the decoding unit 13 from the cache unit 12 is not less than the amount of data of the encoding result, that is, the data read by the decoding unit 13 from the cache unit 12 includes a complete encoding result, and the decoding unit 13 can successfully decode based on the complete encoding result.

[0068] In addition, the decoding unit 13 reads data from the cache unit 12, which means copying data from the cache unit 12, and the read data will still be stored in the cache unit 12. The process of reading data is, for example, that the cache unit 12 determines the data to be decoded from the stored data, copies the determined data, obtains the copy result, and sends the copy result to the decoding unit 13, so that the decoding unit 13 decodes according to the copy result. By copying the data, even if the decoding unit 13 does not completely use the read data, since the undecoded data is still stored in the memory space of the cache unit 12, the decoding unit 13 can also read the undecoded data from the cache unit 12 for the next decoding. Therefore, the decoding unit 13 does not need to write the undecoded data into the cache unit 12 again, which avoids the cache unit 12 from frequently executing write and write, and reduces the power consumption of the cache unit 12.

[0069] Next, taking the second bit width as the longest code length as an example, the reason why the decoding unit 13 does not fully use the read data is explained. Since the length of the encoding result is not uniform, the decoding unit 13 reads the code length of the processed encoding result as the maximum code length each time, but it may happen that the code length of the processed encoding result is not the maximum code length, for example, the code length of the currently decoded encoding result is C bits, and C bits are less than the maximum code length. Since the decoding unit 13 decodes one encoding result at a time, the decoding unit 13 does not decode the data belonging to other encoding results after the C bit, and the decoding unit 13 does not use the data after the C bit.

[0070] Since the amount of data used for decoding by the decoding unit 13 may be the second bit width or any value less than the second bit width, the decoding circuit will count the amount of data used for decoding after each decoding is completed. The amount of data used for decoding is also the code length of the decoded encoding result, so that when decoding data next time, the data to be read can be determined from the data stored in the cache unit 12 according to the counted amount of data used for decoding.

[0071] In a possible case, the decoding circuit may count the amount of data used for decoding by the decoding unit 13 through the first statistical unit 11. For example, the first statistical unit 11 counts the total amount of first data according to the amount of data used for decoding by the decoding unit 13 at least once.

[0072] Among them, the at least one decoding counted by the first statistics unit 11 refers to the decoding performed before the current moment, and the data amount decoded by the decoding unit 13 each time is not fixed, which means that the data amount decoded by the decoding unit 13 is not a fixed value, and the data amount used for each decoding may be completely different. For example, the decoding unit 13 performs three decodings before the current moment, and the data amounts used for the three decodings are data amount a, data amount b, and data amount c, respectively, and the data amount a, data amount b, and data amount c are different. Optionally, the data amount decoded by the decoding unit 13 each time is not fixed, and the data amounts used for the multiple decodings may be partially different. Continuing with the example that the data amounts used for the three decodings are data amount a, data amount b, and data amount c, respectively, the data amount a and the data amount b are the same, but the data amount c is different from the data amounts used for the other two decodings (data amount a and data amount b).

[0073] Regardless of the amount of data used in each decoding by the decoding unit 13, the first statistical unit 11 can count the first total amount of data based on the amount of data used in at least one decoding performed at the current moment and before. In the case where the decoding circuit uses the decoding unit 13 to perform decoding, the amount of data used in at least one decoding counted by the first statistical unit 11 can be understood as the amount of data used in at least one decoding process performed by the decoding circuit using one decoding unit 13. That is, if the decoding circuit includes multiple decoding units, one first statistical unit 11 corresponds to one decoding unit 13. Since the statistical processes corresponding to different decoding units 13 are similar, the statistical process of the first statistical unit 11 is temporarily described by taking the decoding circuit using one decoding unit 13 as an example.

[0074] In a possible case, after each decoding is completed, the decoding unit 13 sends first indication data to the first statistical unit 11, where the first indication data indicates the first data amount used by the decoding unit 13 in the decoding ended at the current moment.

[0075] Exemplarily, the first statistical unit 11 receives the first indication data sent by the decoding unit 13; determines the first total data amount according to the first data amount and the second data amount, and the second data amount is determined based on the data amount used in the decoding ended by the decoding unit 13 at a historical moment.

[0076] Figure 3 A schematic diagram of the structure of a first statistical unit 11 provided in an embodiment of the present application is shown in FIG. Figure 3 The first statistical unit 11 includes an arithmetic unit 111 and a trigger unit 112, wherein the input end of the arithmetic unit 111 is connected to the output end of the decoding unit 13, the output end of the arithmetic unit 111 is connected to the input end of the trigger unit 112, and the output end of the trigger unit 112 is connected as the output end of the first statistical unit 11 and the input end of the cache unit 12. Figure 3 In the diagram, a white circle is used to mark the input terminal, and a black circle is used to mark the output terminal.

[0077] Figure 3 The trigger unit 112 is used to store the second indication data indicating the second data amount output by the arithmetic unit 111 at a historical moment; and send the second indication data to the arithmetic unit 111 at the current moment; the arithmetic unit 111 is used to receive the second indication data sent by the trigger unit 112 and the first indication data sent by the decoding unit 13, calculate the total amount of the first data according to the first data amount and the second data amount, and send data indicating the total amount of the first data to the trigger unit 112; the trigger unit 112 is also used to store the data indicating the total amount of the first data sent by the arithmetic unit 111, and the total amount of the first data is updated by the arithmetic unit 111 when the decoding unit 13 finishes decoding next time.

[0078] In one possible case, the first total amount of data may be any decoding situation that can represent the data in the cache unit 12. The first total amount of data may be the total amount of data obtained by accumulation or the total amount of data obtained by subtraction. Next, examples are given to illustrate the process of interaction between the arithmetic unit 111 and the trigger unit 112 to determine different first total amounts of data.

[0079] Case 1: the first data total amount includes a first total amount, and the first total amount indicates a data amount of the decoded data stored in the cache unit 12 .

[0080] The first total amount in case one belongs to the total amount of data obtained by accumulation, with the current moment as moment 1 and the historical moment as moment 2, which illustrates the process of determining the second data amount based on the amount of data decoded by the decoding unit 13, and determining the first total amount based on the second data amount.

[0081] After the decoding unit 13 completes the decoding at time 2, it sends data 2 indicating the data amount 2 used for the current decoding to the arithmetic unit 111. Since the decoding unit 13 has not decoded data before time 2, the value of the arithmetic unit 111 before time 2 is 0. The arithmetic unit 111 adds 0 and the data amount 2, and uses the sum obtained by the addition as the second data amount, which is equal to the data amount 2. After determining the second data amount, the arithmetic unit 111 may send second indication data indicating the second data amount to the trigger unit 112, and the trigger unit 112 stores the second indication data.

[0082] Afterwards, the decoding unit 13 ends decoding at time 1, that is, the current time, and sends data 1 indicating the amount of data 1 used for this decoding to the arithmetic unit 111. The amount of data 1 is also the first amount of data, and data 1 is also the first indication data indicating the first amount of data. When the decoding unit 13 ends decoding and sends data 1 to the arithmetic unit 111, the trigger unit 112 sends the stored second indication data to the arithmetic unit 111. In one possible case, after the decoding unit 13 ends decoding, it will send a notification signal to the cache module, and the notification signal indicates that the decoding unit 13 has completed decoding. The trigger unit 112 located in the cache module can determine that the decoding unit 13 has completed decoding when receiving the notification signal, and send the stored second indication data to the arithmetic unit 111.

[0083] The arithmetic unit 111 adds the data amount 1 indicated by data 1 and the data amount 2 indicated by the second indication data, and uses the sum as the first total amount, which is used to indicate the data amount of decoded data stored in the cache unit 12, that is, the cumulative data amount used by the decoding unit 13 in the two decoding processes at time 1 and time 2.

[0084] In the above process of determining the second data amount based on the data amount 2 used for decoding by the decoding unit 13 at time 2, the determined second data amount can be understood as the first total amount counted at time 2, that is, the process of determining the first total amount based on the first data amount used for decoding by the decoding unit 13 can be understood as the process of updating the first total amount counted according to the first data amount used in the decoding ended at the current time. In some cases, after each decoding by the decoding unit 13, the first statistical unit 11 can update the first total amount based on the first data amount used for the current decoding.

[0085] Therefore, the second data amount refers to the first total amount counted last time, and the first total amount currently counted can also be used as the second data amount for reference in the next decoding. For example, after time 1, the decoding unit 13 also decodes data at time 3. After the decoding unit 13 completes the decoding at time 3, it sends data 3 indicating the data amount 3 used for decoding to the arithmetic unit 111. The trigger unit 112 sends the stored data indicating the sum of data amount 1 and data amount 2 to the input end of the arithmetic unit 111, that is, the data indicating the first total amount counted previously. The arithmetic unit 111 adds the data amount 3 as the first data amount to the first total amount counted previously, and obtains a new first total amount as the sum of data amount 1, data amount 2 and data amount 3. Based on the data amount used for each decoding, the first total amount counted is updated, so that the data amount of the decoded data currently stored in the cache unit 12 is accurately indicated according to the first total amount.

[0086] Case 2: the first total amount of data includes the second total amount, and the second total amount indicates the amount of undecoded data stored in the cache unit 12 .

[0087] The second total amount in case 2 belongs to the total amount of data obtained by cumulative subtraction, wherein the undecoded data is the available data that is not decoded at the current moment and can be used in the subsequent decoding process. Continuing to take the amount of data used by the decoding unit 13 at moment 1 as data amount 1, the amount of data used at moment 2 as data amount 2, and the amount of data used at moment 3 as data amount 3 as an example, the process of interactively determining the second total amount by the arithmetic unit 111 and the trigger unit 112 is explained.

[0088] When the total amount of data stored in the cache unit 12, that is, the total memory capacity of the cache unit 12 is data amount 4, after the arithmetic unit 111 receives data 2 indicating data amount 2, since the decoding unit 13 has not decoded before time 2, the data stored in the cache unit 12 has not been decoded, and the initial value of the arithmetic unit 111 at time 2 is data amount 4. The arithmetic unit 111 can use the data amount 4 to subtract the data amount 2, and the difference 1 obtained indicates the amount of data that has not been decoded in the cache unit 12 after the decoding unit 13 completes the decoding at time 2. The arithmetic unit 111 sends the data indicating the difference 1 to the trigger unit 112 for storage. Among them, the difference 1 is also the second data amount, and the data indicating the difference 1 is also the second indication data.

[0089] Afterwards, the decoding unit 13 completes decoding at time 1 and sends data 1 indicating data amount 1 to the arithmetic unit 112. The trigger unit 112 also sends the stored data indicating difference 1 to the arithmetic unit 111. The arithmetic unit 111 subtracts data amount 1 from difference 1, and the obtained difference 2 is the second total amount counted when time 1 is the current time, indicating the amount of data that has not been decoded and stored in the cache unit 12 after the decoding unit 13 decodes at time 1. The arithmetic unit 111 sends the data indicating difference 2 to the trigger unit 112, and the trigger unit 112 updates the stored data from the data indicating difference 1 to the data indicating difference 2, thereby updating the second total amount.

[0090] Afterwards, the decoding unit 13 completes decoding at time 3, and sends data 3 indicating data amount 3 to the arithmetic unit 111. The trigger unit 112 also sends the stored data indicating difference 2 to the arithmetic unit 111. The difference 2 indicates the second data amount referenced when the current time is time 3. The arithmetic unit 111 subtracts difference 2 from data amount 3, and the calculated difference is the second total amount at time 3. The second total amount reflects the available data amount stored in the cache unit 12 at time 3. The arithmetic unit 111 outputs the data indicating the second total amount, and the trigger unit 112 receives and stores the data indicating the second total amount.

[0091] Figure 3 In the figure, the first statistical unit 11 includes the trigger unit 112 because the arithmetic unit 111 does not have a storage function, and the arithmetic unit 111 will refer to the second data amount counted at the historical moment in the process of counting the total amount of the first data. Therefore, the trigger unit 112 will be used to store the second indication data indicating the second data amount calculated at the historical moment. However, in actual applications, the first statistical unit 11 can be other structures. For example, the first statistical unit 11 only includes the arithmetic unit 111, and the arithmetic unit 111 has a storage function. After calculating the second data amount, the second indication data indicating the second data amount can be stored, so that when the first indication data is received, the second indication data stored in the storage space can be read, and the second data amount indicated by the second indication data and the first data amount indicated by the first indication data can be processed to obtain the total amount of the first data.

[0092] Optionally, the first statistical unit 11 may also connect the output end and the input end of the arithmetic unit 111 to record the second indication data outputted by the arithmetic unit 111 last time. For a structural diagram of the arithmetic unit 111, see Figure 4 , Figure 4In the embodiment, the output end of the arithmetic unit 111 is connected to the input end of the arithmetic unit 111. In this case, the calculation result outputted by the arithmetic unit 111 each time will be used as the input for the next time. The arithmetic unit 111 thus receives the second indication data, and calculates the first total data amount based on the second data amount indicated by the second indication data and the first data amount indicated by the first indication data sent by the decoding unit 13 at the current moment.

[0093] Regardless of the method used by the first statistical unit 11 to count the total amount of the first data, after counting the total amount of the first data, it is possible to determine whether the total amount of the first data meets the removal condition, so as to perform different operations according to the determination result.

[0094] Among them, the fact that the total amount of the first data meets the removal condition indicates that the amount of data to be decoded stored in the cache unit 12 is less than the second bit width. Since the data read by the decoding unit 13 each time is the second bit width, if the amount of data to be decoded in the cache unit 12 is less than the second bit width, the decoding unit 13 cannot extract enough data for decoding at the next decoding, which leads to decoding failure. Based on this, the cache unit 12 will remove the data and move out the stored decoded data to free up memory space for writing the data to be decoded, ensuring that the amount of available data in the memory space is greater than the second bit width, and the decoding unit 13 can read the data smoothly. The embodiments of the present application do not limit the removal conditions. The total amount of the first data in different situations corresponds to different removal conditions. Next, different removal conditions are illustrated with examples for situation one and situation two in the above embodiments, respectively.

[0095] Removal condition 1: The first total amount is greater than the first bit width.

[0096] Removal condition 1 corresponds to case 1 in which the total amount of the first data is the first total amount. For example, the first bit width is the difference between the total memory amount of the cache unit 12 and the second bit width, indicating the amount of decoded data stored in the cache unit 12 when only the second bit width of data is left undecoded in the cache unit 12. The total memory amount of the cache unit 12 can be determined based on the maximum code length, for example, the total memory amount is determined to be the maximum code length × 2. The first bit width and the second bit width can be different values, for example, if the total memory amount is 3I and the second bit width is 1, then the first bit width is 2I, and I is a positive integer. The first bit width and the second bit width can also be the same value, for example, if the total memory amount is 2I and the second bit width is 1, then the first bit width is 1. Regardless of the first bit width, the first statistical unit 11 can compare the first total amount and the first bit width, and determine that the first total amount meets the removal condition when the first total amount is greater than the first bit width.

[0097] Continue with the above Figure 3Taking the first statistical unit 11 including the arithmetic unit 111 and the trigger unit 112 as an example, after receiving the data indicating the first total amount output by the arithmetic unit 111, the trigger unit 112 will not only store the data indicating the first total amount, but also compare the first total amount with the first bit width, and determine that the first total amount meets the removal condition when the first total amount is greater than the first bit width. Figure 5 As shown, the output end of the trigger unit 112 is connected to the comparator, and the trigger unit 112 sends data indicating the first total amount to the comparator. The comparator compares the first total amount with the first bit width. When the first total amount is greater than the first bit width, it is determined that the first total amount meets the removal condition. When the first total amount is not greater than the first bit width, it is determined that the first total amount does not meet the removal condition.

[0098] Removal condition 2: the second total amount is less than the second bit width.

[0099] Removal condition two corresponds to situation two where the total amount of the first data is the second total amount. By way of example, the process in which the first statistical unit 11 compares the second total amount and the second bit width is similar to the process in which the first statistical unit 11 compares the first total amount and the first bit width. For the specific process, please refer to the relevant description of removal condition one, which will not be repeated here.

[0100] Regardless of the method used by the first statistical unit 11 to determine whether the first data volume meets the removal condition, the first statistical unit 11 can output an identification signal to the cache unit 12 when the first data volume meets the removal condition. After receiving the identification signal, the cache unit 12 determines that the first data volume meets the removal condition and starts to perform the removal operation. Figure 5 Taking the first statistical unit 11 shown as an example, after the trigger unit 112 sends data indicating the first total amount to the comparator, the comparator may, based on the comparison result of the first total amount and the first bit width, send an identification signal to the cache unit 12 when the first total amount is greater than the first bit width, that is, when the first total amount meets the removal condition; when the first total amount is not greater than the first bit width, the comparator limits the sending of the identification signal.

[0101] Based on the description of the above situation one and situation two, it can be known that after each decoding by the decoding unit 13, the first statistical unit 11 will update the total amount of historical data as the second data amount according to the first data amount used for the current decoding, and obtain the total amount of first data at the current moment. That is, after each decoding, the first statistical unit 11 will count a total amount of first data, and determine whether the removal condition is met based on the counted total amount of first data. If the removal condition is not met, the cache unit 12 will not remove the stored data. If the removal condition is met, the cache unit 12 will remove the stored data.

[0102] That is, although the first statistical unit 11 counts the total amount of the first data after each decoding, the cache unit 12 does not remove the stored data after each decoding. The number of times the data is removed is less than the number of decodings by the decoding unit 13. By reducing the number of times the cache unit 12 removes data, the power consumption of the cache unit 12 is reduced.

[0103] Exemplarily, the cache unit 12 can remove the decoded first data from the stored data after the total amount of the first data meets the removal condition. The first data is data in the cache unit 12 starting from the lowest bit and having a length equal to the first bit width, and the lowest bit is, for example, 0.

[0104] Figure 6 A schematic diagram of a cache of first data provided in an embodiment of the present application, see Figure 6 , the cache unit 12 stores a total of muxword*2 bits of data, Figure 6 In the example, the decoded data in the stored data is marked in black, the undecoded data in the stored data is marked in white, muxword indicates the first bit width, and the first data to be removed in the cache unit 12 is Figure 6 The starting point is bit 0, the ending point is muxword-1, and the length is the data of the first bit width muxword.

[0105] After determining the first data to be removed, the cache unit 12 may remove the first data from the memory space, for example, by shifting the first data from the stored data. Figure 7 , Figure 7 (1) corresponds to Figure 6 The data before shifting is shown. Figure 7 (2) indicates the data after shifting, Figure 7 In the example, the cache unit 12 can shift the stored data right by muxword bits as a whole, and the shifted data is as follows: Figure 7 As shown in (2), the data of muxword-1 bit before the shift is moved to bit 0, and Figure 7 The first data before the muxword-1 bit in (1) is all moved out of the storage space of the cache unit 12 and discarded. The above shifting may be called truncation in some cases, or expressed as >>.

[0106] Exemplarily, after removing the first data, the cache unit 12 can also obtain second data having a length of the first bit width from the external storage module and store the second data. By obtaining and storing the second data, it is ensured that the amount of undecoded data stored in the cache unit 12 is greater than the second bit width, so that the data required by the decoding unit 13 can be provided when the next decoding starts.

[0107] In a possible implementation, the external storage module refers to a module connected to the cache unit 12 for storing data. The external storage module includes a memory, and the memory is, for example, a SRAM (Static Random-Access Memory).

[0108] Optionally, the cache unit 12 can directly read the data in the external storage module, or can indirectly read the data in the external storage module. Taking the external storage module as a memory as an example, the encoding result obtained by entropy encoding will be first stored in the memory, and then sent from the memory to the buffer, and multiple encoding results of indefinite length will be generated into data with a fixed bit width through the buffer, and the fixed bit width is such as the second bit width in the above embodiment, and the cache unit 12 then obtains the second data from the buffer.

[0109] Since the memory capacity of the buffer is much larger than the memory capacity of the cache unit 12, the memory capacity of the cache unit 12 is used as the above Figure 6 Taking the 2 muxword shown as an example, the memory capacity of the buffer may be 100 muxword. If the decoding unit 13 reads data directly from the buffer, the data reading rate is slow. Therefore, the data stored in the buffer is first written into the cache unit 12. For example, the data is read from the buffer twice, and the length of the data read each time is muxword. Then the cache unit 12 provides the data to be decoded to the decoding unit 13 to improve the data reading rate and ensure the decoding efficiency.

[0110] Based on the above situation that the cache unit 12 obtains the second data from the buffer, the decoding circuit can also send a control signal to the buffer so that the buffer returns the second data based on the control signal. Optionally, the control signal can be sent by the first statistical unit 11. For example, after determining that the total amount of the first data meets the removal condition, the first statistical unit 11 not only sends an identification signal to the cache unit 12 to prompt the cache unit 12 to remove the first data in time, but also sends a control signal to the buffer to prompt the buffer to return the second data, so that after the cache unit 12 vacates the memory space, the data can be written in time.

[0111] Alternatively, the decoding circuit may also be sent a control signal by the cache unit 12. For example, after the cache unit 12 completes the removal operation and clears the first data from the memory space, it sends a control signal to the buffer to prompt the buffer to send the second data. The control signal is sent by the cache unit 12 to ensure that the first data has been removed when the cache unit 12 receives the second data, and the second data can be directly written into the memory space after reaching the cache unit 12, thereby avoiding queuing due to insufficient memory space and packet loss exceptions that occur when queuing and waiting to be written.

[0112] In a possible case, the decoding circuit may also send the control signal through a unit independent of the first statistical unit 11 and the cache unit 12 . Figure 8 A schematic diagram of the structure of another cache module provided in an embodiment of the present application, Figure 8 In the decoding circuit, the decoding circuit further includes a control unit 14, which belongs to a unit in the cache module. The control unit 14 is used to control the cache unit 12 to receive the second data to be decoded when the total amount of the first data meets the removal condition.

[0113] See also Figure 8 , the control unit 14 is connected to the first statistical unit 11, the cache unit 12 and the buffer respectively. The control unit 14 can receive the identification signal sent by the first statistical unit 11, and send a control signal to the buffer based on the identification signal. After receiving the control signal, the buffer reads data with a length of the first bit width from the lowest bit as the second data based on the control signal, and sends the second data to the control unit 14. After receiving the second data, the control unit 14 sends the received second data to the cache unit 12, so that the cache unit 12 obtains the second data.

[0114] Regardless of the method by which the cache unit 12 obtains the second data, the second data can be written into the cache space after receiving the second data. Optionally, the cache unit 12 can determine the starting position of the second data based on the highest bit of the stored data and write the second data. The writing process is described in detail in Figure 7 , Figure 7 In (2), the highest bit of the data stored in the cache unit 12 is muxword-1, and the second data stored is data between muxword-1 and muxword*2-1. The process of writing the second data is also Figure 7 Left shift muxword as shown.

[0115] In addition, the above example is intended to illustrate the process of removing the first data and writing the second data in the cache unit 12, rather than to limit the stored data. In some cases, the first data removed by the cache unit 12 can be all the decoded data in the stored data. For example, there is data with a length of the first bit width in the cache unit 12 that has been decoded, so the first data removed is all the decoded data. In this case, after writing the second data, all the data stored in the cache unit 12 are undecoded data.

[0116] Optionally, the first data removed by the cache unit 12 may be a decoded portion of the stored data, for example Figure 7As shown, there is data of length N in the cache unit 12 that has been decoded, and N is greater than the first bit width muxword, so the first data removed is part of the decoded data. After writing the second data, the data stored in the cache unit 12 also includes the decoded data, for example Figure 7 The data marked in black in (2).

[0117] However, no matter what the data stored in the cache unit 12 is, the cache unit 12 can send the third data to be decoded to the decoding unit 13 during the next decoding. Fig. 9 The decoding circuit also includes a second statistical unit 15, which is also a unit in the cache module. The second statistical unit 15 is used to count the total amount of second data according to the amount of data used for at least one decoding by the decoding unit 13. The total amount of second data indicates the amount of decoded data stored in the cache unit 12; the cache unit 12 can determine the third data to be decoded from the stored data according to the second total amount of data, and send the third data to the decoding unit 13.

[0118] The process of the second statistical unit 15 counting the second data amount is similar to the process of the first statistical unit 11 counting the second data amount, and the relevant contents of the above embodiment can be referred to, and will not be repeated here. Fig. 9 After each decoding, the decoding unit 13 sends data indicating the amount of data used in this decoding to the first statistical unit 11 and the second statistical unit 15. The first statistical unit 11 updates the first total data amount according to the amount of data indicated by the received data, and the second statistical unit 15 updates the second total data amount according to the amount of data indicated by the received data.

[0119] The second statistical unit 15 sends data indicating the total amount of the second data calculated each time to the cache unit 12, so that the cache unit 12 locates the lowest bit of the undecoded data in the stored data according to the total amount of the second data, selects the third data with a length of the second bit width starting from the determined lowest bit, and sends the selected third data to the decoding unit 13.

[0120] Although the cache unit 12 may or may not remove the first data, regardless of whether the cache unit 12 removes the first data, the cache unit 12 will locate the third data according to the total amount of the second data. Next, examples are given of the third data in different scenarios for different situations of whether the cache unit 12 removes the first data.

[0121] Scenario 1: When the total amount of the first data satisfies the removal condition, the value of the least significant bit of the third data is equal to the difference between the total amount of the second data and the first bit width.

[0122] The total amount of the first data meets the removal condition, and therefore, the data stored in the cache unit 12 is shifted by the first bit width as a whole, and the amount of decoded data stored in the cache unit 12 is also changed from the total amount of the second data to the difference between the total amount of the second data and the first bit width. The cache unit 12 can determine the difference as the lowest bit of the third data, and locate the third data from the stored data based on the lowest bit.

[0123] Continue with Figure 7 As an example, the data storage situation shown in the figure is Figure 7 The black mark in indicates the decoded data, that is, the second total data. Although the second total data is N, since the first total data meets the removal condition, the cache unit 12 performs a shift operation, and the data stored in the cache unit 12 becomes Figure 7 In the case shown in (2), the undecoded data is shifted right by the first bit width muxword. Therefore, in the cache unit 12 after the shift, the N-muxword-1th data starts to be the undecoded data. The cache unit 12 can use N-muxword-1 as the lowest bit of the third data and select muxword data to the left to obtain Figure 7 The third data shown in (2) is sent to the decoding unit 13.

[0124] Scenario 2: When the total amount of the first data does not satisfy the shift condition, the value of the least significant bit of the third data is equal to the total amount of the second data.

[0125] In one possible case, since the first data amount does not meet the shift condition, the cache unit 12 does not perform the removal operation, and the amount of decoded data in the data stored in the cache unit 12 is still the second data amount. The cache unit 12 can directly use the second data amount as the value of the lowest bit of the third data.

[0126] Fig.10 A schematic diagram of a data decoding process provided in an embodiment of the present application, see Fig.10 , the cache unit 12 sends the data of length muxword to the decoding unit 13, the decoding unit 13 decodes the M bits of data, and returns the data indicating the M bits to the cache unit 12 through the second statistical unit 15, the cache unit 12 determines that the total amount of the second data is M based on the received data, and because the total amount of the first data does not meet the removal condition at this time, the cache unit 12 does not remove the first data, so the cache unit 12 sends the third data to the decoding unit 13 next time, Fig.10 As shown, the least significant bit is determined as M bits, data with a length of muxword bits is taken backward as the third data, and the third data is returned to the decoding unit 13.

[0127] Next, Fig.11The cache module in the decoding circuit shown in the figure illustrates the operation of each unit in the cache module after each decoding by the decoding unit 13 . Fig.11 In the embodiment, the subtracter corresponds to the arithmetic unit 111, the two FFs (Flip-Flop, trigger) configured in the cache module, one is used as the trigger unit 112, the other is used as the cache unit 12, the adder is used as the second statistical unit 15, and the buffer read control unit is used as the control unit 14. The decoding unit 13 is connected to the trigger 12, the subtractor 111 and the adder 15 respectively.

[0128] For example, when the first bit width and the second bit width are both muxword, the total memory capacity of the cache unit 12 is Fig.10 In the case of 2muxword shown, Fig.11 The processing of each unit in the process includes: the cache unit 12 is as follows Fig.10 As shown, the data of muxword bits is read, and the read data is sent to the decoding unit 13. After the first decoding is completed, the decoding unit 13 sends the first indication data indicating the first data amount i_used_bits used for decoding to the arithmetic unit 111 and the second statistical unit 15 respectively. Since the decoding unit 13 is the first decoding, the second data amount in the arithmetic unit 111 is the memory amount 2muxword of the cache unit 12. The arithmetic unit 111 uses 2muxword-i_used_bits to obtain the first data total amount 1. The first data total amount 1 indicates the data amount of the undecoded data stored in the cache unit 12. In some cases, the first data total amount 1 can be as shown in FIG. Fig.11 The one shown is called ssmbuff_fullness.

[0129] The arithmetic unit 111 sends the data indicating the first data total amount 1 to the trigger unit 112. The trigger unit 112 stores the data indicating the first data total amount 1 and sends the data indicating the first data total amount 1 to the comparator. The comparator compares the first data total amount 1 and muxword. Since the first data total amount 1 is greater than muxword, the comparator does not output a flag signal, and the cache unit 12 does not perform a shift operation.

[0130] The second statistical unit 15 receiving the data indicating i_used_bits will also add i_used_bits and the initial value 0 to obtain the second data total amount 1, and send the data indicating the second data total amount 1 to the cache unit 12. The cache unit 12 Fig.10 The lowest bit of the third data is M, and muxword data is selected from M to the left, that is, Fig.10The data between M and muxword-1+M in the address is the third data, the third data will be copied, and the copied third data will be sent to the decoding unit 13.

[0131] After completing the decoding, the decoding unit 13 again sends data indicating the first data amount 2 used for decoding to the arithmetic unit 111. At this time, the trigger unit 112 also sends the stored data indicating the second data amount 2 to the arithmetic unit 111. The arithmetic unit 111 subtracts the first data amount 2 from the second data amount 2 to obtain the first data total amount 2, which is the new first data total amount, and sends the data indicating the first data total amount 2 to the trigger unit 112. The trigger unit 112 updates the stored data from the data indicating the first data total amount 1 to the data indicating the first data total amount 2, and sends the data indicating the first data total amount 2 to the comparator.

[0132] The comparator compares the first data amount 2 and the size of muxword. Since the first data amount 2 is smaller than muxword, a flag signal is output to the cache unit 11 and the control unit 14 respectively. After receiving the flag signal, the cache unit 12 can Fig.10 Perform the removal operation as shown. Fig.10 In the figure, the first data amount 2 used by the decoding unit 13 for the second decoding is N1, N1+M=N, and the data between the 0th bit to the Nth bit in the cache unit 12 are all decoded data. The amount of decoded data is greater than muxword, and the data stored in the cache unit 12 is right-shifted by muxword, thereby removing it as the first data.

[0133] Optionally, after receiving the flag signal, the control unit 14 sends a control signal to the buffer, receives the second data of the muxword bit returned by the buffer, and sends the received second data to the cache unit 12. The cache unit 12 receives the second data and shifts muxword left based on the second data to write the second data into the memory space.

[0134] In addition, in addition to sending data indicating the first data amount 2 to the arithmetic unit 111, the decoding unit 13 also sends data indicating the first data amount 2 to the second statistical unit 15. After receiving the data indicating the first data amount 2, the second statistical unit 15 adds the first data amount 2 and the second data amount 1 indicated by the data returned from the output end to obtain the second data amount 2, and sends the data indicating the second data amount 2 to the cache unit 12. The cache unit 12 is based on the received data indicating the second data amount 2. Although the second data amount 2 is N, the cache unit 12 has removed the first data of muxword bits, thereby locating the lowest bit of N-muxword, and selecting the data of muxword length to the left to obtain the third data used for the next decoding, and sending the third data to the decoding unit 13. Based on the above example, it can be seen that the data of the cache unit 12 each time is [L+muxword-1, L], totaling muxword bits, where L is the lowest bit determined based on the second data amount.

[0135] In a possible case, the first statistical unit 11 and the second statistical unit 15, in addition to performing the above-mentioned cumulative subtraction or cumulative addition operations, also perform data update according to the removal operation of the cache unit 12. Fig.11 Taking the cache module shown as an example, in addition to sending a flag signal to the cache unit 12 and the control unit 14, the selector also sends a flag signal to the trigger unit 112. Each time the trigger unit 112 receives the flag signal, it adjusts the second data amount based on the first bit width. If the second data amount is used to calculate the first total amount, since the cache unit 12 has removed the first data, the decoded data stored in the cache unit 12 is reduced by the first bit width. The trigger unit 112 can subtract the first bit width from the second data amount to obtain a new second data amount, and send the data indicating the new second data amount to the algorithm unit 111.

[0136] Alternatively, if the second data amount is used to calculate the second total amount, since the cache unit 12 will write new second data after removing the first data, the undecoded data stored in the cache unit 12 increases by the first bit width, and the trigger unit 112 can add the second data amount to the first bit width to obtain a new second data amount. In addition, the above-mentioned identification signal can also be sent directly to the arithmetic unit 111, and the arithmetic unit 111 will calculate the first data total amount based on the second data amount, the first data amount and the first bit width after receiving the identification signal, and the embodiment of the present application is not limited to this.

[0137] Similar to the first statistical unit 11, the second statistical unit 15 may also receive the identification signal and, in the next calculation of the second total data amount, in addition to summing the currently used data amount, subtract the first bit width from the sum to obtain a new second total data amount.

[0138] In addition, the above examples are intended to illustrate the processing of the decoding circuit, rather than to limit the various units included in the decoding circuit. The decoding circuit may also include more units than those shown in the above embodiments. In some cases, the decoding circuit may also be split into multiple independent circuits. For example, the cache module in the decoding circuit is a cache circuit independent of the decoding unit, but is connected to the decoding unit 13.

[0139] Furthermore, the embodiments of the present application do not limit the structure of each unit in the decoding circuit. Taking the cache module in the decoding circuit as an example, Fig.11 The cache unit 12 shown may include one subunit or multiple subunits. Taking the multiple subunits including the first subunit and the second subunit as an example, the first subunit is used to store data, and the second subunit is connected to the second statistical unit 15, and is used to determine the lowest bit of the third data according to the total amount of the second data output by the second statistical unit 15, and send the determined lowest bit information to the first subunit, and the first subunit determines the third data according to the lowest bit, and sends the third data to the decoding unit 13. Among them, the first subunit is, for example, FF, and the second subunit is, for example, MUX (data selector).

[0140] In summary, the decoding circuit provided in the embodiment of the present application counts the amount of data used for decoding by the decoding unit 13 through the first statistical unit 11, and removes the stored first data only when the total amount of the first data meets the removal condition. The frequency of data removal is low, which reduces the working time of the circuit and has low power consumption. Moreover, even if the amount of data used for decoding is different, the decoding circuit is applied to variable-length decoding, and each removal by the cache unit 12 is a fixed-length removal, and the length of the first data removed is a fixed first bit width. The cache unit 12 only needs to support the removal operation of one amount of data, which requires low complexity, and the circuit size of low complexity is smaller.

[0141] The present application also provides a data processing method, which can be Figure 1-Figure 5 , Figure 8 , Fig. 9 or Fig.11 Any of the decoding circuits shown in the figure is executed, and the flowchart of the method is as follows Fig.12 As shown, it includes steps 1201 to 1204.

[0142] In step 1201, data to be decoded is obtained and decoded, wherein the amount of data to be decoded each time is not fixed.

[0143] In a possible implementation, the decoding circuit can decode the acquired data by copying the data to be decoded cached in the cache unit. Figure 1 The process of the decoding circuit in the illustrated embodiment acquiring and decoding data through the decoding unit 13 is similar, and reference may be made to the relevant description, which will not be repeated here.

[0144] In step 1202, a total amount of first data is counted based on an amount of data used for at least one decoding.

[0145] Optionally, the decoding circuit can count the total amount of the first data through the first statistical unit, and the first statistical unit can obtain the first data amount used in the decoding ended at the current moment; determine the total amount of the first data according to the first data amount and the second data amount, and the second data amount is determined based on the data amount used in the decoding ended at the historical moment. For the process of the first statistical unit determining the total amount of the first data, please refer to Figure 1 In the illustrated embodiment, the process of the first statistical unit 11 determining the total amount of first data is not described again.

[0146] Exemplarily, the first total amount of data based on the statistics of the amount of data used for at least one decoding may include a first total amount or a second total amount, wherein the first total amount indicates the amount of data of the stored decoded data, and the second total amount indicates the amount of data of the stored undecoded data. For the specific acquisition process of the first total amount and the second total amount, please refer to the above Figure 1 The process of obtaining the first total amount in case 1 and the process of obtaining the second total amount in case 2 in the illustrated embodiment will not be repeated here.

[0147] In step 1203, when the total amount of first data meets the removal condition, the decoded first data is removed from the stored data with decoding requirements, and the length of the first data is the first bit width.

[0148] Exemplarily, the decoding circuit determines whether the first data total amount satisfies the removal condition through the first statistical unit. Since the first data total amount may be the first total amount or the second total amount, the removal condition compared with different first data total amounts is also different. For example, when the first data total amount includes the first total amount, the removal condition includes that the first total amount is greater than the first bit width; when the first data total amount includes the second total amount, the removal condition includes that the second total amount is less than the second bit width, and the second bit width is the difference between the total amount of stored data and the first bit width.

[0149] For the process of comparing the first total amount and the removal condition, please refer to the above Figure 1 The comparison process in the removal condition 1 in the embodiment shown in the figure can be referred to in the above Figure 1 In the illustrated embodiment, the comparison process in condition 2 is removed and will not be described again.

[0150] Optionally, after determining whether the total amount of the first data satisfies the removal condition, the first statistical unit may send a control signal to the cache unit to prompt the cache unit to remove the stored first data if the total amount of the first data satisfies the removal condition. Figure 1 The process of removing the first data by the cache unit 12 is not described again.

[0151] In step 1204, second data to be decoded having a length equal to the first bit width is obtained from an external storage module, and the second data is stored.

[0152] In one possible case, the decoding circuit indirectly obtains data in the external storage module through the buffer. Taking the external storage module as a memory, the data obtained by entropy coding is first stored in the memory, and then sent from the memory to the buffer, and then the decoding circuit reads the second data from the buffer. Optionally, the process of obtaining the second data from the buffer includes: sending a control signal to the buffer, the buffer is used to store the data to be decoded; receiving the second data returned by the buffer based on the control signal. For the process of the cache unit obtaining the second data, please refer to the above Figure 1 The process of the cache unit 12 acquiring the second data in the illustrated embodiment will not be described in detail here.

[0153] Optionally, if the total amount of the first data does not meet the removal condition, the cache unit will limit the removal of the stored data, that is, even if there is decoded data in the memory space, the cache unit will not remove the decoded data. Regardless of whether the cache unit removes the first data according to the total amount of the first data, the third data used for the next decoding can be determined after each decoding.

[0154] Exemplarily, the process of determining the third data includes: counting the total amount of second data according to the amount of data used for at least one decoding, the total amount of second data indicating the amount of stored decoded data; and determining the third data to be decoded from the stored data according to the total amount of second data. For the process of counting the total amount of second data, see the above Fig. 9 The process of the second statistical unit 15 counting the total amount of second data is not repeated here.

[0155] In one possible case, when the first data amount does not meet the removal condition, the value of the lowest bit of the third data is equal to the second data amount; or, when the first data amount meets the removal condition, the value of the lowest bit of the third data is equal to the difference between the second data amount and the first bit width. For the process of determining the third data according to the second data amount, please refer to the above Fig. 9 The process of the cache unit 12 determining the third data according to the total amount of the second data is not described here. No matter how the cache unit determines the third data, the determined third data can be sent to the decoding unit for the next decoding.

[0156] In summary, the data processing method provided by the embodiment of the present application removes the stored first data only when the total amount of the first data meets the removal condition, and the frequency of data removal is low, which reduces the working time of the circuit and has low power consumption. Moreover, even if the amount of data used for decoding is different, the decoding circuit is applied to variable-length decoding, and each removal of the cache unit is a fixed-length removal, and the length of the first data removed is a fixed first bit width. The cache unit only needs to support the removal operation of one amount of data, which requires low complexity, and the circuit size of low complexity is smaller.

[0157] The present application provides an electronic device including a decoding circuit and a storage module, wherein the decoding circuit is used to execute Fig.12 The data processing method shown reads the second data from the storage module. Optionally, the storage module includes an SRAM.

[0158] Exemplarily, the electronic device may be any device with a display function, and may be any terminal. Optionally, the terminal may be any electronic product that can interact with a user through one or more methods such as a keyboard, a touch pad, a touch screen, a remote control, voice interaction, or a handwriting device, such as a PC (Personal Computer), a mobile phone, a smart phone, a PDA (Personal Digital Assistant), a wearable device, a PPC (Pocket PC), a tablet computer, a smart car machine, a smart TV, etc.

[0159] The present application also provides a chip including a decoding circuit for executing Fig.12 The data processing method shown.

[0160] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.) and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant laws, regulations and standards of relevant countries and regions. For example, the total amount of first data involved in this application is obtained with full authorization.

[0161] It should be understood that the "plurality" mentioned in this article refers to two or more. "And / or" describes the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0162] The above description is only an exemplary embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A decoding circuit, characterized in that: The decoding circuit includes a first statistical unit, a cache unit and a decoding unit; The decoding unit is used to read the data stored in the cache unit and decode the read data, and the amount of data decoded by the decoding unit each time is not fixed; The first statistical unit is used to count the total amount of first data according to the amount of data used for at least one decoding by the decoding unit; The cache unit is used to remove the decoded first data from the stored data when the total amount of the first data meets the removal condition, and the length of the first data is the first bit width; The cache unit is further used to obtain second data to be decoded with a length of the first bit width from an external storage module, and store the second data.

2. The circuit according to claim 1, characterized in that The first statistics unit is used to receive first indication data sent by the decoding unit, where the first indication data indicates a first data amount used by the decoding unit in decoding ended at a current moment; The first total amount of data is determined based on the first amount of data and a second amount of data, where the second amount of data is determined based on an amount of data used in decoding ended by the decoding unit at a historical moment.

3. The circuit according to claim 2, characterized in that The first statistical unit includes an arithmetic unit and a trigger unit; the arithmetic unit is configured to receive the second indication data indicating the second data amount sent by the trigger unit and the first indication data sent by the decoding unit, calculate the first data total amount according to the first data amount and the second data amount, and send data indicating the first data total amount to the trigger unit; The trigger unit is used to store the data indicating the total amount of the first data sent by the arithmetic unit; The arithmetic unit is further used to update the total amount of first data stored in the trigger unit when the decoding unit completes the next decoding.

4. The circuit according to any one of claims 1 to 3, characterized in that: The first data total amount includes a first total amount, the first total amount indicates a data amount of the decoded data stored in the cache unit, and the removal condition includes that the first total amount is greater than the first bit width; Alternatively, the first total amount of data includes a second total amount, the second total amount indicates the amount of undecoded data stored in the cache unit, and the removal condition includes that the second total amount is less than a second bit width, and the second bit width is the difference between the total memory capacity of the cache unit and the first bit width.

5. The circuit according to any one of claims 1 to 3, characterized in that: The decoding circuit also includes a control unit; The control unit is used to control the cache unit to receive the second data to be decoded when the total amount of the first data meets the removal condition.

6. The circuit according to any one of claims 1 to 3, characterized in that: The decoding circuit further includes a second statistical unit, the second statistical unit being used to count a second total amount of data according to the amount of data used for at least one decoding by the decoding unit, the second total amount of data indicating the amount of decoded data stored in the cache unit; The cache unit is further configured to determine third data to be decoded from the stored data according to the total amount of the second data, and send the third data to the decoding unit.

7. The circuit according to claim 6, characterized in that When the first total amount of data satisfies the removal condition, the value of the least significant bit of the third data is equal to the difference between the second total amount of data and the first bit width; Alternatively, when the first total amount of data does not satisfy the removal condition, the value of the least significant bit of the third data is equal to the second total amount of data.

8. A data processing method, characterized in that: The method comprises: Acquire data to be decoded, and decode the data to be decoded, wherein the amount of data decoded each time is not fixed; Counting the first total amount of data according to the amount of data used for at least one decoding; When the total amount of the first data satisfies a removal condition, removing the decoded first data from the stored data with decoding requirements, the length of the first data being the first bit width; Acquire second data to be decoded having a length equal to the first bit width from an external storage module, and store the second data.

9. The method according to claim 8, characterized in that The counting of the first total amount of data according to the amount of data used for at least one decoding comprises: Obtaining a first data amount used in decoding that ends at a current moment; The first total amount of data is determined based on the first amount of data and a second amount of data, where the second amount of data is determined based on an amount of data used in decoding that ends at a historical moment.

10. The method according to claim 8 or 9, characterized in that: The first data total amount includes a first total amount, the first total amount indicates a data amount of the stored decoded data, and the removal condition includes that the first total amount is greater than the first bit width; Alternatively, the first total amount of data includes a second total amount, the second total amount indicates the amount of stored undecoded data, and the removal condition includes that the second total amount is less than a second bit width, and the second bit width is the difference between the total amount of stored data and the first bit width.

11. The method according to claim 8 or 9, characterized in that: The method further comprises: Counting a second total amount of data according to the amount of data used for the at least one decoding, where the second total amount of data indicates the amount of stored decoded data; The third data to be decoded is determined from the stored data according to the second total amount of data.

12. The method according to claim 11, characterized in that When the first total amount of data satisfies the removal condition, the value of the least significant bit of the third data is equal to the difference between the second total amount of data and the first bit width; Alternatively, when the first total amount of data does not satisfy the removal condition, the value of the least significant bit of the third data is equal to the second total amount of data.

13. An electronic device, characterized in that: It comprises a decoding circuit and a storage module, wherein the decoding circuit is used to execute the data processing method according to any one of claims 8 to 12, and read the second data from the storage module.

14. The device according to claim 13, characterized in that The storage module includes a static random access memory SRAM.

15. A chip, characterized in that: The chip comprises a decoding circuit, and the decoding circuit is used to execute the data processing method according to any one of claims 8 to 12.

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