Broadband vector signal generator

Abstract

The invention discloses a broadband vector signal generator, which comprises a multi-path phase locking module, a baseband processing module and a radio frequency processing module, and is used for carrying out phase locking on a synchronous reference signal to obtain five clock signals; obtaining waveform data, and performing digital-to-analog conversion on the waveform data based on the first clock signal to obtain two paths of baseband signals; performing frequency division on the third clock signal to obtain a frequency division signal; taking the second clock signal or the frequency division signal as a local oscillator signal of quadrature modulation, and performing quadrature modulation on the two paths of baseband signals to obtain a quadrature modulation signal; performing power control on the quadrature modulation signal to obtain a first radio frequency signal, a first control signal and a second control signal; performing up-conversion on the first control signal by taking the fourth clock signal as a local oscillator signal of up-conversion to obtain a second radio frequency signal; and performing down-conversion on the second control signal by taking the fifth clock signal as a down-conversion local oscillator signal to obtain a third radio frequency signal. The broadband vector signal generator can realize wide bandwidth and high linearity.

Description

Technical Field

[0001] The present application belongs to the technical field of radio frequency circuits, and in particular relates to a broadband vector signal generator. Background Art

[0002] The RF vector signal generator is a widely used test instrument that can generate any required signal within a specified bandwidth and frequency range to provide specified excitation to the device under test. Therefore, it is widely used in the field of wireless communication testing. It is an important instrument used in the research and development and production of various wireless communication products, as well as aerospace, broadband digital pre-distortion processing (Digital Pre-Distortion, DPD) verification, 6G prediction, and high-end scientific experiments.

[0003] Some of the most common vector signal generators (such as the N5182B vector signal generator) are not suitable for the latest communication test needs. For example, the 2-carrier or 3-carrier test used in 5G NR co-construction and sharing requires a bandwidth of 200MHz or 300MHz, which exceeds the 160MHz range of the N5182B. The 6G-7.125GHz frequency range planned for dedicated 5G also exceeds the highest frequency range of the N5182B. The 320MHz bandwidth and 6GHz-7.125GHz frequency range specified by WiFi7 also exceed the bandwidth and frequency range of the N5182.

[0004] Although the bandwidth of some high-end products can cover multi-carrier needs, the linearity drops sharply during multi-carrier output, some index characteristics are close to or lower than the 5G test standards, and the frequency range of dedicated 5G planning exceeds its highest frequency range, making it difficult to adapt to actual testing needs. Summary of the invention

[0005] The technical purpose of the present application is to provide a broadband vector signal generator to address the technical problems that the current RF vector signal generator has limited frequency bandwidth and poor linearity and cannot meet the latest practical communication test requirements.

[0006] To achieve the above technical objectives, the embodiment of the present application provides a broadband vector signal generator, including: a multi-channel phase-locking module, used to phase-lock a synchronization reference signal to obtain a first clock signal, a second clock signal, a third clock signal, a fourth clock signal, and a fifth clock signal;

[0007] A baseband processing module, used for acquiring waveform data, and performing digital-to-analog conversion on the waveform data based on the first clock signal to obtain two baseband signals;

[0008] A radio frequency processing module, including an orthogonal modulation unit, a power control unit, a frequency divider, an up-conversion unit, and a down-conversion unit;

[0009] The frequency divider is used to divide the frequency of the third clock signal to obtain a divided frequency signal;

[0010] The orthogonal modulation unit is used to use the second clock signal or the frequency-divided signal as a local oscillator signal for orthogonal modulation, and to perform orthogonal modulation on the two baseband signals to obtain an orthogonal modulated signal;

[0011] The power control unit is used to perform power control on the orthogonal modulation signal to obtain a first radio frequency signal, a first control signal and a second control signal;

[0012] The up-conversion unit is used to use the fourth clock signal as an up-conversion local oscillator signal to up-convert the first control signal to obtain a second radio frequency signal;

[0013] The down-conversion unit is used to use the fifth clock signal as a down-converted local oscillator signal to down-convert the second control signal to obtain a third radio frequency signal.

[0014] Further, the multi-channel phase locking module includes a first phase locking unit, a second phase locking unit, a fourth phase locking unit and a fifth phase locking unit;

[0015] The first phase-locking unit is used to phase-lock the synchronization reference signal and then perform power distribution, and output a first phase-locking signal, a second phase-locking signal and a third phase-locking signal;

[0016] The second phase locking unit is used to perform phase locking based on the first phase locking signal to obtain the first clock signal;

[0017] The fourth phase locking unit is used to perform phase locking based on the second phase locking signal to obtain the second clock signal, the third clock signal and the fourth clock signal;

[0018] The fifth phase locking unit is used to perform phase locking based on the third phase locking signal to obtain the fifth clock signal.

[0019] In some possible implementations, the multi-channel phase locking module further includes a third phase locking unit;

[0020] The third phase locking unit is used to phase lock the second phase locking signal to generate a point frequency signal, and send the point frequency signal to the fourth phase locking unit;

[0021] The fourth phase locking unit is further used to lock the frequency of the dot frequency signal and output the second clock signal, the third clock signal and the fourth clock signal.

[0022] Further, the fourth phase-locked unit includes a fourth integrated phase-locked loop, a first one-to-many switch, a many-to-one switch, and a second one-to-many switch connected in sequence, wherein a plurality of radio frequency channels are formed between the first one-to-many switch and the many-to-one switch, and each of the radio frequency channels is provided with a filter;

[0023] The fourth integrated phase-locked loop is connected to an output end of the third phase-locked unit;

[0024] The one-to-many switches are respectively connected to the orthogonal modulation unit, the frequency divider and the up-conversion unit, and are used to output the second clock signal, the third clock signal and the fourth clock signal.

[0025] Further, the first clock signal includes a first clock sub-signal and a second clock sub-signal;

[0026] The baseband processing module includes a processor and a digital-to-analog converter, and the processor and the digital-to-analog converter are connected by a low-voltage differential signal bus;

[0027] The first clock sub-signal is used as a clock reference signal of the processor;

[0028] The second clock sub-signal is used as a clock reference signal of the digital-to-analog converter;

[0029] The processor is used to transmit the waveform data to the digital-to-analog converter;

[0030] The digital-to-analog converter is used to perform digital-to-analog conversion on the waveform data and output two baseband signals.

[0031] Furthermore, the baseband processing module also includes a USB interface and / or a network port, and the USB interface and / or a network port are used to receive control instructions issued by a host computer, and transmit the control instructions to the processor so that the processor performs corresponding operations to obtain operation results, and returns the operation results to the host computer.

[0032] Further, the second phase-locked unit includes a second integrated phase-locked loop and a clock distributor;

[0033] The second integrated phase-locked loop is used to phase-lock the first phase-locked signal to generate a synchronization signal;

[0034] The clock distributor is used to generate the first clock sub-signal based on the synchronization signal by frequency division, and to generate the second clock sub-signal based on the synchronization signal.

[0035] Furthermore, the multi-channel phase-locked module also includes:

[0036] A synchronization reference signal generating unit;

[0037] The synchronization reference signal generating unit includes a crystal oscillator, an external input channel and a switch, the crystal oscillator and the external input channel are connected to one end of the switch, the crystal oscillator is used to generate a local synchronization reference signal, the external input channel is used to input an external synchronization reference signal, and the other end of the switch outputs a selected synchronization reference signal.

[0038] Furthermore, the baseband processing module further includes:

[0039] Trigger unit;

[0040] When the trigger function is set to output mode, each time the waveform file being played back in a loop switches from the end to the beginning, a trigger signal is output through the trigger unit; when the trigger function is set to input mode, each time a trigger signal transmitted by the trigger unit is detected, the waveform file is played back once, wherein the waveform file stores the waveform data.

[0041] Furthermore, the trigger mode of the trigger function is single trigger or continuous trigger.

[0042] Compared with the prior art, the broadband vector signal generator provided in the embodiment of the present application has the following beneficial technical effects: a synchronization reference signal is phase-locked through a multi-channel phase-locked module to obtain multiple clock signals, which can be synchronized and frequency-converted, and can support flexible frequency conversion, thereby generating wide-bandwidth RF signals; the orthogonal modulation unit, the up-conversion unit and the down-conversion unit use different clock signal sources, which helps to improve the stability and accuracy of the signal generated by each unit, and can achieve high-linear signal generation to a certain extent. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The drawings described herein are for explanation purposes only and are not intended to limit the scope of the present application in any way. In addition, the shapes and proportional dimensions of the components in the drawings are only for illustration purposes and are used to help understand the present application. They do not specifically limit the shapes and proportional dimensions of the components of the present application. Under the guidance of the present application, those skilled in the art can select various possible shapes and proportional dimensions to implement the present application according to specific circumstances. In the drawings:

[0044] Figure 1 A schematic diagram of the structure of a broadband vector signal generator provided in an embodiment of the present application;

[0045] Figure 2 A schematic diagram of a portion of the structure of a baseband processing module in a broadband vector signal generator provided in an embodiment of the present application;

[0046] Figure 3 A schematic diagram of the data flow of the external communication interface in the broadband vector signal generator provided in an embodiment of the present application;

[0047] Figure 4 A schematic diagram of the USB interface circuit principle in a broadband vector signal generator provided in an embodiment of the present application;

[0048] Figure 5 A schematic diagram of the LAN interface circuit principle in the broadband vector signal generator provided in an embodiment of the present application;

[0049] Figure 6 A schematic diagram of data flow for high-speed playback of a baseband processing module in a wideband vector signal generator provided in an embodiment of the present application;

[0050] Figure 7 A schematic diagram of the principle of a digital-to-analog converter circuit in a broadband vector signal generator provided in an embodiment of the present application;

[0051] Figure 8 A schematic diagram of the memory circuit principle in the broadband vector signal generator provided in an embodiment of the present application;

[0052] Fig. 9 A schematic diagram of the principle of a synchronization reference signal generating unit in a broadband vector signal generator provided in an embodiment of the present application;

[0053] Fig.10 A schematic diagram of the principle of a first phase-locked unit in a broadband vector signal generator provided in an embodiment of the present application;

[0054] Fig.11 A schematic diagram of the principle of a second phase-locked unit in a broadband vector signal generator provided in an embodiment of the present application;

[0055] Fig.12 A schematic diagram of the principle of the fourth phase-locked unit in the broadband vector signal generator provided in an embodiment of the present application;

[0056] Fig.13 A schematic diagram of the principle of a power control unit in a broadband vector signal generator provided in an embodiment of the present application;

[0057] Reference numerals:

[0058] 10-multi-channel phase-locked module, 20-baseband processing module, 30-radio frequency processing module, 101-first phase-locked unit, 102-second phase-locked unit, 103-third phase-locked unit, 104-fourth phase-locked unit, 105-fifth phase-locked unit, 106-synchronous reference signal generating unit, 201-FPGA, 202-digital-to-analog converter, 203-USB interface, 204-memory, 205-non-volatile storage unit, 206-processing unit, 207-network port, 208-trigger unit, 301-orthogonal modulation unit, 302-power control unit, 303-divider, 304-up conversion unit, 305-down conversion unit, 306-first filtering unit, 307-second filtering unit. DETAILED DESCRIPTION

[0059] In order to enable those skilled in the art to better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of this application.

[0060] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more features.

[0061] like Figure 1 As shown, an embodiment of the present application provides a broadband vector signal generator, including a multi-channel phase-locked module 10, a baseband processing module 20 and a radio frequency processing module 30.

[0062] In a specific implementation, the multi-channel phase-locking module 10 is used to phase-lock the synchronization reference signal to obtain the first clock signal, the second clock signal, the third clock signal, the fourth clock signal and the fifth clock signal. The baseband processing module 20 is used to obtain waveform data, and perform digital-to-analog conversion on the waveform data based on the first clock signal to obtain two baseband signals. The RF processing module 30 includes an orthogonal modulation unit 301, a power control unit 302, a frequency divider 303, an up-conversion unit 304 and a down-conversion unit 305. The frequency divider 303 is used to divide the third clock signal to obtain a divided signal; the orthogonal modulation unit 301 is used to use the second clock signal or the divided signal as the local oscillator signal of orthogonal modulation, and perform orthogonal modulation on the two baseband signals to obtain an orthogonal modulation signal; the power control unit 302 is used to perform power control on the orthogonal modulation signal to obtain a first RF signal, a first control signal, and a second control signal; the up-conversion unit 304 is used to use the fourth clock signal as the local oscillator signal for up-conversion, and perform up-conversion on the first control signal to obtain a second RF signal; the down-conversion unit 305 is used to use the fifth clock signal as the local oscillator signal for down-conversion, and perform down-conversion on the second control signal to obtain a third RF signal.

[0063] The core of the high-speed digital part of the broadband vector signal generator provided by the present application is a processor, and the processor can adopt a field programmable gate array (Field-Programmable Gate Array, FPGA201), such as Figure 1 and Figure 2As shown, the high-speed digital part can also have external communication interfaces such as USB interface 203, network port 207, non-volatile storage unit 205, memory 204, digital-to-analog converter 202, etc.; and the radio frequency part includes multiple phase locking, orthogonal modulation, secondary frequency conversion, power control and filtering units, etc.; the system block diagram of the broadband vector signal generator of the embodiment is shown in Figure 1 shown.

[0064] like Figure 1 As shown, in the embodiment, the memory 204 can be used to store the waveform data that needs to be played back, because the memory 204 has a high speed and a large bandwidth; it can be used for temporary storage required for waveform playback; the data in the memory 204 will disappear after power failure.

[0065] In the embodiment, the most commonly used USB interface 203 and network port 207 can be used as external control interfaces to receive waveform data and control commands sent by the host computer and return the device status; it is the main way for the broadband vector signal generator to communicate with the host computer, and it is also a necessary interface for automatic testing.

[0066] In a specific implementation, the non-volatile storage unit 205 can be used to store the waveform data sent by the user for repeated use. The data in the non-volatile storage unit 205 will not disappear after power failure. The waveform data sent by the user is stored in the memory in the form of a file (waveform file) according to the format, and the file name and basic information are added; when needed later, there is no need to send the waveform data from the host computer, but it can be directly called from the non-volatile storage unit 205. At the same time, the configuration information of the broadband vector signal generator (hereinafter referred to as the device) itself can also be stored in the non-volatile storage unit 205. The non-volatile storage unit 205 used can be in the form of an SD / TF card or a hard disk.

[0067] In the embodiment, the Secure Digital Input and Output (SDIO) method can be used to read and write SD / TF cards, which has the main feature of fast reading and writing speed; the SATA bus can be used to read and write SSD hard disks through the high-speed port of FPGA201 in conjunction with related IP. SSD hard disks have larger capacity and faster reading and writing speeds, but they are more expensive, consume more power, and are larger in size.

[0068] FPGA 201 is used to support the communication protocol with the USB interface 203 and the network port 207 to facilitate communication with the host computer; to realize reading and writing of the non-volatile storage unit 205 to store waveform files and configuration information, etc.; to operate the reading and writing of the memory 204 to store the waveform file data in the memory 204, and to read and pass it to the digital-to-analog converter 202 at high speed during playback; to realize the trigger function; and to interact with the processing unit 206 to pass various commands and perform corresponding operations.

[0069] The baseband processing module 20 may also include a processing unit 206, which is mainly responsible for parsing the control commands sent by the host computer, executing the corresponding operations according to the commands, and returning the results. The processing unit 206 can be an MCU; its main task is to parse various instructions sent by the host computer, then execute them, and return the status results. FPGA201 and the processing unit 206 can generally interact through a set of IO. The control and configuration of other controlled devices such as phase-locked loops, switches, etc. are also controlled by the processing unit 206 through SPI, I2C, IO, etc.

[0070] The digital-to-analog converter 202 converts the waveform data into an analog signal as a baseband input for quadrature modulation. To implement quadrature modulation, the digital-to-analog converter 202 has two independent output channels.

[0071] In some embodiments, the baseband processing module 20 also includes a trigger unit 208, which can be set to an input mode or an output mode. When the trigger function is set to the output mode, each time the waveform file being played back in a loop switches from the end to the beginning, a trigger signal is output through the trigger unit 208 so that other test instruments (such as a spectrum analyzer) can track it; when the trigger function is set to the input mode, the waveform file is played back each time a trigger signal transmitted by the trigger unit 208 is detected.

[0072] In the embodiment, the trigger function is implemented by the logic of FPGA201. When set to output mode, every time the waveform is played back to the end and restarted from the beginning, FPGA201 pulls a narrow pulse on the trigger IO pin; when set to input, every time FPGA201 receives a narrow pulse, it plays back the waveform file from the beginning. In a specific embodiment, the trigger mode of the trigger function is single trigger or continuous trigger. This application implements different trigger functions through FPGA201 logic programming.

[0073] The embodiment functionally implements the interaction between FPGA 201 and external interfaces, the interaction with processing unit 206, the trigger function, the reading and writing and high-speed playback of non-volatile storage unit 205, and the interaction with the host computer.

[0074] The data sent by the host computer can be either a waveform file or a control instruction; the data links of the two are different, such as Figure 3As shown. The waveform data sent by the host computer can be written into the SD / TF non-volatile storage unit 205 for permanent storage as needed; it can also be directly written into the memory 204 for subsequent playback. In some embodiments, the control instructions sent by the host computer are forwarded by FPGA201 and passed to the processing unit 206 for command parsing, executing corresponding operations, and returning status results. For the waveform files already stored in the non-volatile storage unit 205, the FPGA201 can also read the required data from the non-volatile storage unit 205 and write it into the memory 204 by issuing instructions for subsequent playback.

[0075] The USB interface 203 can be implemented by using a USB interface 203 chip, which converts the USB interface 203 into a local IO and then interacts with the FPGA 201. In some embodiments, the USB uses a USB 3.0 interface chip, model FT601, which is compatible with USB 2.0; it converts the USB interface 203 into a local IO and then interacts with the FPGA 201 for data. Figure 4 shown.

[0076] In order to realize the Gigabit LAN network port 207 and improve the data reading and writing speed; some embodiments use the network port 207 chip model KSZ9031RNX of MicroChip Company to convert Gigabit Ethernet into local high-speed IO, which is convenient for data interaction with FPGA201; in order to be compatible with Visa32 and IEEE488.2 protocols, the network port 207 can be configured as a TCP Server, which is convenient for users to control the vector signal generator through virtual instrument programming to achieve automated testing. LAN interface circuit such as Figure 5 shown.

[0077] In the embodiment, the broadband vector signal generator further includes a power management unit (not shown in the figure), which is a series of power supply systems for providing the required power supply for each device.

[0078] Please continue to see Figure 1 In some embodiments, the multi-channel phase locking module 10 includes a first phase locking unit 101 , a second phase locking unit 102 , a fourth phase locking unit 104 and a fifth phase locking unit 105 .

[0079] The first phase-locked unit 101 is used to perform phase-locking on the synchronization reference signal and then perform power allocation, and output a first phase-locked signal, a second phase-locked signal, and a third phase-locked signal. The second phase-locked unit 102 is used to perform phase-locking based on the first phase-locked signal to obtain a first clock signal. The fourth phase-locked unit 104 is used to perform phase-locking based on the second phase-locked signal to obtain a second clock signal, a third clock signal, and a fourth clock signal. The fifth phase-locked unit 105 is used to perform phase-locking based on the third phase-locked signal to obtain a fifth clock signal.

[0080] The fourth phase-locked unit 104 generally adopts a fractional frequency division method, which will bring integer boundary spurious. In order to obtain the best EVM (Error Vector Magnitude), ACP (Adjacent Channel Power) and spurious performance, the output of the fourth phase-locked unit 104 must be able to effectively suppress boundary spurious. For this reason, in some embodiments, the multi-channel phase-locked module 10 also includes a third phase-locked unit 103; the third phase-locked unit 103 is used to phase-lock the second phase-locked signal to generate a point frequency signal, and send the point frequency signal to the fourth phase-locked unit 104. The fourth phase-locked unit 104 is also used to lock the point frequency signal and output the second clock signal, the third clock signal and the fourth clock signal.

[0081] A frequency signal is dynamically generated by the third phase-locked unit 103 to provide input for the fourth phase-locked unit 104. As an example, the third phase-locked unit 103 is an integrated phase-locked loop (third phase-locked loop, not shown in the figure), which uses a signal of the first phase-locked unit 101 as input and locks, and dynamically outputs a point frequency signal as input of the fourth phase-locked unit 104. The variable reference frequency working mode is adopted to dynamically change and adjust the output frequency of the third phase-locked unit 103, so that the boundary spurious frequency generated by the fourth phase-locked unit 104 during fractional frequency division is farther away from the integral multiple frequency of the phase-locked frequency, so that it can be effectively suppressed by the phase-locked loop filter, thereby effectively suppressing spurious.

[0082] In the embodiment, the first phase lock unit 101 is used to lock the frequency of the synchronization reference signal to generate an ultra-low phase noise reference signal, which is divided into three paths to provide input for the subsequent second phase lock unit 102 , the third phase lock unit 103 and the fifth phase lock unit 105 .

[0083] The synchronization reference signal can be used to synchronize the frequencies of different electronic devices to avoid the generation of frequency differences; the present application realizes frequency synchronization through phase-locked technology; that is, an externally input synchronization reference signal can be used, or an internal synchronization reference signal can be used, and the selection of the use of the two is realized by a single-pole double-throw switch, and its state can be controlled by instructions issued by the host computer; and the internal 10MHz signal can be optionally equipped with a temperature-compensated crystal oscillator or a constant temperature crystal oscillator to obtain a stable low phase noise output. The use of a constant temperature crystal oscillator can obtain higher frequency stability and lower phase noise, but it occupies a larger volume and consumes more power; the use of a temperature-compensated crystal oscillator can obtain better frequency stability and lower phase noise, and it occupies a small volume and consumes less power. Through switch selection, users can flexibly switch the source of the synchronization reference signal to adapt to different application scenarios and needs.

[0084] The switching structure of the synchronization signal in the embodiment is as follows: Fig. 9As shown, the multi-channel phase-locked module 10 also includes a synchronization reference signal generating unit 106; the synchronization reference signal generating unit 106 includes a crystal oscillator, an external input channel and a switch, the output end of the crystal oscillator and the output end of the external input channel are connected to one end of the switch, the crystal oscillator is used to generate a local synchronization reference signal, the external input channel is used to input an external synchronization reference signal, and the other end of the switch outputs the selected synchronization reference signal.

[0085] In some embodiments, the first phase-locked unit 101 may be composed of a phase-locked loop and a power divider; the phase-locked loop uses a voltage-controlled crystal oscillator to ensure the phase noise level, and locks the synchronization signal through the phase-locked loop chip to eliminate the frequency difference; the power divider divides the phase-locked output into three paths and provides them to the subsequent circuits. The output frequency of the first phase-locked unit 101 can be fixed. In a specific implementation, a 100MHz low phase noise voltage-controlled crystal oscillator can be used, with 10MHz as the synchronization reference signal. After being locked by the first integrated phase-locked loop (not shown in the figure), power distribution is performed for output. The functional block diagram is as follows Fig.10 shown.

[0086] In some embodiments, the second phase lock unit 102 locks the signal frequency of the first phase lock unit 101 and outputs two frequency signals, one of which is provided to the digital-to-analog converter 202 as a clock input and the other is provided to the processor (such as FPGA201) as a reference frequency.

[0087] As an example, Fig.11 As shown, the second phase-locked unit 102 can be composed of an integrated phase-locked loop (a second integrated phase-locked loop, not shown in the figure) and a clock distributor. Using a signal (a first phase-locked signal) of the first phase-locked unit 101 as input, a low phase noise signal output with a maximum frequency of 1.25 GHz is generated after locking; the clock distributor has two outputs, one of which transmits a signal with a maximum frequency of 1.25 GHz (a second clock sub-signal) to the digital-to-analog converter 202 as a clock, and the other signal is provided to the FPGA 201 after frequency division (generating a first clock sub-signal).

[0088] High-speed playback refers to outputting the waveform data stored in the memory 204 in the form of an analog signal through the digital-to-analog converter 202. This output signal is also called a baseband signal. In order to obtain the best bandwidth; in some embodiments, the processor (FPGA201) and the digital-to-analog converter 202 (high-speed digital-to-analog converter 202) are connected by a low-voltage differential signal bus. The first clock sub-signal and the second clock sub-signal can synchronize the low-voltage differential signal (LVDS) signal frequency between the FPGA201 and the digital-to-analog converter 202 with the clock frequency of the digital-to-analog converter 202, ensuring the stable output of the digital-to-analog converter 202 and avoiding abnormalities caused by data discontinuity. The output frequency of the second phase-locked unit 102 varies according to the sample rate set for the actual high-speed playback.

[0089] In the embodiment, the DAC3482 of Texas Instruments can be used as a high-speed digital-to-analog converter 202. It is a dual-channel 16-bit converter that uses an LVDS bus and DDR transmission method. Generally, the LVDS bus switching frequency of FPGA201 is approximately 1.25GHz; the digital-to-analog converter 202 using the LVDS interface is usually a parallel data interface, so the maximum data transmission rate is 1.25GSPS. Using the DDR transmission method, the data of the two converters are transmitted by the same set of LVDS buses. At this time, the maximum data rate that the system can provide is 1.25G / 2=625MSPS, and the corresponding maximum modulation bandwidth is 625M×0.8=500MHz. Generally, the common 5GNR multi-carrier test uses two or three carrier tests. Taking three carriers as an example, the actual bandwidth used is 100MHz×3=300MHz; the maximum bandwidth specified by WiFi7 is 320MHz, so the modulation bandwidth of 500MHz is completely sufficient.

[0090] In order to achieve high-speed playback, the amount of data that FPGA201 needs to stably provide to the digital-to-analog converter 202 is 1.25G×16=20Gbit / S; this exceeds the rate that can be achieved by general external interfaces such as the USB interface 203 and the network port 207; therefore, the design uses DDR memory 204 to store the waveforms that need to be played back. Relying on the ultra-high data reading capability of the memory 204, FPGA201 reads the data from the memory 204 to the cache of FPGA201, and then passes it to the digital-to-analog converter 202 from the cache to achieve high-speed playback and obtain a baseband signal with a bandwidth of 500MHz and high linearity. Figure 6 shows the process.

[0091] The DAC3482 digital-to-analog converter 202 has a digital quadrature modulator correction function, which can directly adjust the difference between the two converters by writing registers to achieve correction of quadrature modulation and obtain optimal sideband suppression and local oscillator suppression.

[0092] The circuits related to the digital-to-analog converter 202 used in the embodiment are as follows: Figure 7 As shown; memory 204 circuit as Figure 8 shown.

[0093] In the embodiment, the fourth phase-locked unit 104 locks the signal frequency of the third phase-locked unit 103, and generates signals of corresponding frequencies (second clock signal, third clock signal and fourth clock signal) according to user settings, which can be used as the local oscillator signal of the orthogonal modulation unit 301, the local oscillator signal input of the divider 303 or the local oscillator signal input of the up-conversion unit 304.

[0094] As an example, the fourth phase-locked unit 104 is composed of an integrated phase-locked loop (a fourth integrated phase-locked loop, not shown in the figure), a series of filter banks and radio frequency switches. The fourth integrated phase-locked loop takes the output signal of the third phase-locked unit 103 as input and locks; the output of the fourth phase-locked unit 104 can be used as the local oscillator input of the orthogonal modulation unit 301, the input of the frequency divider 303, or the local oscillator input of the up-conversion unit 304.

[0095] The frequency coverage range of the fourth phase-locked unit 104 is generally wide. Some embodiments use a set of filters to effectively suppress harmonics after the phase-locked output, and realize multi-path selection output through a radio frequency switch. The block diagram is as follows: Fig.12 shown.

[0096] like Fig.12As shown, the fourth phase-locked unit 104 includes a fourth integrated phase-locked loop, a first one-to-many switch, a many-to-one switch and a second one-to-many switch connected in sequence, a plurality of radio frequency channels are formed between the first one-to-many switch and the many-to-one switch, and each radio frequency channel is provided with a filter; the fourth integrated phase-locked loop is connected to the output end of the third phase-locked unit 103; the one-to-many switch is respectively connected to the orthogonal modulation unit 301, the up-conversion unit 304 and the down-conversion unit 305, for outputting the second clock signal, the third clock signal and the fourth clock signal. The fourth phase-locked unit 104 can generate and distribute multiple clock signals at the same time through an integrated phase-locked loop (PLL) and subsequent switch design. This design improves the flexibility and availability of the clock signal, so that different modules (such as the orthogonal modulation unit 301, the frequency divider 303, and the up-conversion unit 304) can select and use appropriate clock signals as needed, and filters are set on multiple radio frequency channels, which helps to filter the clock signals passing through these channels to remove unnecessary frequency components or noise, maintain the purity and stability of the radio frequency signal, and thus improve the performance of the entire vector signal generator.

[0097] In some embodiments, the fifth phase-locked unit 105 locks the frequency of the third phase-locked signal output by the first phase-locked unit 101, and generates a fixed-frequency local oscillation signal (fifth clock signal) as the local oscillation input of the down-conversion unit 305. As an example, the fifth phase-locked unit 105 is an integrated phase-locked loop (fifth integrated phase-locked loop, not shown in the figure), which uses a signal (third phase-locked signal) of the first phase-locked unit 101 as input and locks; and outputs a fixed frequency signal (fifth clock signal) as the local oscillation input of the down-conversion unit 305.

[0098] The orthogonal modulation unit 301 modulates the baseband signal to the radio frequency. The baseband signal of the orthogonal modulation unit 301 comes from the digital-to-analog converter 202 . The local oscillator signal of the orthogonal modulation unit 301 may come from the fourth phase-locked unit 104 or the frequency divider 303 .

[0099] In a specific implementation, the orthogonal modulation unit 301 is an orthogonal modulator, which can specifically adopt a zero intermediate frequency modulation method, and fine-tune and correct by adjusting the amplitude, phase difference and DC offset difference between the outputs of the two digital-to-analog converters 202 to obtain the best sideband suppression and local oscillator suppression performance. When the output of the fourth phase-locked unit 104 is selected as the local oscillator, the frequency coverage within the frequency range of the fourth phase-locked unit 104 can be covered. The phase-locked loop device and the orthogonal modulator should be selected in a suitable combination to obtain the best characteristics. In some embodiments, the 0.4-6 GHz frequency band is selected as the frequency band of the orthogonal modulation output, and a frequency coverage of up to 6 GHz can be obtained.

[0100] In the embodiment, the power control unit 302 is used to adjust the power of the orthogonal modulation signal. As an example, the power control unit 302 includes two cascaded amplifiers and two variable attenuators. The typical gain of the amplifier is 20dB; the attenuator uses a voltage-controlled attenuator, and the power adjustment range of each attenuator is 25dB. The total range of the two attenuators cascaded is 50dB. By using the 14-bit digital-to-analog converter 202 output voltage and adjusting the voltage-controlled attenuator, extremely fine power steps can be achieved, such as Fig.13 shown.

[0101] For signals in higher frequency bands (such as 6GHz-8GHz), this application adopts up-conversion. The signal (first control signal) obtained by orthogonal modulation and power control is used as the input of the up-conversion unit 304, and the output signal (fourth clock signal) of the fourth phase-locked unit 104 is used as the local oscillator of the up-conversion. The output signal can be output as a second RF signal after passing through the first filtering unit 306. When up-conversion is used in the embodiment, interference signals such as local oscillator leakage, image, and harmonics will be generated. In the specific implementation, the up-conversion unit 304 is connected to the first filtering unit 306, and the first filtering unit 306 is used to suppress these interference signals. The first filtering unit 306 can be a group of bandpass filters, and its passband covers the frequency range of 6-8GHz.

[0102] In some embodiments, when the practical frequency range is higher than the frequency range of the fourth phase-locked unit 104 and the orthogonal modulation, up-conversion is used. In the embodiment, an up-conversion mixer is used to implement the up-conversion unit 304, and the output signal (first control signal) of the power control unit 302 is used as the input of the up-conversion unit 304, and one output signal (fourth clock signal) of the fourth phase-locked unit 104 is used as the local oscillator of the up-conversion. In the embodiment, the frequency divider 303 can use two-division, take the 4-5.33GHz frequency band of the fourth phase-locked unit 104, and obtain a 2-2.66GHz signal after frequency division as the local oscillator of the orthogonal modulation, and obtain a 2-2.66GHz orthogonal modulation signal as the input of the up-conversion mixer; take the direct output of the fourth phase-locked unit 104 as the local oscillator of the up-conversion mixer, and the frequency range of 6-8GHz can be covered.

[0103] For signals with lower frequencies (less than 0.4 GHz frequency range), the present application adopts down-conversion. The signal (second control signal) obtained by orthogonal modulation and power control is used as the input of the down-conversion unit 305, and the output signal (fifth clock signal) of the fifth phase-locked unit 105 is used as the local oscillator of the down-conversion; the output signal can be output as a third RF signal after passing through the second filtering unit 307.

[0104] In a specific embodiment, when the practical frequency range is lower than the frequency range of the fourth phase-locked unit 104 and the orthogonal modulation, down-conversion is used. The down-conversion unit 305 can be implemented using a down-conversion mixer, with the output signal (second control signal) of the power control unit 302 as the input of the down-conversion unit 305, and the fifth phase-locked unit 105 as the local oscillator of the down-conversion. Using a high local oscillator mode, the frequency range below 0.4 GHz is covered after frequency conversion, and then a low-pass filter (second filter unit 307) is used to filter out clutter. When using down-conversion, its output generally contains local oscillator leakage, harmonics and other signals; in order to obtain a purer output as much as possible, the second filter unit 307 can be used to improve the performance of local oscillator leakage and harmonics. The second filter unit 307 can be a fixed low-pass filter.

[0105] The broadband vector signal generator provided in the embodiment of the present application can achieve excellent performance of key indicators, and is particularly suitable for demanding testing needs such as multi-carrier 5G testing and WiFi7 testing. For the dedicated 5G of 6.0-7.125GHz, it can also provide an ACP characteristic of 60dBc (the higher the frequency, the lower the ACP).

[0106] The measured performance indicators of the broadband vector signal generator provided in the embodiment are as follows:

[0107] Frequency: Up to 8GHz

[0108] Bandwidth: up to 500MHz

[0109] Power step: 0.02dB

[0110] N78 band single carrier 5G NRTM31a EVM: 0.50%

[0111] N78 band 3 carrier 5G NR TM31a EVM: 0.65%

[0112] N78 band single carrier 5G NR TM31a ACP (ACPR / ACLR): 62dBc / 64dBc

[0113] N78 band 3 carrier 5G NR TM31a ACP (ACPR / ACLR): 53dBc / 55dBc

[0114] 7.1GHz band single carrier 5G NR TM31a ACP (ACPR / ACLR): 60dBc / 62dBc

[0115] Spurious: -80dBc

[0116] LO leakage: -70dBc

[0117] Image rejection: -70dBc

[0118] Harmonics: better than -35dBc;

[0119] Among them, ACPR (Adjacent Channel Power Ratio) is the adjacent channel power ratio; ACLR (Adjacent Channel Leakage Ratio) is the adjacent channel leakage ratio.

[0120] This broadband vector signal generator has outstanding cost performance and the excellent characteristics of broadband and high linearity.

[0121] The broadband vector signal generator provided by the present application is introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the concept of the present application and should not be understood as limiting the scope of protection of the present application.

Claims

1. A broadband vector signal generator, characterized in that: include: A multi-channel phase-locking module, used to phase-lock the synchronization reference signal to obtain a first clock signal, a second clock signal, a third clock signal, a fourth clock signal and a fifth clock signal; A baseband processing module, used for acquiring waveform data, and performing digital-to-analog conversion on the waveform data based on the first clock signal to obtain two baseband signals; A radio frequency processing module, including an orthogonal modulation unit, a power control unit, a frequency divider, an up-conversion unit, and a down-conversion unit; The frequency divider is used to divide the frequency of the third clock signal to obtain a divided frequency signal; The orthogonal modulation unit is used to use the second clock signal or the frequency-divided signal as a local oscillator signal for orthogonal modulation, and perform orthogonal modulation on the two baseband signals to obtain an orthogonal modulated signal; The power control unit is used to perform power control on the orthogonal modulation signal to obtain a first radio frequency signal, a first control signal and a second control signal; The up-conversion unit is used to use the fourth clock signal as an up-conversion local oscillator signal to up-convert the first control signal to obtain a second radio frequency signal; The down-conversion unit is used to use the fifth clock signal as a down-converted local oscillator signal to down-convert the second control signal to obtain a third radio frequency signal.

2. The broadband vector signal generator according to claim 1, characterized in that: The multi-channel phase locking module includes a first phase locking unit, a second phase locking unit, a fourth phase locking unit and a fifth phase locking unit; The first phase-locking unit is used to phase-lock the synchronization reference signal and then perform power distribution, and output a first phase-locking signal, a second phase-locking signal and a third phase-locking signal; The second phase locking unit is used to perform phase locking based on the first phase locking signal to obtain the first clock signal; The fourth phase locking unit is used to perform phase locking based on the second phase locking signal to obtain the second clock signal, the third clock signal and the fourth clock signal; The fifth phase locking unit is used to perform phase locking based on the third phase locking signal to obtain the fifth clock signal.

3. The broadband vector signal generator according to claim 2, characterized in that: The multi-channel phase-locking module also includes a third phase-locking unit; The third phase locking unit is used to phase lock the second phase locking signal to generate a point frequency signal, and send the point frequency signal to the fourth phase locking unit; The fourth phase locking unit is further used to lock the frequency of the dot frequency signal and output the second clock signal, the third clock signal and the fourth clock signal.

4. The broadband vector signal generator according to claim 3, characterized in that: The fourth phase-locked unit includes a fourth integrated phase-locked loop, a first one-to-many switch, a many-to-one switch, and a second one-to-many switch connected in sequence, wherein a plurality of radio frequency channels are formed between the first one-to-many switch and the many-to-one switch, and each of the radio frequency channels is provided with a filter; The fourth integrated phase-locked loop is connected to an output end of the third phase-locked unit; The one-to-many switches are respectively connected to the orthogonal modulation unit, the frequency divider and the up-conversion unit, and are used to output the second clock signal, the third clock signal and the fourth clock signal.

5. The broadband vector signal generator according to claim 2, characterized in that: The first clock signal includes a first clock sub-signal and a second clock sub-signal; The baseband processing module includes a processor and a digital-to-analog converter, and the processor and the digital-to-analog converter are connected by a low voltage differential signal bus; The first clock sub-signal is used as a clock reference signal of the processor; The second clock sub-signal is used as a clock reference signal of the digital-to-analog converter; The processor is used to transmit the waveform data to the digital-to-analog converter; The digital-to-analog converter is used to perform digital-to-analog conversion on the waveform data and output two baseband signals.

6. The broadband vector signal generator according to claim 5, characterized in that: The baseband processing module also includes a USB interface and an OR / network port, which are used to receive control instructions issued by the host computer and transmit the control instructions to the processor so that the processor performs corresponding operations to obtain operation results, and returns the operation results to the host computer.

7. The broadband vector signal generator according to claim 5, characterized in that: The second phase-locked unit includes a second integrated phase-locked loop and a clock distributor; The second integrated phase-locked loop is used to phase-lock the first phase-locked signal to generate a synchronization signal; The clock distributor is used to generate the first clock sub-signal based on the synchronization signal by frequency division, and to generate the second clock sub-signal based on the synchronization signal.

8. The broadband vector signal generator according to claim 1, characterized in that: The multi-channel phase-locked module also includes: A synchronization reference signal generating unit; The synchronization reference signal generating unit includes a crystal oscillator, an external input channel and a switch, the crystal oscillator and the external input channel are connected to one end of the switch, the crystal oscillator is used to generate a local synchronization reference signal, the external input channel is used to input an external synchronization reference signal, and the other end of the switch outputs a selected synchronization reference signal.

9. The broadband vector signal generator according to claim 1, characterized in that: The baseband processing module also includes: Trigger unit; When the trigger function is set to output mode, each time the waveform file being played back in a loop switches from the end to the beginning, a trigger signal is output through the trigger unit; when the trigger function is set to input mode, each time a trigger signal transmitted by the trigger unit is detected, the waveform file is played back once, wherein the waveform file stores the waveform data.

10. The broadband vector signal generator according to claim 1, characterized in that: The trigger mode of the trigger function is single trigger or continuous trigger.

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