Printed circuit board

Abstract

The invention provides a printed circuit board. The printed circuit board includes: a glass layer; a through hole penetrating the glass layer; the seed layer is arranged along the inner wall of the through hole; and a through via disposed on the seed layer and filling the through hole. The seed layer comprises a carbon-based conductive material.

Description

[0001] This application claims the benefit of priority from Korean Patent Application No. 10-2023-0147587 filed on October 31, 2023, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2023-0120274 filed on September 11, 2023, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein in their entirety by reference. Technical Field

[0002] The present disclosure relates to a printed circuit board. Background Art

[0003] Due to the recent progress of artificial intelligence (AI) technology, etc., multi-chip packages have been used, which include memory chips (such as high bandwidth memory (HBM) for processing exponentially growing data), processor chips (such as central processing units (CPUs), graphic processing units (GPUs)) and logic chips (such as application-specific integrated circuits (ASICs), field programmable gate arrays (FPGAs)), etc. Therefore, attempts to use glass materials are continuing. However, the problem with glass materials is that the adhesion of glass materials to metal materials is low, resulting in problems when using glass substrates. Summary of the invention

[0004] One aspect of the present disclosure is to provide a printed circuit board including a glass layer.

[0005] An aspect of the present disclosure is to provide a printed circuit board in which adhesion between a glass layer and a metal material can be ensured.

[0006] An aspect of the present disclosure is to provide a printed circuit board having improved reliability.

[0007] According to one aspect of the present disclosure, a printed circuit board includes: a glass layer; a through hole penetrating the glass layer; a seed layer disposed along an inner wall of the through hole; and a through via disposed on the seed layer and filling the through hole. The seed layer includes a carbon-based conductive material.

[0008] According to another aspect of the present disclosure, a printed circuit board includes: a glass layer; a through via penetrating the glass layer; and a seed layer disposed between the through via and the glass layer. The seed layer includes at least one of a conductive polymer material and a carbon-based conductive material, and an upper surface of the through via is substantially coplanar with an upper surface of the glass layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other aspects, features and advantages of the present disclosure will be more clearly understood through the following detailed description in conjunction with the accompanying drawings, in which: Figure 1 is a block diagram schematically illustrating an example of an electronic device system; Figure 2 is a perspective view schematically showing an example of an electronic device; Figure 3 is a cross-sectional view schematically showing an example of a printed circuit board; and Figures 4 to 10 are cross-sectional views schematically illustrating various embodiments of a glass layer for a printed circuit board and a method of manufacturing a glass layer for a printed circuit board. DETAILED DESCRIPTION

[0010] Hereinafter, the present disclosure will be described with reference to the accompanying drawings. For clearer description, the shapes and sizes of elements in the drawings may be exaggerated or reduced.

[0011] Electronic Devices Figure 1 is a block diagram schematically illustrating an example of an electronic device system.

[0012] Reference Figure 1 , the electronic device 1000 may house a mainboard 1010 therein. Chip-related components 1020, network-related components 1030, other components 1040, etc. may be physically or electrically connected to the mainboard 1010. These components may be connected to other electronic components to be described below through various signal lines 1090.

[0013] The chip-related components 1020 may include: memory chips, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory), etc.; application processor chips, such as central processing units (e.g., central processing units (CPUs)), graphics processors (e.g., graphics processing units (GPUs)), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; and logic chips, such as analog-to-digital converters (ADCs), application-specific integrated circuits (ASICs), etc. However, the chip-related components 1020 are not limited thereto, but may also include other types of chip-related components. In addition, the chip-related components 1020 may also be combined with each other. The chip-related components 1020 may be in the form of a package including the above-mentioned chips.

[0014] The network-related components 1030 may include components that are compatible with or operate according to protocols such as: Wireless Fidelity (Wi-Fi) (Institute of Electrical and Electronics Engineers (IEEE) 802.11 series, etc.), Worldwide Interoperability for Microwave Access (WiMAX) (IEEE 802.16 series, etc.), IEEE 802.20, Long Term Evolution (LTE), Evolution-Data Optimized (Ev-DO), High Speed ​​Packet Access + (HSPA+), High Speed ​​Downlink Packet Access + (HSDPA+), High Speed ​​Uplink Packet Access + (HSUPA+), Global System for Mobile Communications (GSM), Enhanced Data Rates for GSM Evolution (EDGE), Global Positioning System (GPS), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Enhanced Digital Cordless Telecommunications (DECT), Bluetooth, third generation mobile communication technology (3G) protocols, fourth generation mobile communication technology (4G) protocols, and fifth generation mobile communication technology (5G) protocols, as well as any other wireless protocols and wired protocols specified after the above protocols. However, the network-related component 1030 is not limited thereto, but may also include components compatible with or operating in accordance with various other wireless standards or protocols or wired standards or protocols. In addition, the network-related component 1030 may be combined with the chip-related component 1020 described above.

[0015] Other components 1040 may include high frequency inductors, ferrite inductors, power inductors, ferrite beads, low temperature co-fired ceramic (LTCC) components, electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCC), etc. However, other components 1040 are not limited thereto, but may also include passive devices in the form of chip components for various other purposes, etc. In addition, other components 1040 may also be combined with the above-mentioned chip-related components 1020 and / or network-related components 1030.

[0016] Depending on the type of the electronic device 1000, the electronic device 1000 may include other electronic components that are physically or electrically connected to the mainboard 1010 or that are not physically or electrically connected to the mainboard 1010. These other electronic components may include, for example, a camera 1050, an antenna 1060, a display 1070, a battery 1080, etc. However, these other electronic components are not limited thereto, and may also be an audio codec, a video codec, a power amplifier, a compass, an accelerometer, a gyroscope, a speaker, a mass storage unit (e.g., a hard disk drive), a compact disk (CD) drive, a digital versatile disk (DVD) drive, etc. In addition, depending on the type of the electronic device 1000, the electronic device 1000 may also include other electronic components for various purposes.

[0017] The electronic device 1000 may be a smart phone, a personal digital assistant (PDA), a digital video camera, a digital camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television, a video game console, a smart watch, an automobile component, etc. However, the electronic device 1000 is not limited thereto but may be any other electronic device capable of processing data.

[0018] Figure 2 is a schematic perspective view showing an example of an electronic device.

[0019] Reference Figure 2 , the electronic device may be, for example, a smart phone 1100. A mainboard 1110 is housed inside the smart phone 1100, and various components 1120 are physically or electrically connected to the mainboard 1110. In addition, other electronic components (such as a camera module 1130 and / or a speaker 1140) that are physically or electrically connected to the mainboard 1110 or that are not physically or electrically connected to the mainboard 1110 may be housed in the smart phone 1100. Some of the components 1120 may be the above-mentioned chip-related components, for example, a component package 1121, but are not limited thereto. The component package 1121 may be in the form of a printed circuit board on which an electronic component (including an active component and / or a passive component) is surface-mounted. Alternatively, the component package 1121 may be in the form of a printed circuit board in which an electronic component (including an active component and / or a passive component) is embedded. On the other hand, the electronic device need not be limited to the smart phone 1100, and may also be other electronic devices as described above.

[0020] Printed Circuit Board Figure 3 is a cross-sectional view schematically showing an example of a printed circuit board.

[0021] Reference Figure 3 According to some embodiments of the present disclosure, a printed circuit board may include: a glass layer 110; a through hole h penetrating the glass layer 110; a seed layer 120 formed on a surface of an inner wall of the through hole h; and a through via 130 disposed on the seed layer 120 and filling the through hole h.

[0022] The glass layer 110 may include glass as an amorphous solid. The glass may include, for example, pure silicon dioxide (about 100% SiO2), soda-lime glass, borosilicate glass, aluminum silicate glass, etc., but the present disclosure is not limited thereto, and optional glass materials such as fluorine glass, phosphate glass, chalcogenide glass, etc. may also be used as materials for the glass layer 110. In addition, other additives may be included to form glass with specific physical properties. These additives may include magnesium, sodium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, antimony, and carbonates (e.g., calcium carbonate (e.g., limestone) and sodium carbonate (e.g., soda)) and / or oxides of these and other elements. The glass layer 110 includes a material different from a material containing glass fibers (such as glass fabrics exemplified by glass cloth) (such as copper clad laminates (CCL), prepregs (PPG), etc.), and, for example, may be understood as flat glass, etc. The glass layer 110 may be a flat glass supported by a support member such as another core, etc.

[0023] The printed circuit board according to some examples includes the glass layer 110, and thus may basically have excellent flatness, and further, may be advantageous for warpage control through a low coefficient of thermal expansion (CTE) and the like. In detail, since the printed circuit board according to some examples may have the glass layer 110 as a core layer, it may be advantageous for warpage control even in an operation of stacking other insulating layers. In addition, even if other insulating layers are stacked on the glass layer 110 simultaneously or sequentially, flatness may be further improved, and thus, it may be more advantageous for forming a high-density fine circuit with a fine pitch. In addition, by adopting the glass layer 110, the number of layers of the printed circuit board may be reduced and the degree of freedom of design may be further improved through the characteristics of glass having variable dielectric properties (e.g., Dk (dielectric constant) of 2.5 to 11).

[0024] The through hole h formed in the glass layer may penetrate the glass layer 110. Since the through hole h may penetrate the glass layer 110, a wiring layer disposed on the upper surface of the glass layer 110 and a wiring layer disposed on the lower surface of the glass layer 110 may be connected. The through hole h may be formed by various methods such as laser processing, mechanical processing, chemical processing, etc., and the through hole h may also be formed by combining a plurality of processing methods instead of one processing method.

[0025] The through hole h may be formed so that the width of the upper surface and the width of the lower surface are respectively wider than the width of the center. For example, the through hole h may have a tapered shape to have the narrowest width at the center of the glass layer 110 in the thickness direction and the width of the through hole h may gradually widen from the narrowest width toward both the upper surface and the lower surface of the glass layer 110. For example, the through hole h may have an hourglass shape. However, the present disclosure is not necessarily limited thereto, and the through hole h may have a tapered shape so that the width at the bottom becomes narrower than the width at the top. In addition, the present disclosure is not limited thereto, and the through hole h may have a non-tapered cylindrical shape. The cross-sectional shape of the through hole h (e.g., the shape in a cross section perpendicular to the thickness direction) may be circular, but is not necessarily limited thereto, and may have various shapes such as elliptical and polygonal.

[0026] A printed circuit board according to some examples of the present disclosure may include a seed layer 120 formed along the inner wall of the through hole h. The seed layer 120 may be used as a seed for forming the through hole 130 and may be used as a plating lead-in for electroplating. The seed layer 120 may include a conductive material such as a carbon-based conductive material, a conductive polymer material, etc.

[0027] The carbon-based conductive material may refer to a carbon-based inorganic material, and may include, for example, a carbon black material, but the carbon-based conductive material is not necessarily limited thereto, and may include at least one material of graphite, graphene, carbon nanotubes (CNTs), and fullerenes, but is not necessarily limited thereto. In addition, any material containing a carbon-based inorganic material and having conductivity may be used without limitation. Carbon black (an example of a carbon-based conductive material) is one of the byproducts obtained by burning a carbon material, and may have conductivity. By adding other additives to such a carbon black material having conductivity, the conductivity may be further increased and the bonding strength of the carbon black material to the glass layer 110 may be increased. When the seed layer 120 includes a carbon-based conductive material, the seed layer 120 may be formed by coating the glass layer 110 with a coating solution containing the carbon-based conductive material. At this time, the seed layer 120 may be formed on the upper surface, the lower surface, and the side surface of the glass layer 110. Since an operation of removing a portion of the seed layer 120 may be further included, the seed layer 120 of the printed circuit board according to some examples may be formed only on the inner wall of the through hole h of the glass layer 110 , which will be described in detail later in the method of manufacturing the printed circuit board.

[0028] The conductive polymer material may be a conductive polymer. The conductive polymer may include a polymer composed of an organic material having conductivity. The conductive polymer may include, but is not necessarily limited to, at least one selected from the group consisting of, for example, poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS), polyaniline, polyindole, and polypyrrole. In addition, any organic material having conductivity may be used without limitation. When the seed layer 120 includes a conductive polymer, the seed layer 120 may be formed by coating.

[0029] In a printed circuit board according to some examples, the seed layer 120 may not include copper. If the seed layer 120 includes copper, the adhesion between the seed layer 120 and the glass layer 110 may be weak. In detail, because the adhesion between copper and the glass layer is weak, the phenomenon of the seed layer peeling off from the glass layer may occur when manufacturing the buildup layer, or the problem of copper being separated from the finished substrate may also occur. If the seed layer 120 is formed by a deposition method such as a sputtering method without using copper to ensure adhesion, it may take a lot of time and cost. On the other hand, the seed layer 120 in the printed circuit board according to some examples may include at least one of the carbon-based conductive material and the conductive polymer material as described above, and therefore, the seed layer 120 may be formed using a low-cost process while ensuring the adhesion between the seed layer 120 and the glass layer 110. In detail, a seed layer 120 used as a plated lead-in without containing a metal may be realized in a printed circuit board according to some examples. Since the seed layer 120 does not include metal, the problem of irregular plating due to loss or damage of the seed layer 120 caused by pre-treatment performed before electroplating may be prevented, which may be more conducive to ensuring adhesion of the seed layer 120 to the glass layer 110 .

[0030] The printed circuit board according to some examples includes a through via 130 disposed on the seed layer 120 and disposed to fill the through hole h. The through via 130 may have the same shape as the through hole h.

[0031] The through via 130 may include at least one metal selected from the group consisting of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and alloys thereof. According to some embodiments, the through via 130 may include copper (Cu), but is not limited thereto. Each wiring layer may perform various functions according to design, and for example, each wiring layer may include a signal via, a power via, a ground via, etc.

[0032] The through via 130 may be formed by performing plating using the seed layer 120 as a plating lead-in. The plating may be electroplating, and in the case of electroplating, the through via may be formed by electrolytic copper plating, but is not necessarily limited thereto. For example, after an electroless plating layer (e.g., a chemical copper plating layer) is formed on the seed layer 120, electroplating (e.g., electrolytic copper plating) may be performed. Figure 3 , the through via 130 is shown as a so-called filled via, for example, the through via 130 is formed by filling the through hole h of the glass layer 110 with a metal layer, but is not limited thereto. The through via 130 may be a conformal via disposed along the wall of the via hole, but is not limited thereto. Figure 3 , and the through via 130 may be formed by forming a thin plating layer on the inner wall of the through hole h, filling the through hole h with a paste, and then firing. At this time, the plug may include ink of an insulating material, but is not necessarily limited thereto.

[0033] The upper surface of the through via 130 may be substantially coplanar with the upper surface of the glass layer 110, and the lower surface of the through via 130 may be substantially coplanar with the lower surface of the glass layer 110. By including an operation of planarizing the glass layer 110 and the through via 130 after forming the through via 130 in the through hole h, the upper surface and the lower surface of the glass layer 110 may be substantially coplanar with the upper surface and the lower surface of the through via 130, respectively. The operation of planarizing the glass layer 110 and the through via 130 may be performed by a chemical mechanical polishing (CMP) process, but is not necessarily limited thereto, and any method for planarizing the glass layer 110, etc., such as polishing or grinding, may be used without limitation. Because the upper surface of the through via 130 may be polished together with the upper surface of the glass layer 110, the surface roughness of the upper surface of the glass layer 110 may be substantially the same as the surface roughness of the upper surface of the through via 130. Similarly, in the case of the lower surface of the through via 130 and the lower surface of the glass layer 110 , the surface roughness of the lower surface of the glass layer 110 may be substantially the same as that of the lower surface of the through via 130 , but the present disclosure is not necessarily limited thereto.

[0034] According to some embodiments of the present disclosure, in the process of planarizing the glass layer 110 and the through via 130, a portion of the seed layer 120 disposed on the upper surface of the glass layer 110 may be removed, and an electrically unnecessary portion may be opened to allow a function such as signal transmission of a board to be performed. Since the seed layer 120 may also be planarized together with the glass layer 110 and the through via 130, the upper surface of the seed layer 120 may also be substantially coplanar with the upper surface of the glass layer 110 and the upper surface of the through via 130, and the lower surface of the seed layer 120 may also be substantially coplanar with the lower surface of the glass layer 110 and the lower surface of the through via 130. In this case, the upper surface and the lower surface of the seed layer 120 may refer to surfaces exposed to the upper surface and the lower surface of the glass layer 110, respectively. For example, in a top view of the glass layer 110, the upper surface of the through via 130 is located within the glass layer 110, and the upper surface of the seed layer 120 may be located along the periphery of the through via 130. In the bottom view of the glass layer 110, the same shape may also be provided, that is, the lower surface of the through-hole 130 is located within the glass layer 110, and the lower surface of the seed layer 120 may be located along the periphery of the through-hole 130. As used herein, the term "substantially" means an amount that will be expected by a person skilled in the art, is small, insignificant, does not significantly affect the overall performance and allows variations compared to absolute or perfect conditions, dimensions, measurements, results, etc. When used for quantities, parameters or properties that can be expressed as numbers, "substantially" means within 10%.

[0035] The printed circuit board according to the example may further include a first insulating layer 111 and a second insulating layer 112 disposed on the glass layer 110, and may further include: a first wiring layer 121 disposed on the first insulating layer 111; a second wiring layer 122 disposed on the second insulating layer 112; a first via layer 131 penetrating at least a portion of the first insulating layer 111 to connect the first wiring layer 121 and the through via 130 to each other; and a second via layer 132 penetrating at least a portion of the second insulating layer 112 to connect the second wiring layer 122 and the first wiring layer 121 to each other.

[0036] The first insulating layer 111 and the second insulating layer 112 may each include an organic insulating material. The organic insulating material may include a thermosetting resin (such as an epoxy resin), a thermoplastic resin (such as polyimide), or a material prepared by impregnating a core material (such as glass fiber (for example, glass fabric with glass cloth as an example)) with an inorganic filler in a thermosetting resin or a thermoplastic resin. For example, the organic insulating material may include a non-photosensitive organic insulating material such as an Ajinomoto built-up film (ABF) or a prepreg (PPG), but is not limited thereto. In addition, other polymer materials may be used. In addition, the organic insulating material may include a photosensitive insulating material such as a photosensitive dielectric (PID). In addition, the organic insulating material may include an adhesive sheet such as a bonding sheet (BS).

[0037] The first insulating layer 111 and the second insulating layer 112 may include the same insulating material. Specifically, the first insulating layer 111 and the second insulating layer 112 may each include an Ajinomoto built-up film (ABF), but are not limited thereto. The first insulating layer 111 and the second insulating layer 112 may each include other organic insulating materials, but are not limited thereto. In addition, the first insulating layer 111 and the second insulating layer 112 may each include different materials.

[0038] On the other hand, Figure 3 , the first insulating layer 111 and the second insulating layer 112 are each shown as one insulating layer, but this is not necessarily limited. If necessary, the first insulating layer 111 and the second insulating layer 112 may each include a plurality of insulating layers. In addition, the thicknesses of the first insulating layer 111 and the second insulating layer 112 may be substantially different, and the second insulating layer 112 disposed above the glass layer 110 may be composed of a relatively thin insulating layer for fine circuits, etc., and may also further include additional configurations that can be used by those skilled in the art.

[0039] The first wiring layer 121 and the second wiring layer 122 may each include a metal. The metal may include at least one selected from the group consisting of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and alloys thereof. In detail, the metal may include copper (Cu), but the present disclosure is not limited thereto. The first wiring layer 121 and the second wiring layer 122 may independently perform various functions according to the design. For example, the first wiring layer 121 and the second wiring layer 122 may each include a signal pattern, a power pattern, a ground pattern, etc. These patterns may each have various forms such as lines, planes, and pads. The first wiring layer 121 and the second wiring layer 122 may each include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer), or may include a metal foil (e.g., a copper foil) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). Alternatively, the first wiring layer 121 and the second wiring layer 122 may each include a metal foil (e.g., a copper foil), an electroless plating layer (e.g., a chemical copper plating layer), and an electrolytic plating layer (e.g., an electrolytic copper plating layer). A sputtering layer may be included instead of the electroless plating layer (e.g., the chemical copper plating layer), and both may be included if necessary.

[0040] The first via layer 131 and the second via layer 132 may each include a metal. The metal may include at least one selected from the group consisting of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and alloys thereof. According to some embodiments of the present disclosure, the first via layer 131 and the second via layer 132 may each include copper (Cu), but are not limited thereto. The first via layer 131 and the second via layer 132 may each include a filled via that fills the via hole, but may also include a conformal via disposed along the wall of the via hole. The first via layer 131 and the second via layer 132 may perform various functions according to the design, for example, may include a ground via, a power via, a signal via, and the like. The first via layer 131 and the second via layer 132 may each include an electroless plating layer (e.g., a chemical copper plating layer) and an electrolytic plating layer (e.g., an electrolytic copper plating layer). A sputtering layer may be included instead of the electroless plating layer (e.g., the chemical copper plating layer), and both may be included if necessary.

[0041] On the other hand, Figure 3, the first wiring layer 121 and the second wiring layer 122 are each shown as one wiring layer, but this is not necessarily limited. Since the first insulating layer 111 and the second insulating layer 112 may each be composed of a plurality of insulating layers, the first wiring layer 121 and the second wiring layer 122 may each be composed of a plurality of wiring layers if necessary. In addition, the thickness and pitch of the first wiring layer 121 and the second wiring layer 122 may be substantially different, and the second wiring layer 122 disposed above the glass layer 110 may be composed of a redistribution layer as a thinner and finer pitch wiring layer for fine circuits. Additional configurations that can be used by those skilled in the art may also be included.

[0042] The printed circuit board according to some embodiments of the present disclosure may include a solder resist layer 150 located on the outermost portion of the printed circuit board. The solder resist layer 150 may be disposed on the second insulating layer 112. The solder resist layer 150 may include an insulating material and a liquid or film type solder resist, but is not limited thereto, and other types of insulating materials may be used. The solder resist layer 150 may have one or more openings, and each of the openings may expose at least a portion of the second wiring layer 122.

[0043] In addition, the printed circuit board according to some examples is not limited to Figure 3 , and may also include other configurations, or may omit some configurations in some cases. For example, the second insulating layer 112 may not be disposed under the glass layer 110, a plurality of first insulating layers 111 may be disposed, a cavity penetrating at least a portion of the first insulating layer 111 or the second insulating layer 112 may be further formed, or a cavity penetrating at least a portion of the glass layer 110 may be further formed, and an electronic component may be mounted in the cavity. Optionally, a surface treatment layer may be further formed on the wiring layer exposed through the opening of the solder resist layer 150, in detail, not limited to Figure 3 The configuration shown in , and may also include configurations that can be used in the art.

[0044] Figures 4 to 10 2 is a cross-sectional view schematically showing various embodiments of a glass layer for a printed circuit board and a method for manufacturing the glass layer for a printed circuit board. Figures 4 to 10 Only various embodiments of the glass layer 110 and the through-via 130 of the printed circuit board and a method of manufacturing the glass layer 110 and the through-via 130 of the printed circuit board are shown. After the glass layer 110 and the through-via 130 are formed to complete the core layer, other components such as the first insulating layer 111 and the like may be formed by a known method. Therefore, a detailed description thereof will be omitted. Below, various embodiments of the glass layer 110 and the through-via 130 and a method of manufacturing the glass layer 110 and the through-via 130 are described.

[0045] Figure 4A method of forming a through hole h in the glass layer 110 according to some embodiments of the present disclosure is shown. The through hole h may be formed by various methods such as laser processing, mechanical processing, chemical processing, etc., and the through hole h may be formed by combining multiple processing methods rather than one processing method. Optionally, the method is not limited thereto, and any known method of forming a through hole for a through glass via (TGV) that penetrates the glass layer may be used without limitation. The processing of the through hole h may be performed from the upper surface and the lower surface of the glass layer 110, respectively. Therefore, the through hole h may have a tapered shape so that the width at the center of the glass layer 110 in the thickness direction is the narrowest and the width at the upper and lower surfaces of the glass layer 110 is wider.

[0046] Subsequently, the seed layer 120 may be formed along the surface of the inner wall of the through hole h and the upper and lower surfaces of the glass layer 110. As described above in the printed circuit board according to some examples, the seed layer 120 may include a conductive material such as a carbon-based conductive material or a conductive polymer material, and thus, the seed layer 120 may be formed by coating the glass layer 110 with a coating solution containing the material of the seed layer 120 (e.g., the carbon-based conductive material or the conductive polymer material). Therefore, the method of forming the seed layer 120 may be performed at a lower cost than the cost of the process for forming a seed on the glass layer 110 of the related art, and the operation of forming the seed may be simplified and sufficient adhesion between the glass layer 110 and the seed layer 120 may be ensured. At this time, as the method of forming the seed layer 120 by the wet process proceeds, the seed layer 120 may be formed on the inner wall of the through hole h, the seed layer 120 may also be formed on the upper and lower surfaces of the glass layer 110, and the seed layer 120 may also be formed on the outer surface of the glass layer 110. In detail, the seed layer 120 may be formed on all surfaces of the glass layer 110 exposed outward. However, the present disclosure is not limited thereto, and in the case where the seed layer 120 is formed by spraying a coating solution containing a material of the seed layer 120, the seed layer 120 may be formed only in a region of the glass layer 110 adjacent to the inner wall of the through hole h by aligning with the inner wall of the through hole h and spraying, or the like.

[0047] After that, the through via 130 is formed. The through via 130 may be formed through a plating operation and a planarization operation.

[0048] In the plating operation for forming the through via 130, electroplating may be performed using the seed layer 120 as a plating lead-in. Since the seed layer 120 may be formed along the outer surface of the glass layer 110, the plating layer 130' for the through via 130 may also be formed along the entire surface of the glass layer 110. For example, in the plating operation, after the plating layer 130' fills the through hole h, overplating is performed, and the plating layer 130' may be placed on the upper and lower surfaces of the glass layer 110, and may also be disposed on the outer side surface of the glass layer 110.

[0049] Thereafter, an operation may be performed to complete the through-via 130 by removing at least a portion of the plating layer 130' and planarizing the glass layer 110 and the through-via 130. The operation of removing at least a portion of the plating layer 130' may be performed by a chemical mechanical polishing (CMP) process, but is not necessarily limited thereto, and any method for planarizing the glass layer 110 (such as polishing or grinding) may be used without limitation. In addition, before planarizing the glass layer 110 and the through-via 130, an etching process for removing at least a portion of the plating layer 130' may also be included. In the operation of planarizing the glass layer 110 and the through-via 130, a portion of the seed layer 120 may be removed, and the seed layer 120 disposed on the upper and lower surfaces and the outer side surface of the glass layer 110 may be removed to prevent a short circuit caused by a plated lead-in, thereby serving as a core layer of a printed circuit board. In this case, the upper surface of the glass layer 110, the upper surface of the through-via 130, and the upper surface of the seed layer 120 may provide a structure in which they are substantially coplanar with each other. Since the seed layer 120 may include a conductive material such as a carbon-based conductive material or a conductive polymer material, the adhesive force between the glass layer 110 and the seed layer 120 may be increased. In this case, in the case where patterning is performed on the glass layer 110, it may be difficult to selectively remove only an unnecessary portion of the seed layer 120. Therefore, in this case, the through-hole 130 may be completed by removing the seed layer 120 in batches while removing the plating layer 130' disposed on the upper and lower surfaces of the glass layer 110 through a chemical mechanical polishing process. However, the present disclosure is not necessarily limited thereto, and a method of patterning the plating layer 130' or a method of patterning using a plating resist in a plating operation may be used, and patterning may also be performed on the glass layer 110 by removing a portion of the seed layer 120.

[0050] After completing the through via 130 in the glass layer 110 , operations for forming other components of the printed circuit board such as the first insulating layer 111 may be performed, which are the same as those described above in the printed circuit board according to the example, and thus their descriptions are omitted.

[0051] Reference Figure 5, when the through hole h is formed in the glass layer 110, a groove t that penetrates a portion of the glass layer 110 may be formed. The method of forming the groove t in the glass layer 110 may be similar to the method of forming the through hole h in the glass layer 110, and is not limited thereto, and a known groove forming method may be used. The groove t does not completely penetrate the glass layer 110, and may penetrate only a portion of the glass layer 110. The groove t may have a bottom surface that may be a portion of the glass layer 110, and may have a tapered shape such that the width of the bottom surface of the groove t is narrower than the width of the top surface. However, the groove t is not limited thereto, and may have a shape that is not formed as a tapered column. In Figure 5 , the depth of the trench t is shown as half the depth of the through via 130, but the present disclosure is not limited thereto. The depth of the trench t may be less than half the depth of the through via 130. In this way, the shape of the trench t is not limited, and it may be sufficient if the trench t consists of an empty space for realizing a fill pattern in the glass layer 110.

[0052] Next, after forming the groove t, a seed layer 120 may be further formed on the inner wall and bottom surface of the groove t. In a subsequent plating operation, a plating layer 130' may be formed to fill the groove t. By removing at least a portion of the plating layer 130', a filling pattern 130-1 filling the groove t may be formed. The filling pattern 130-1 may be formed in the same manner as the through-hole 130 and may include the same metal. The filling pattern 130-1 may have various shapes and perform various functions. The description of the shape and function of the wiring layer may be applied to the shape and function of the filling pattern 130-1. The filling pattern 130-1 may be embedded so that the remaining surface except the upper surface is covered by the glass layer 110, and the seed layer 120 may be disposed between the filling pattern 130-1 and the glass layer 110. If necessary, a first via layer 131 may be formed on the filling pattern 130-1 and connected to the first wiring layer 121. The filling pattern 130 - 1 may be connected to the first wiring layer 121 in the same manner as the through via 130 may be connected to the first wiring layer 121 .

[0053] The operations of forming the seed layer 120 and completing the through via 130 after plating are the same as described above except for the configuration of forming the trench t in the operation of forming the through via h, and thus redundant descriptions thereof will be omitted.

[0054] Reference Figure 6, the through hole h formed in the glass layer 110 may have a tapered shape so that the width of the lower surface of the through hole h is narrower than the width of the upper surface of the through hole h. This may be the result of processing the through hole h from the upper surface of the glass layer 110 instead of processing the through hole h from both the upper and lower surfaces of the glass layer 110. However, the present disclosure is not limited thereto, and the through hole h may have a non-tapered cylindrical shape. As described above in the printed circuit board as an example, the shape of the through hole 130 may be determined according to the shape of the through hole h.

[0055] Except for the shape of the through hole h, the operation of forming the seed layer 120 and the operation of completing the through via 130 after plating are the same as described above, and thus redundant descriptions thereof will be omitted.

[0056] Reference Figure 7 , the through hole h formed in the glass layer 110 may not completely penetrate the glass layer 110. The through hole h may penetrate only a portion of the glass layer 110 from the upper surface of the glass layer 110 to the lower surface of the glass layer 110. For example, the through hole h may include a bottom surface that is a portion of the glass layer 110. After the through hole h is formed, the seed layer 120 may be disposed on the inner wall of the through hole h and may also be disposed on the bottom surface of the through hole h. After the plating layer 130' is formed, a portion of the glass layer 110 and a portion of the plating layer 130' may be removed by removing the lower portion of the glass layer 110, and the lower surface of the through hole 130 may be exposed to the lower surface of the glass layer 110. By removing the lower portion of the glass layer 110, a structure in which the lower surface of the through hole 130 is exposed to the outside may be provided.

[0057] The operations of forming the seed layer 120 and completing the through via 130 after plating are the same as described above except for the shape of the through via 130 and the method of manufacturing the through via 130 , and thus repeated description thereof will be omitted.

[0058] Reference Figure 8 After forming the through hole h in the glass layer 110, the adhesive layer 140 may be formed along the inner wall of the through hole h. After forming the adhesive layer 140, the seed layer 120 may be disposed on the adhesive layer 140. For example, the adhesive layer 140 is disposed on the inner wall of the through hole h and may be disposed between the inner wall of the through hole h and the seed layer 120.

[0059] The adhesive layer 140 may be an organic film containing a silane coupling agent, but is not necessarily limited thereto, and any adhesive material available in the art may be used without limitation. The silane coupling agent may include at least one type selected from silanes such as acrylic silanes, epoxy silanes, amino silanes, imidazole silanes, and mercapto silanes, but the present disclosure is not limited thereto. The adhesive layer 140 is located between the glass layer 110 and the seed layer 120, and may increase the adhesion between the glass layer 110 and the seed layer 120, which may provide an effect of increasing the adhesion between the through-hole 130 and the glass layer 110. Any known adhesive layer forming method may be used without limitation to form the adhesive layer 140. In the operation of forming the adhesive layer 140, the adhesive layer 140 may be formed on the upper and lower surfaces of the glass layer 110, and may also be formed on the outer surface of the glass layer 110.

[0060] Thereafter, an operation of forming the seed layer 120 , an operation of performing plating, and an operation of planarizing the glass layer 110 are the same as described above, and thus a repeated description thereof will be omitted.

[0061] Reference Fig. 9 After forming the seed layer 120 on the inner wall of the through hole h of the glass layer 110, the first metal layer 160 may be formed. The first metal layer 160 may be disposed on the seed layer 120 and along the shape of the inner wall of the through hole h. For example, the first metal layer 160 may be disposed between the through hole 130 and the seed layer 120.

[0062] The first metal layer 160 may include a metal, and an example of the metal may include at least one selected from the group consisting of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and alloys thereof, and in detail, may include copper (Cu), but is not limited thereto. The first metal layer 160 may include the same metal material as the metal material included in the through via 130. The first metal layer 160 may be formed by electroless plating, but is not necessarily limited thereto, and may be formed by a sputtering method. The first metal layer 160 may be a single metal layer, but is not limited thereto, and may include a plurality of metal layers. Since the first metal layer 160 may be disposed on the seed layer 120, the adhesive force between the first metal layer 160 and the seed layer 120 may be higher than the adhesive force when the first metal layer 160 is directly disposed on the glass layer 110. This is because the adhesive force between the seed layer 120 and the first metal layer 160 is greater than the adhesive force between the first metal layer 160 and the glass layer 110. First metal layer 160 may include an electroless plating layer and thus may be disposed along an outer surface of glass layer 110 on seed layer 120 and assists seed layer 120 serving as a plating lead-in to more effectively perform the function of the plating lead-in.

[0063] Thereafter, operations of performing plating and planarizing the glass layer 110 are the same as described above, and thus repeated descriptions thereof will be omitted.

[0064] Reference Fig.10 , after forming the seed layer 120 along the glass layer 110, an operation of forming a plating resist R and patterning the plating resist R may be included. The plating resist R performs a function of preventing plating growth during electroplating, and a known plating resist may be used.

[0065] When plating is performed after forming the plating resist R, electrolytic plating may be performed only on the region where the plating resist R is not formed, and a pattern layer 170 disposed above and below the glass layer 110 may be further formed together with the through via 130. The pattern layer 170 may be formed on the upper and lower surfaces of the through via 130, and may also be formed on the upper and lower surfaces of the glass layer 110. The seed layer 120 may be disposed between the pattern layer 170 and the glass layer 110. Since the pattern layer 170 is formed together with the through via 130 in the operation of forming the through via 130, the pattern layer 170 and the through via 130 may include substantially the same material (e.g., the same metal), and since the pattern layer 170 and the through via 130 may be integrally formed, a boundary between the pattern layer 170 and the through via 130 may not be clear.

[0066] After forming the pattern layer 170 , the plating resist R may be removed. The operation of removing the plating resist R may be performed using a method well known in the art.

[0067] After removing the plating resist R, a portion of the seed layer 120 may be removed. At this time, the seed layer 120 in the area where the pattern layer 170 is not formed is removed to open the space between adjacent patterns to serve as a circuit pattern. This may be the result of introducing a method of selectively removing a portion of the seed layer 120 rather than removing the entire seed layer 120 disposed on the glass layer 110. The method of selectively removing a portion of the seed layer 120 may be performed in the following manner: only a portion of the seed layer 120 is processed through a mask, but the present disclosure is not limited thereto. Since the seed layer 120 does not contain metal, the through-hole 130 and the pattern layer 170 may be less damaged during the operation of removing the seed layer 120, and only the seed layer 120 of the target area may be effectively removed.

[0068] On the other hand, the configuration other than the pattern layer 170 formed by the plating resist R is the same as described above, and thus repeated description thereof will be omitted.

[0069] On the other hand, Figures 4 to 10, various embodiments of the glass layer 110 and the through via 130 and the method of forming the glass layer 110 and the through via 130 are described, but the corresponding embodiments are of course not limited to one embodiment. For example, the adhesive layer 140 is included and the first metal layer 160 may be further provided, and various configurations such as the pattern layer 170, the filling pattern 130-1, etc. may be realized independently of each other in one glass layer 110.

[0070] As described above, a printed circuit board including a glass layer may be provided.

[0071] A printed circuit board can be provided in which adhesion between a glass layer and a metal material can be ensured.

[0072] A printed circuit board with improved reliability can be provided.

[0073] In the present disclosure, the expression "covering" may include not only the case of covering the whole but also the case of covering a part, and may also include the case of indirect covering as well as direct covering. In addition, the expression "filling" may include not only the case of completely filling but also the case of at least partially filling, and may also include substantially filling, for example, may include the case of having some gaps or pores.

[0074] In the present disclosure, the determination may actually include process errors and positional deviations occurring during the manufacturing process, errors during measurement, etc. For example, "substantially vertical" may include not only completely vertical but also substantially vertical. Furthermore, "substantially coplanar" may include not only completely on the same plane but also substantially on the same plane.

[0075] In the present disclosure, the same insulating material may not only refer to the same insulating material, but also refer to insulating materials including the same type. Therefore, the composition of the insulating materials is basically the same, but their specific composition ratios may be slightly different.

[0076] In the present disclosure, the shape on the cross section may refer to the cross-sectional shape when the object is cut vertically, or the shape when the object is viewed from a side view. In addition, the shape on the plane may refer to the shape when the object is cut horizontally, or the plane shape when the object is viewed from a top view or a bottom view.

[0077] In the present disclosure, for convenience, "lower side", "lower part", "bottom", "lower surface", etc. are used to indicate the downward direction based on the cross section of the drawings. "Upper side", "upper part", "upper surface", "top", etc. are used to indicate the opposite direction. However, this direction is defined for the convenience of explanation, and of course, the scope of the patent claims is not particularly limited by the description of this direction. The concept of top / bottom can be changed at any time.

[0078] In the present disclosure, the meaning of connection is a concept including not only direct connection but also indirect connection through an adhesive layer or the like. In addition, the meaning of electrical connection is a concept including both the case of physical connection and the case of no physical connection. In addition, expressions such as "first", "second", etc. are used to distinguish one component from another component, and do not limit the order and / or importance of components, etc. In some cases, a first component may be named a second component, and similarly, a second component may be named a first component without departing from the scope of the rights.

[0079] The expression "example" used in this disclosure does not mean the same example, but is provided for emphasizing and explaining different unique features. However, the examples presented above do not exclude implementation in combination with features of other examples. For example, even if the content described in an example is not described in another example, it can be understood as an explanation related to the other example unless there is an opposite or contradictory explanation in the other example.

[0080] The terms used in the present disclosure are only used to describe examples and are not intended to limit the present disclosure.At this time, unless the context clearly indicates otherwise, a singular expression includes a plural expression.

[0081] While example embodiments have been shown and described above, it will be readily apparent to those skilled in the art that modifications and variations may be made without departing from the scope of the present disclosure as defined by the appended claims.

Claims

1. A printed circuit board, comprising: Glass layer; A through hole penetrating the glass layer; A seed layer is disposed on the surface of the inner wall of the through hole; as well as a through hole, disposed on the seed layer and filling the through hole, Wherein, the seed layer includes a carbon-based conductive material.

2. The printed circuit board according to claim 1, wherein: The seed layer includes at least one material selected from the group consisting of carbon black, graphite, graphene, carbon nanotubes, and fullerene.

3. The printed circuit board according to claim 1, wherein: The through hole has a tapered shape to have a narrowest width at a central portion of the glass layer in a thickness direction, and a width of the through hole gradually increases from the narrowest width toward both upper and lower surfaces of the glass layer.

4. The printed circuit board according to claim 1, wherein: The through hole has a tapered shape such that a width of the through hole gradually increases from a lower surface toward an upper surface of the glass layer.

5. The printed circuit board according to claim 1, wherein An upper surface of the through via is substantially coplanar with an upper surface of the glass layer.

6. The printed circuit board according to claim 5, wherein: A lower surface of the through via is substantially coplanar with a lower surface of the glass layer.

7. The printed circuit board according to claim 1, wherein: The upper and lower surfaces of the seed layer are substantially coplanar with the upper and lower surfaces of the glass layer, respectively. 8 . The printed circuit board according to claim 1 , further comprising an adhesive layer disposed between the inner wall of the through hole and the seed layer.

9. The printed circuit board according to claim 8, wherein: The adhesive layer includes a silane coupling agent. 10 . The printed circuit board of claim 1 , further comprising a first metal layer interposed between the seed layer and the through via.

11. The printed circuit board according to claim 10, wherein: The first metal layer includes the same metal material as a metal material included in the through via.

12. The printed circuit board according to claim 1, further comprising: a groove penetrating a portion of the glass layer; as well as A filling pattern is embedded in the glass layer and fills the groove.

13. The printed circuit board according to claim 12, wherein: The seed layer is disposed on the bottom surface and the surface of the inner wall of the groove.

14. The printed circuit board according to claim 1, further comprising a pattern layer disposed on the through via and extending to at least a portion of an upper surface of the glass layer, in, The seed layer extends onto at least a portion of the upper surface of the glass layer.

15. The printed circuit board according to claim 1, further comprising: A first insulating layer, disposed on the glass layer; as well as The first wiring layer is arranged on the first insulating layer.

16. A printed circuit board, comprising: Glass layer; A through hole penetrates the glass layer; as well as a seed layer disposed between the through via and the glass layer, wherein the seed layer comprises at least one of a conductive polymer material and a carbon-based conductive material, and An upper surface of the through via is substantially coplanar with an upper surface of the glass layer. 17 . The printed circuit board of claim 16 , further comprising an adhesive layer disposed between the glass layer and the seed layer. 18 . The printed circuit board of claim 16 , further comprising a first metal layer interposed between the seed layer and the through via.

19. The printed circuit board according to claim 16, further comprising: A first insulating layer, disposed on the glass layer; as well as The first wiring layer is arranged on the first insulating layer.

Images