Semiconductor structure and manufacturing method thereof

Abstract

The invention relates to a semiconductor structure and a manufacturing method thereof, and the manufacturing method comprises the following steps: providing an initial structure which comprises a plurality of first semiconductor columns; a plurality of second semiconductor columns are formed, the second semiconductor columns are arranged in multiple columns in the first direction, the second semiconductor columns are connected with the first semiconductor columns, and each second semiconductor column comprises a first area, a second area and a third area which are sequentially arranged in the direction away from the first semiconductor column; word lines are formed, and the word lines extend in the first direction and wrap the side walls of the second areas of the column of second semiconductor columns arranged in the first direction; a sacrificial layer is formed, the sacrificial layer extends between the adjacent word lines in the first direction, and at least part of space between the adjacent word lines is filled with the sacrificial layer; forming a top insulating layer to cover the sacrificial layer and fill the unfilled space between the two adjacent columns of second semiconductor columns; and removing the sacrificial layer, and forming an air layer at the position where the sacrificial layer is removed so as to reduce parasitic capacitance between adjacent word lines.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] With the continuous development of the semiconductor integrated circuit industry, the development of semiconductor integrated circuit miniaturization requires the corresponding integrated circuit to have a higher integration density and a smaller feature size, that is, it is required to set as many devices as possible in a smaller integrated circuit area to obtain higher performance. However, the reduction in the distance between devices will increase the parasitic capacitance between devices, reduce device performance, and reduce the operating speed of the semiconductor structure. Summary of the invention

[0003] Based on this, it is necessary to provide a semiconductor structure and a manufacturing method thereof to address the problem in the prior art that the parasitic capacitance between devices increases due to the reduction in distance.

[0004] In order to achieve the above object, in a first aspect, the present invention provides a method for manufacturing a semiconductor structure, comprising the following steps:

[0005] Providing an initial structure, the initial structure comprising a plurality of first semiconductor pillars, wherein the plurality of first semiconductor pillars are arranged in a plurality of columns along a first direction;

[0006] forming a plurality of second semiconductor pillars, the plurality of second semiconductor pillars are arranged in a plurality of rows along the first direction, each second semiconductor pillar is correspondingly disposed on each first semiconductor pillar and connected to the first semiconductor pillar, and the second semiconductor pillar comprises a first region, a second region and a third region sequentially disposed in a direction away from the first semiconductor pillar;

[0007] forming a word line, wherein the word line extends along the first direction, and the word line covers the sidewalls of the second regions of a column of the second semiconductor pillars arranged along the first direction;

[0008] forming a sacrificial layer, wherein the sacrificial layer extends between adjacent word lines along the first direction, and the sacrificial layer at least fills a portion of the space between adjacent word lines;

[0009] forming a top insulating layer, wherein the top insulating layer covers the top surface of the sacrificial layer and fills the unfilled space between two adjacent columns of the second semiconductor pillars arranged along the first direction;

[0010] The sacrificial layer is removed, and an air layer is formed at a position where the sacrificial layer is removed.

[0011] In one embodiment, the manufacturing method further includes:

[0012] A work function layer is formed, wherein the work function layer covers the side wall of the second region of the second semiconductor column, and the word line and the side wall of the second region are connected through the work function layer.

[0013] In one embodiment, the manufacturing method further includes:

[0014] An insulating sidewall is formed, the insulating sidewall covering the sidewall of the third region of the second semiconductor column.

[0015] In one embodiment, the manufacturing method further includes:

[0016] An insulating dielectric layer is formed, the insulating dielectric layer covers the top surface of the initial structure and the sidewalls of the first region of the second semiconductor column, and the word line and the initial structure are separated by the insulating dielectric layer.

[0017] In one embodiment, forming a plurality of second semiconductor pillars includes:

[0018] forming an initial insulating dielectric layer, wherein the initial insulating dielectric layer covers a top surface of the initial structure;

[0019] Etching the initial insulating dielectric layer to form a plurality of first through holes corresponding to the first semiconductor pillars in the initial insulating dielectric layer, wherein each of the first through holes exposes at least a portion of a top surface of the corresponding first semiconductor pillar;

[0020] The second semiconductor pillars are formed in each of the first through holes.

[0021] In one embodiment, after forming a plurality of second semiconductor pillars, the method further includes the following steps:

[0022] A third semiconductor layer is formed, wherein the third semiconductor layer covers a top surface of the second semiconductor column, and a projection of the second semiconductor column on the initial structure falls within a projection of the third semiconductor layer on the initial structure.

[0023] In one embodiment, after forming the third semiconductor layer, the method includes:

[0024] Using the third semiconductor layer as a mask, the initial insulating dielectric layer is etched to remove a portion of the initial insulating dielectric layer around the third region of the second semiconductor column, and the sidewall of the third region is covered by the initial insulating dielectric layer retained by the etching;

[0025] forming a first insulating layer, wherein the first insulating layer covers the surface of the initial insulating dielectric layer retained by etching and the top surface of the third semiconductor layer;

[0026] The first insulating layer is etched to remove the first insulating layer located on the top surface of the third semiconductor layer and the first insulating layer located on the top surface of the initial insulating dielectric layer, the first insulating layer covering the side wall of the third region is etched and retained, and the initial insulating dielectric layer and the first insulating layer covering the side wall of the third region together form an insulating side wall.

[0027] In one embodiment, after forming the insulating sidewall, the method includes:

[0028] forming a first dielectric layer, wherein the first dielectric layer covers the top surface of the initial insulating dielectric layer, the surface of the insulating sidewall and fills the space between the third regions;

[0029] Etching and removing a portion of the first dielectric layer and a portion of the initial insulating dielectric layer to form a first trench, wherein the first trench extends between two adjacent columns of the second semiconductor pillars along the first direction, and the first trench exposes a portion of the surface of the insulating sidewall;

[0030] A second dielectric layer is formed in the first trench, the second dielectric layer extends along the first direction, the second dielectric layer and the second semiconductor pillars are alternately arranged along a second direction perpendicular to the first direction, and the top surface of the second dielectric layer is higher than the top surface of the third semiconductor layer.

[0031] In one embodiment, after forming the second dielectric layer in the first trench, the method further includes:

[0032] The first dielectric layer and a portion of the initial insulating dielectric layer are etched away to expose the sidewalls of the second region of the second semiconductor column. The initial insulating dielectric layer below the second dielectric layer is retained to form an insulating dielectric layer, and the insulating dielectric layer covers the sidewalls of the first region of the second semiconductor column.

[0033] In one embodiment, after forming the insulating dielectric layer, the method further comprises:

[0034] forming a gate dielectric layer, wherein the gate dielectric layer covers the sidewalls of the second region;

[0035] forming a work function material layer, wherein the work function material layer covers a surface of the gate dielectric layer;

[0036] The work function material layer is etched using the insulating sidewall as a mask, and the work function material layer shielded by the insulating sidewall is etched away to form a work function layer.

[0037] In one embodiment, forming a word line includes:

[0038] forming a conductive layer, the conductive layer covering the work function layer and filling unfilled spaces between the second semiconductor pillars;

[0039] The conductive layer is etched to remove the conductive layer filled between the third regions, and the conductive layer is divided into the word lines extending along the first direction.

[0040] In one embodiment, forming a sacrificial layer includes:

[0041] removing the second dielectric layer to expose the first trench;

[0042] forming a sacrificial material layer, wherein the sacrificial material layer fills the first trench;

[0043] The sacrificial material layer is etched until a top surface is lower than a top surface of the word line, so as to form the sacrificial layer in the first trench.

[0044] In one embodiment, before removing the second dielectric layer, the method further comprises:

[0045] A second insulating layer is formed, the second insulating layer filling unfilled spaces between the third regions of the second semiconductor pillars.

[0046] In one embodiment, the manufacturing method further includes:

[0047] A capacitor contact portion is formed on the third semiconductor layer, wherein the capacitor contact portion covers at least a portion of a surface of the third semiconductor layer.

[0048] In one embodiment, forming a capacitor contact includes:

[0049] forming a metal material layer on the top surface of the third semiconductor layer;

[0050] thermally treating the third semiconductor layer and the metal material layer;

[0051] The metal material layer after the heat treatment is removed, and the capacitor contact portion is formed on the third semiconductor layer.

[0052] In a second aspect, the present invention provides a semiconductor structure, comprising:

[0053] An initial structure, the initial structure comprising a plurality of first semiconductor pillars, wherein the plurality of first semiconductor pillars are arranged in a plurality of rows along a first direction;

[0054] A plurality of second semiconductor pillars, wherein the plurality of second semiconductor pillars are arranged in a plurality of rows along the first direction, each second semiconductor pillar is correspondingly disposed on each first semiconductor pillar and connected to the first semiconductor pillar, and the second semiconductor pillar comprises a first region, a second region and a third region sequentially disposed in a direction away from the first semiconductor pillar;

[0055] A word line extending along the first direction, the word line covering a side wall of the second region of a column of the second semiconductor pillars arranged along the first direction;

[0056] an air layer, the air layer extending along the first direction, the air layer being arranged between adjacent word lines, and a top surface of the air layer being lower than a top surface of the word line;

[0057] A top insulating layer covers top surfaces of the word lines and fills spaces between the word lines above the air layer.

[0058] In one embodiment, the semiconductor structure further comprises:

[0059] A protection layer covers the sidewall of the word line, and the word line and the air layer are separated by the protection layer.

[0060] In one embodiment, the semiconductor structure further comprises:

[0061] A work function layer covers a side wall of the second region of the second semiconductor column, and the word line and the side wall of the second region are connected through the work function layer.

[0062] In one embodiment, the semiconductor structure further comprises:

[0063] an insulating dielectric layer, the insulating dielectric layer being located below the air layer, the insulating dielectric layer covering a top surface of the initial structure and a side wall of the first region of the second semiconductor column, the word line and the initial structure being separated by the insulating dielectric layer;

[0064] An insulating sidewall covers a sidewall of the third region of the second semiconductor column.

[0065] In one embodiment, the semiconductor structure further comprises:

[0066] A third semiconductor layer covers a top surface of the second semiconductor column, and a projection of the second semiconductor column on the initial structure falls within a projection of the third semiconductor layer on the initial structure.

[0067] The semiconductor structure and the manufacturing method thereof of the present invention form an air layer between adjacent word lines, and the air dielectric constant is relatively low. Thus, the existence of the air layer can reduce the parasitic capacitance between adjacent word lines, avoid the parasitic capacitance between the word lines causing the resistance and capacitance response delay, and help to improve the response speed of the semiconductor structure and improve the electrical performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0069] Figure 1 FIG. 4 is a flow chart of a method for manufacturing a semiconductor structure provided in one embodiment.

[0070] Figure 2 A schematic diagram of an initial structure provided in an embodiment.

[0071] Figure 3 FIG. 4 is a projection diagram of a first semiconductor column formed on a substrate in an embodiment.

[0072] Figure 4 It is a cross-sectional view of the initial structure along line AA in one embodiment.

[0073] Figure 5 FIG. 1 is a schematic diagram of an embodiment after an initial insulating dielectric layer is formed.

[0074] Figure 6 FIG. 4 is a schematic diagram after forming a first through hole in an embodiment.

[0075] Figure 7 It is a cross-sectional view along line AA after forming the first through hole in one embodiment.

[0076] Figure 8 FIG. 4 is a schematic diagram after forming a second semiconductor column in one embodiment.

[0077] Fig. 9 FIG. 4 is a schematic diagram after forming a third semiconductor layer in one embodiment.

[0078] Fig.10 It is a cross-sectional view along line AA after forming the third semiconductor layer in one embodiment.

[0079] Fig.11 FIG. 4 is a schematic diagram of an embodiment after etching the third oxide layer.

[0080] Fig.12It is a cross-sectional view along line AA after etching the third oxide layer in one embodiment.

[0081] Fig.13 FIG. 4 is a schematic diagram after forming a first insulating material layer in an embodiment.

[0082] Fig.14 It is a cross-sectional view along line AA after forming a first insulating material layer in one embodiment.

[0083] Fig.15 FIG. 4 is a schematic diagram after forming an insulating sidewall in one embodiment.

[0084] Fig.16 It is a cross-sectional view along line AA after forming an insulating sidewall in one embodiment.

[0085] Fig.17 FIG. 4 is a schematic diagram after forming a first dielectric layer in an embodiment.

[0086] Fig.18 FIG. 4 is a schematic diagram after forming a mask layer in one embodiment.

[0087] Fig.19 FIG. 1 is a schematic diagram after forming a first trench in an embodiment.

[0088] Fig. 20 FIG. 4 is a schematic diagram after forming a second dielectric material layer in one embodiment.

[0089] Fig.21 FIG. 5 is a cross-sectional view along line BB after forming a second dielectric layer in one embodiment.

[0090] Fig. 22 FIG. 1 is a schematic diagram after the second dielectric layer and the second oxide layer are removed in one embodiment.

[0091] Fig.23 It is a cross-sectional view along line AA after the second dielectric layer and the second oxide layer are removed in one embodiment.

[0092] Fig.24 FIG. 1 is a cross-sectional view along line BB after the second dielectric layer and the second oxide layer are removed in one embodiment.

[0093] Fig.25 It is a cross-sectional view along line AA after a gate dielectric layer is formed in one embodiment.

[0094] Fig.26 for Fig.24 A partial enlarged view of point A in the middle.

[0095] Fig. 27 A cross-sectional view along line AA after forming a work function layer in one embodiment.

[0096] Fig.28 A cross-sectional view along line BB after forming a work function layer in one embodiment.

[0097] Fig.29 FIG. 1 is a schematic diagram after a conductive layer is formed in one embodiment.

[0098] Fig.30 FIG. 1 is a schematic diagram after word lines are formed in one embodiment.

[0099] Fig.31 FIG. 1 is a cross-sectional view along line AA after word lines are formed in one embodiment.

[0100] Fig.32 FIG. 1 is a cross-sectional view along line BB after word lines are formed in one embodiment.

[0101] Fig.33 FIG. 4 is a schematic diagram after forming a second insulating material layer in one embodiment.

[0102] Fig.34 FIG. 4 is a schematic diagram after forming a second insulating layer in one embodiment.

[0103] Fig.35 FIG. 5 is a cross-sectional view along line BB after forming a second insulating layer in one embodiment.

[0104] Fig.36 FIG. 1 is a schematic diagram of an embodiment after the second dielectric layer is removed to expose the first trench.

[0105] Fig.37 FIG. 1 is a cross-sectional view along line BB after forming the first trench in one embodiment.

[0106] Fig.38 It is a cross-sectional view along line BB after forming a protection layer in one embodiment.

[0107] Fig.39 FIG. 1 is a schematic diagram after forming a sacrificial material layer in one embodiment.

[0108] Fig.40 FIG. 1 is a cross-sectional view along line BB after forming a sacrificial material layer in one embodiment.

[0109] Fig.41 FIG. 1 is a schematic diagram after forming a sacrificial layer in one embodiment.

[0110] Fig.42 FIG. 5 is a cross-sectional view along line BB after a sacrificial layer is formed in one embodiment.

[0111] Fig.43 FIG. 4 is a schematic diagram after forming a top insulating layer in one embodiment.

[0112] Fig.44FIG. 1 is a cross-sectional view along line BB after a top insulating layer is formed in one embodiment.

[0113] Fig.45 FIG. 1 is a cross-sectional view along line BB after an air layer is formed in one embodiment.

[0114] Fig.46 FIG. 1 is a schematic diagram of an embodiment after the top insulating layer is etched to expose the surface of the third semiconductor layer.

[0115] Fig.47 FIG. 4 is a schematic diagram after forming a third insulating layer in an embodiment.

[0116] Fig.48 It is a cross-sectional view along line AA after forming a third insulating layer in one embodiment.

[0117] Fig.49 FIG. 5 is a cross-sectional view along line BB after forming a third insulating layer in one embodiment.

[0118] Fig.50 FIG. 4 is a schematic diagram after a photoresist layer is formed in one embodiment.

[0119] Fig.51 FIG. 4 is a schematic diagram after forming a second through hole in an embodiment.

[0120] Fig.52 FIG. 5 is a cross-sectional view along line BB after forming the second through hole in one embodiment.

[0121] Fig.53 FIG. 5 is a cross-sectional view along line BB after a metal material layer is formed in one embodiment.

[0122] Fig.54 FIG. 1 is a cross-sectional view along line AA after forming a capacitor contact portion in one embodiment.

[0123] Fig.55 FIG. 1 is a cross-sectional view along line BB after forming a capacitor contact portion in one embodiment.

[0124] Description of reference numerals:

[0125] 10. Initial structure; 11. Substrate; 12. First semiconductor column; 13. Isolation structure; 14. Bit line; 15. Bit line contact layer; 20. Second semiconductor column; 21. First region; 22. Second region; 23. Third region; 30. Third semiconductor layer; 40. Word line; 41. Gate dielectric layer; 411. First gate dielectric material layer; 412. Second gate dielectric material layer; 50. Work function layer; 60. Insulating dielectric layer; 70. Air layer; 80. Top insulating layer; 90. Capacitor contact; 140. Insulating sidewall; 141. First insulating material layer; 142. First insulating layer; 241 , second insulating material layer; 242, second insulating layer; 342, third insulating layer; 151, first dielectric layer; 251, second dielectric layer; 252, second dielectric material layer; 161, first trench; 161a, mask layer; 165, first through hole; 265, second through hole; 170, sacrificial layer; 171, sacrificial material layer; 191, conductive layer; 192, protective layer; 193, metal material layer; 310, initial insulating dielectric layer; 311, first oxide layer; 312, first nitride layer; 313, second oxide layer; 314, second nitride layer; 315, third oxide layer;

[0126] D1, first direction; D2, second direction; D3, third direction. DETAILED DESCRIPTION

[0127] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0128] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0129] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0130] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0131] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "consisting of" and / or "comprising" are used in this specification, the presence of the features, integers, steps, operations, elements and / or parts can be determined, but the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups is not excluded. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0132] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic diagrams of ideal embodiments (and intermediate structures) of the invention, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the invention.

[0133] With the development of dynamic random access memory (DRAM), the unit area of ​​the gate transistor in the array part of the dynamic random access memory has been continuously miniaturized from 6F2 to 4F2, where F refers to Feature, i.e., feature size, which is usually 1 / 2 of the spacing between word lines or 1 / 2 of the spacing between bit lines. Reducing the spacing between word lines and bit lines can reduce the unit area of ​​the gate transistor and further improve the integration density of devices in the dynamic random access memory. However, the reduction in feature size will cause the parasitic capacitance between word lines to increase, and the increase in parasitic capacitance between word lines will cause resistance capacitance response delay (Resistance Capacitance delay), reduce the operating speed of the dynamic random access memory, and even cause the dynamic random access memory to fail to work.

[0134] In view of this, the present application provides a method for manufacturing a semiconductor structure, such as Figure 1 As shown, Figure 1 A flowchart of a method for manufacturing a semiconductor structure provided according to an exemplary embodiment of the present disclosure is shown. The method for manufacturing a semiconductor structure comprises the following steps:

[0135] Step S110: providing an initial structure, the initial structure comprising a plurality of first semiconductor pillars, the plurality of first semiconductor pillars being arranged in a plurality of rows along a first direction.

[0136] Step S120: forming a plurality of second semiconductor columns, the plurality of second semiconductor columns are arranged in a plurality of columns along a first direction, each second semiconductor column is correspondingly arranged on each first semiconductor column and connected to the first semiconductor column, and the second semiconductor column comprises a first region, a second region and a third region sequentially arranged in a direction away from the first semiconductor column.

[0137] Step S130 : forming a word line, wherein the word line extends along a first direction and covers a side wall of a second region of a row of second semiconductor pillars arranged along the first direction.

[0138] Step S140: forming a sacrificial layer, wherein the sacrificial layer extends between adjacent word lines along a first direction, and the sacrificial layer at least fills a portion of the space between adjacent word lines.

[0139] Step S150 : forming a top insulating layer, wherein the top insulating layer covers the top surface of the sacrificial layer and fills the unfilled space between two adjacent columns of second semiconductor pillars arranged along the first direction.

[0140] Step S160: removing the sacrificial layer, and forming an air layer at the position where the sacrificial layer is removed.

[0141] The method for manufacturing the semiconductor structure provided in this embodiment forms an air layer between adjacent word lines, and the air dielectric constant is relatively low. In this way, the existence of the air layer can reduce the parasitic capacitance between adjacent word lines, improve the resistance and capacitance response delay caused by the parasitic capacitance between the word lines, and is beneficial to improving the response speed of the semiconductor structure and improving the electrical performance of the semiconductor structure.

[0142] Below, this embodiment is described in detail with reference to the accompanying drawings:

[0143] In step S110, Figure 2 , Figure 3 , Figure 4 As shown, the initial structure 10 provided in this embodiment includes a substrate 11, a plurality of first semiconductor pillars 12 arranged on the substrate 11, and an isolation structure 13 filled between the first semiconductor pillars 12. The top surfaces of the first semiconductor pillars 12 and the isolation structure 13 are flush, and the initial structure 10 exposes the top surfaces of the plurality of first semiconductor pillars 12. The plurality of first semiconductor pillars 12 are arranged on the substrate 11 and connected to the substrate 11. The plurality of first semiconductor pillars 12 are arranged in a plurality of columns along a first direction D1. The plurality of columns of first semiconductor pillars 12 are spaced apart in a second direction D2. The first semiconductor pillars 12 extend along a third direction perpendicular to the top surface of the substrate 11, wherein the first direction D1 and the second direction D2 are parallel to the top surface of the substrate 11, and the first direction D1 and the second direction D2 are perpendicular. In this embodiment, refer to Figure 3 As shown, the first semiconductor pillars 12 in two adjacent columns are staggered to increase the distance between the first semiconductor pillars 12 in the two adjacent columns, which is beneficial to increase the arrangement density of the first semiconductor pillars 12 and improve the device integration density of the semiconductor structure. It can be understood that in other embodiments, the plurality of first semiconductor pillars 12 can be arranged in a rectangular array along the first direction D1 and the second direction D2.

[0144] Among them, the substrate 11 can be a semiconductor substrate, the material of the semiconductor substrate can be silicon (Si), germanium (Ge), or silicon germanium (GeSi), silicon carbide (SiC); the material of the semiconductor substrate can also be silicon on insulator (SOI), germanium on insulator (GOI), and the semiconductor substrate can be doped with conductive ions.

[0145] The material of the first semiconductor column 12 may include silicon, germanium, or silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide or other materials with semiconductor properties, such as III / V group compounds or II / VI group compounds, and the first semiconductor column 12 may be doped with conductive ions.

[0146] The material of the isolation structure 13 may include at least one of silicon oxide, silicon nitride or silicon oxynitride.

[0147] In this embodiment, Figure 2 As shown, the initial structure 10 further includes a plurality of bit lines 14, which are bent and extended in a curved shape, are arranged in parallel, and each bit line 14 covers a portion of the circumference of a column of first semiconductor pillars 12. A bit line contact layer 15 is arranged between the bit line 14 and the circumference of the first semiconductor pillar 12, and the bit line contact layer 15 is used to achieve ohmic contact between the bit line 14 and the first semiconductor pillar 12, thereby reducing the contact resistance between the bit line 14 and the first semiconductor pillar 12.

[0148] In step S120, a plurality of second semiconductor pillars are formed, including the following steps:

[0149] Step S121: forming an initial insulating dielectric layer, wherein the initial insulating dielectric layer covers the top surface of the initial structure.

[0150] An insulating material may be deposited to form an initial insulating dielectric layer 310, and the initial insulating dielectric layer 310 covers the top surface of the initial structure 10. The initial insulating dielectric layer 310 is used to electrically isolate the subsequent devices from the initial structure 10.

[0151] In this embodiment, the initial insulating dielectric layer 310 may be formed by the following implementations:

[0152] like Figure 4 As shown, refer to Figure 2Any one of the deposition processes, including chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD) or sputtering, or a combination of several deposition processes, can be used to sequentially deposit oxides and nitrides to form a first oxide layer 311, a first nitride layer 312, a second oxide layer 313, a second nitride layer 314 and a third oxide layer 315 sequentially covering the top surface of the initial structure 10. The first oxide layer 311, the first nitride layer 312, the second oxide layer 313, the second nitride layer 314 and the third oxide layer 315 together form an initial insulating dielectric layer 310.

[0153] The initial insulating dielectric layer 310 formed in this embodiment is a stacked structure of oxide layer-nitride layer-oxide layer-nitride layer-oxide layer, and the nitride layer has a high etching selectivity relative to the oxide layer. For example, the materials of the first oxide layer 311, the second oxide layer 313, and the third oxide layer 315 may include silicon oxide, and the materials of the first nitride layer 312 and the second nitride layer 314 may include silicon nitride.

[0154] Step S122: etching the initial insulating dielectric layer to form a plurality of first through holes corresponding to the first semiconductor pillars in the initial insulating dielectric layer, each of the first through holes exposing at least a portion of the top surface of the corresponding first semiconductor pillar.

[0155] Figure 6 Schematic diagram showing the formation of the first through hole 165, Figure 7 The diagram shows the structure along line AA (see FIG. Figure 3 ). Figure 6 , Figure 7 As shown, refer to Figure 4 , Figure 5 , the initial insulating dielectric layer 310 is etched, a portion of the initial insulating dielectric layer 310 is removed until the top surface of the initial structure 10 is exposed, and a first through hole 165 is correspondingly formed on each first semiconductor column 12, the first through hole 165 penetrates the initial insulating dielectric layer 310 and exposes a portion of the top surface of the first semiconductor column 12.

[0156] Step S123: forming a second semiconductor pillar in each first through hole.

[0157] like Figure 8 As shown, refer to Figure 6A second semiconductor column 20 can be formed in the first through hole 165 by using an epitaxial process or a deposition process. The material of the second semiconductor column 20 can include silicon, germanium, or silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide or other materials with semiconductor properties, such as III / V group compounds or II / VI group compounds. The second semiconductor column 20 can be doped with conductive ions.

[0158] Exemplarily, in this embodiment, the second semiconductor pillar 20 is formed by deposition using a selective epitaxial process, and the following implementation methods may be used:

[0159] like Figure 8 As shown, refer to Figure 6 , Fig.10 , placing the semiconductor structure in a reaction chamber, using the top surface of the first semiconductor column 12 exposed by the first through hole 165 as a seed crystal, introducing a gas source for forming the second semiconductor column 20 into the reaction chamber, and using a chemical vapor deposition process to epitaxially grow the second semiconductor column 20.

[0160] In this embodiment, the material of the second semiconductor pillar 20 includes silicon. After the semiconductor structure is placed in the reaction chamber, the temperature in the reaction chamber is adjusted to 550° C. to 650° C., such as 550° C., 600° C. or 650° C., and then a silicon source gas, such as silane and / or higher order silane, is introduced into the reaction chamber. The higher order silane may include at least one of disilane and neopentasilane (NPS), and the second semiconductor pillar 20 is epitaxially grown on the exposed surface of the first semiconductor pillar 12 to fill the first through hole 165.

[0161] Reference Fig.10 The second semiconductor columns 20 are disposed on and connected to the first semiconductor columns 12 . The second semiconductor columns 20 are arranged according to the arrangement of the first semiconductor columns 12 . The second semiconductor columns 20 are arranged in multiple rows along the first direction D1 .

[0162] Each second semiconductor column 20 includes a first region 21, a second region 22, and a third region 23 which are sequentially arranged in a direction away from the first semiconductor column 12 (i.e., in a third direction D3). The portion of each second semiconductor column 20 covered by the second oxide layer 313 is the second region 22, the second semiconductor column 20 located below the second region 22 is the first region 21, and the second semiconductor column 20 located above the second region 22 is the third region 23. Among them, the second region 22 is the portion of each second semiconductor column 20 that is subsequently in contact with and connected to the word line 40 (which will be described in detail in the subsequent steps). In this embodiment, when forming the initial insulating dielectric layer 310, the thickness of the second region 22 can be defined by adjusting the thickness of the second oxide layer 313, thereby limiting the height of the word line 40 formed subsequently, and improving the accuracy of process control.

[0163] In this embodiment, after step S120, the following steps are further performed:

[0164] Step S10: forming a third semiconductor layer, wherein the third semiconductor layer covers the top surface of the second semiconductor column, and the projection of the second semiconductor column on the initial structure falls within the projection of the third semiconductor layer on the initial structure.

[0165] like Fig. 9 , Fig.10 As shown, refer to Figure 8 After forming the second semiconductor column 20, the pressure in the reaction chamber is adjusted to 420° C. to 500° C., such as 420° C., 450° C., 470° C. or 800° C. Then, a phosphorus-containing gas source is introduced into the reaction chamber to epitaxially form a third semiconductor layer 30 on the top surface of the second semiconductor column 20. In this embodiment, the material of the third semiconductor layer 30 includes polycrystalline silicon doped with phosphorus ions.

[0166] In this embodiment, the radial dimension of the third semiconductor layer 30 is greater than the radial dimension of the second semiconductor column 20. The projection formed by the second semiconductor column 20 on the initial structure 10 falls within the projection formed by the third semiconductor layer 30 on the initial structure 10. In this way, in the subsequent process, the third semiconductor layer 30 can be used as a mask for self-aligned etching, thereby reducing the difficulty of the subsequent process.

[0167] Step S20 : ​​forming an insulating sidewall, wherein the insulating sidewall covers the sidewall of the third region of the second semiconductor column.

[0168] In this embodiment, forming the insulating sidewall includes the following steps:

[0169] Step S201: etching the initial insulating dielectric layer using the third semiconductor layer as a mask to remove a portion of the initial insulating dielectric layer around the third region of the second semiconductor column, with the sidewall of the third region being covered by the initial insulating dielectric layer retained by the etching.

[0170] Fig.11 Schematic diagram showing the etching of the third oxide layer 315, Fig.12 The AA line (refer to FIG. Figure 3 ) cross-section, such as Fig.11 , Fig.12 As shown, the initial insulating dielectric layer 310 is etched using the third semiconductor layer 30 as a mask. The etching process can be a dry process or a wet process, and the etching process has a high etching selectivity relative to the nitride layer. The etching stops at the second nitride layer 314, and the third oxide layer 315 exposed by the third semiconductor layer 30 is removed. The third oxide layer 315 blocked by the third semiconductor layer 30 is etched and retained. The etched and retained third oxide layer 315 covers the circumference of the third region 23 of the second semiconductor column 20 to avoid the third region 23 of the second semiconductor column 20 being directly exposed to the process environment, and to avoid the second semiconductor column 20 reacting with the gas or other impurities in the process environment to reduce the conductivity of the second semiconductor column 20.

[0171] In this embodiment, the third semiconductor layer 30 is used as a mask to self-align and etch the initial insulating dielectric layer 310, with high alignment accuracy and small etching deviation. At the same time, a mask forming process is saved, the process cost is saved, and the process efficiency is improved.

[0172] Step S202: forming a first insulating layer, wherein the first insulating layer covers the surface of the initial insulating dielectric layer retained by etching and the top surface of the third semiconductor layer.

[0173] Fig.13 Schematic diagram showing the formation of the first insulating material layer 141, Fig.14 The diagram shows the structure along line AA (see FIG. Figure 3 ) cross-section, such as Fig.13 , Fig.14 As shown, first, any deposition process including chemical vapor deposition process, physical vapor deposition process, atomic layer deposition process or sputtering can be selected to deposit and form the first insulating material layer 141, and the first insulating material layer 141 covers the surface of the third semiconductor layer 30, the third oxide layer 315 on the sidewall of the third region 23, and the top surface of the second nitride layer 314. The material of the first insulating material layer 141 may include at least one of silicon nitride or silicon oxynitride. In this embodiment, the material of the first insulating material layer 141 includes silicon nitride, that is, the material of the first insulating material layer 141 is the same as the material of the second nitride layer 314.

[0174] Then, the first insulating material layer 141 is etched by an anisotropic etching process. The etching rate of the anisotropic etching process along the vertical direction is much greater than the etching rate along the horizontal direction. The first insulating material layer 141 covering the surface of the third semiconductor layer 30 and the first insulating material layer 141 covering the second nitride layer 314 are etched away to expose the surface of the second nitride layer 314. The first insulating material layer 141 covering the third oxide layer 315 is retained to form a first insulating layer 142.

[0175] Step S203: Etch the first insulating layer to remove the first insulating layer located on the top surface of the third semiconductor layer and the first insulating layer located on the top surface of the initial insulating dielectric layer. The first insulating layer covering the side wall of the third region is etched and retained. The initial insulating dielectric layer and the first insulating layer covering the side wall of the third region together form an insulating side wall.

[0176] Fig.15 Schematic diagram showing the insulating sidewall 140 after it is formed, Fig.16 The diagram shows the structure along line AA (see FIG. Figure 3 ) cross-section, such as Fig.15 , Fig.16 As shown, the exposed second nitride layer 314 is continuously etched using an anisotropic etching process until the top surface of the second oxide layer 313 is exposed, and a portion of the second nitride layer 314 located below the first insulating layer 142 is retained, and the etched and retained second nitride layer 314, the third oxide layer 315 and the first insulating layer 142 are together formed into an insulating sidewall 140. The insulating sidewall 140 is an insulating structure in which a nitride layer wraps an oxide layer. The insulating sidewall 140 has better electrical isolation performance, which is beneficial to avoiding the problem of conduction caused by short circuits caused by adjacent second semiconductor pillars 20 being too close.

[0177] Step S30: forming an insulating dielectric layer, the insulating dielectric layer covering the top surface of the initial structure and the sidewalls of the first region of the second semiconductor column, the word line and the initial structure being separated by the insulating dielectric layer.

[0178] In this embodiment, forming the insulating dielectric layer includes the following steps:

[0179] Step S301: forming a first dielectric layer, wherein the first dielectric layer covers the top surface of the initial insulating dielectric layer, the surface of the insulating sidewalls and fills the space between the third regions.

[0180] like Fig.17 As shown, refer to Fig.15The first dielectric layer 151 can be formed by depositing a first dielectric layer 151 using any deposition process including a chemical vapor deposition process, a physical vapor deposition process, an atomic layer deposition process or a sputtering process. The first dielectric layer 151 covers the top surface of the second oxide layer 313, the surface of the third semiconductor layer 30, the surface of the insulating sidewall 140 and fills the space between the third regions 23. The top surface of the first dielectric layer 151 is higher than the top surface of the third semiconductor layer 30.

[0181] The material of the first dielectric layer 151 is selected to have the same etching selectivity as the material of the second oxide layer 313. In this embodiment, the material of the first dielectric layer 151 includes silicon oxide.

[0182] Step S302: etching and removing a portion of the first dielectric layer and a portion of the initial insulating dielectric layer to form a first trench, wherein the first trench extends between two adjacent columns of second semiconductor pillars along a first direction, and the first trench exposes a portion of the surface of the insulating sidewall.

[0183] like Fig.18 As shown, refer to Fig.17 A mask layer 161a is formed on the top surface of the first dielectric layer 151, and the mask layer 161a defines the pattern of the first trench 161 to be formed. Fig.19 As shown, with the top surface of the first nitride layer 312 as an etching stop layer, the first dielectric layer 151 and the second oxide layer 313 are sequentially etched according to the mask layer 161a, and a first trench 161 extending along the first direction D1 is formed on the second nitride layer 314. The first trench 161 is located between two columns of second semiconductor pillars 20 arranged along the first direction D1. The first trench 161 exposes a portion of the surface of the insulating sidewall 140 on the second semiconductor pillar 20 adjacent to it. The first trench 161 and the second semiconductor pillar 20 are separated by the insulating sidewall 140 and the second oxide layer 313 retained by etching.

[0184] Step S303: forming a second dielectric layer in the first trench, the second dielectric layer extending along the first direction, the second dielectric layer and the second semiconductor pillars being alternately arranged along a second direction perpendicular to the first direction, and the top surface of the second dielectric layer being higher than the top surface of the third semiconductor layer.

[0185] like Fig. 20 As shown, refer to Fig.19 First, a second dielectric material layer 252 may be formed by deposition using any deposition process such as chemical vapor deposition, physical vapor deposition, atomic layer deposition or sputtering. The second dielectric material layer 252 fills the first trench 161 and covers the top surface of the first dielectric layer 151. The material of the second dielectric layer 251 may include at least one of single crystal silicon or polycrystalline silicon.

[0186] Fig.21The diagram shows the structure along line BB (refer to Figure 3 ) cross-section, such as Fig.21 As shown, refer to Fig. 20 , the second dielectric material layer 252 is etched, the second dielectric material layer 252 covering the top surface of the first dielectric layer 151 and the portion of the second dielectric material layer 252 filling the top of the first trench 161 are removed, and the second dielectric material layer 252 retained in the first trench 161 is formed into a second dielectric layer 251, and the second dielectric layer 251 is arranged between two columns of second semiconductor pillars 20 arranged along the first direction D1. The second dielectric layers 251 and the second semiconductor pillars 20 are alternately arranged along the second direction D, and the second dielectric layer 251 and the second semiconductor pillars 20 adjacent thereto are separated by the insulating sidewall 140.

[0187] In this embodiment, the top surface of the second dielectric layer 251 is higher than the top surface of the third semiconductor layer 30 , so that the second dielectric layer 251 can be used to limit the manufacturing process later.

[0188] Step S304: etching and removing the first dielectric layer and part of the initial insulating dielectric layer to expose the sidewall of the second region of the second semiconductor column, and retaining the initial insulating dielectric layer below the second dielectric layer to form an insulating dielectric layer, which covers the sidewall of the first region of the second semiconductor column.

[0189] like Fig. 22 , Fig.23 , Fig.24 As shown, refer to Fig.21 The second dielectric layer 251 and the second oxide layer 313 are removed by wet etching to expose the sidewall of the second region 22 of the second semiconductor column 20 and the space between the second region 22 and the third region 23 of the second semiconductor column 20 arranged along the first direction D1. The initial insulating dielectric layer 310 located below the second dielectric layer 251 is formed into an insulating dielectric layer 60, that is, the insulating dielectric layer 60 includes a first oxide layer 311 and a first nitride layer 312 (such as Fig.54 and Fig.55 As shown in FIG. 1 , an insulating dielectric layer 60 is disposed between a subsequently formed word line 40 and the initial structure 10 to prevent the word line 40 and a device (such as a bit line 14) in the initial structure 10 from being short-circuited.

[0190] It can be understood that in this step, second dielectric layers 251 are formed on both sides of each column of second semiconductor pillars 20 arranged along the first direction D1 , that is, a space for a word line 40 to be formed subsequently is defined between two adjacent second dielectric layers 251 .

[0191] Step S40: forming a work function layer, wherein the work function layer covers the side wall of the second region of the second semiconductor column, and the word line and the side wall of the second region are connected through the work function layer.

[0192] In this embodiment, forming a work function layer includes the following steps:

[0193] Step S401: forming a gate dielectric layer, wherein the gate dielectric layer covers the sidewalls of the second region.

[0194] In this embodiment, the following implementation is adopted:

[0195] Reference Fig.25 , Fig.26 As shown, refer to Fig. 22 , Fig.23 , Fig.24 First, an atomic layer deposition process is used to deposit and form a first gate dielectric material layer 411, the first gate dielectric material layer 411 covers the sidewall of the second region 22, the surface of the insulating sidewall 140, the surface of the third semiconductor layer 30, the surface of the second dielectric layer 251, and the top surface of the second nitride layer 314 exposed by the second semiconductor pillars 20 arranged along the first direction D1, and the material of the first gate dielectric material layer 411 can be selected from at least one of silicon dioxide (SiO2), silicon oxynitride (SiON), silicon nitride, aluminum oxide (Al2O3), and aluminum oxynitride (AlON). In this embodiment, the material of the first gate dielectric material layer 411 includes silicon oxide, and the thickness of the first gate dielectric material layer 411 is 1.2nm.

[0196] Then, refer to Fig.26 , an atomic layer deposition process is used to deposit and form a second gate dielectric material layer 412, and the second gate dielectric material layer 412 covers the first gate dielectric material layer 411. The material of the second gate dielectric material layer 412 is a high-k dielectric material (a dielectric material with a dielectric constant greater than or equal to 3.9), for example, the material of the second gate dielectric material layer 412 may include at least one of aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2) or strontium titanium oxide (SrTiO3). In this embodiment, the material of the second gate dielectric material layer 412 includes hafnium oxide, and the thickness of the second gate dielectric material layer 412 is 1.4nm.

[0197] After forming the first gate dielectric material layer 411 and the second gate dielectric material layer 412, an etching step needs to be performed to remove the first gate dielectric material layer 411 and the second gate dielectric material layer 412 covering the surface of the third semiconductor layer 30 and the surface of the second dielectric layer 251 to form a gate dielectric layer 41. The formed gate dielectric layer 41 includes a double-layer structure of the first gate dielectric material layer 411 and the second gate dielectric material layer 412 sequentially covering the side walls of the second region 22.

[0198] It can be understood that the step of etching the first gate dielectric material layer 411 and the second gate dielectric material layer 412 can be performed after the first gate dielectric material layer 411 and the second gate dielectric material layer 412 are formed; or, after the first gate dielectric material layer 411 and the second gate dielectric material layer 412 are formed, the subsequent steps of forming the work function layer 50 and forming the word line 40 can be performed first, and in the subsequent etching step, the first gate dielectric material layer 411 and the second gate dielectric material layer 412 covering the surface of the third semiconductor layer 30 and the surface of the second dielectric layer 251 are removed to save process steps and improve process efficiency. In the subsequent steps, the embodiment in which the steps of forming the work function layer 50 and forming the word line 40 can be performed first after the first gate dielectric material layer 411 and the second gate dielectric material layer 412 are formed, and then the first gate dielectric material layer 411 and the second gate dielectric material layer 412 are etched will be described in detail.

[0199] Step S402: forming a work function material layer, wherein the work function material layer covers the surface of the gate dielectric layer.

[0200] The work function material layer 51 is deposited and formed by an atomic layer deposition process. The work function material layer 51 covers the second gate dielectric material layer 412 . In this embodiment, the material of the work function material layer 51 may include titanium nitride.

[0201] Step S403: etching the work function material layer using the insulating sidewall as a mask, and the work function material layer shielded by the insulating sidewall is etched away to form a work function layer.

[0202] like Fig. 27 , Fig.28 As shown, a dry process or a wet process can be used to etch the work function material layer 51, and the work function material layer 51 exposed by the insulating sidewall 140 is removed. The work function material layer 51 located below the insulating sidewall 140 is etched and retained to form a work function layer 50. The work function layer 50 covers the sidewall of the second region 22 of the second semiconductor column 20, and the work function layer 50 and the second region 22 are separated by the first gate dielectric material layer 411 and the second gate dielectric material layer 412 (refer to Fig.26 ) separated by .

[0203] In step S130, a word line is formed, including the following steps:

[0204] First, if Fig.29 As shown, a conductive layer 191 is formed, and the conductive layer 191 covers the work function layer 50 and fills the unfilled space between the second semiconductor pillars 20. For example, any deposition process among chemical vapor deposition process, physical vapor deposition process, atomic layer deposition process or sputtering process can be selected to deposit and form the conductive layer 191, and the conductive layer 191 covers the work function layer 50 and fills the unfilled space between the second semiconductor pillars 20, and the top surface of the conductive layer 191 is higher than the top surface of the second dielectric layer 251.

[0205] Then, if Fig.30 , Fig.31 , Fig.32 As shown, refer to Fig.29 , etching the conductive layer 191 , removing the conductive layer 191 filled between the third regions 23 , and dividing the conductive layer 191 into word lines 40 extending along the first direction D1 .

[0206] In this embodiment, the conductive layer 191 can be etched by a dry process or a wet process to remove the conductive layer 191 located above the second dielectric layer 251 and the third region 23 filled in the second semiconductor column 20 (see Fig.10 ), the conductive layer 191 filled between the second regions 22 of the second semiconductor pillars 20 is etched and retained to form word lines 40. In this embodiment, in the process of etching the conductive layer 191 to form the word lines 40, the conductive layer 191 is divided into a plurality of word lines 40 extending along the first direction D1 by self-alignment and limiting of the second dielectric layer 251, and each word line 40 is filled in the space between the second regions 22 of the second semiconductor pillars 20 extending along the first direction D1, thereby saving the process of forming a mask on the top surface of the conductive layer 191, streamlining the process, improving the process efficiency, and reducing the process cost.

[0207] The material of the word line 40 may include at least one of indium tin oxide, polysilicon, copper, tungsten, aluminum, copper alloy, titanium, titanium nitride, palladium nitride, and tantalum nitride. In this embodiment, the material of the word line 40 includes tungsten.

[0208] In this embodiment, after step S130 and before step S140, the following steps are further performed:

[0209] Step S50 : forming a second insulating layer, wherein the second insulating layer fills the unfilled spaces between the third regions of the second semiconductor pillars.

[0210] like Fig.33 As shown, refer to Fig.32The second insulating material layer 241 can be formed by depositing any one of chemical vapor deposition, physical vapor deposition, atomic layer deposition or sputtering processes, and the second insulating material layer 241 covers the top surface of the word line 40, the top surface of the second dielectric layer 251 and fills the unfilled space between the third region 23 of the second semiconductor column 20.

[0211] like Fig.34 , Fig.35 As shown, refer to Fig.33 The second insulating material layer 241 is polished by a chemical mechanical polishing (CMP) process with the top surface of the second dielectric layer 251 as a polishing stop surface, and the second insulating material layer 241 located above the top surface of the second dielectric layer 251 is polished away, and the second insulating material layer 241 is divided into a plurality of second insulating layers 242, each of which is disposed on a word line 40, and each of which covers the top surface of the word line 40 corresponding thereto and fills the third region 23 of the second semiconductor pillar 20 extending along the first direction D1 (refer to Fig.10 Since the top surface of the second dielectric layer 251 is higher than the top surface of the third semiconductor layer 30, the top surface of the second insulating layer 242 formed in this embodiment is higher than the top surface of the third semiconductor layer 30.

[0212] The material of the second insulating layer 242 may include silicon oxide or silicon oxynitride. In the present embodiment, the material of the second insulating layer 242 includes silicon oxide.

[0213] In step S140, a sacrificial layer is formed, including the following steps:

[0214] Step S141: removing the second dielectric layer to expose the first trench.

[0215] like Fig.36 , Fig.37 As shown, refer to Fig.35 The second dielectric layer 251 may be removed by etching using a dry process or a wet process to expose the first trench 161 again. The first trench 161 is located between two columns of second semiconductor pillars 20 arranged along the first direction D1.

[0216] In this embodiment, the first trench 161 exposes the second gate dielectric material layer 412 originally covering the second dielectric layer 251. Therefore, after removing the second dielectric layer 251, the second gate dielectric material layer 412 and the first gate dielectric material layer 411 originally covering the second dielectric layer 251 can be sequentially etched away using a dry process or a wet process (refer to Fig.26 ), exposing the sidewalls of the word line 40 and the sidewalls of the second insulating layer 242.

[0217] It should be noted that the first gate dielectric material layer 411 and the second gate dielectric material layer 412 covered on the surface of the second dielectric layer 251 mentioned in step S401 are etched away in this step.

[0218] Then, if Fig.38 As shown, refer to Fig.37 Any of the above deposition processes can be used to deposit and form a protective layer 192, which covers the side walls of the first trench 161 (including the side walls of the word line 40 and the side walls of the second insulating layer 242) and the bottom wall of the first trench 161, thereby preventing the word line 40 from being directly exposed to the process environment and preventing subsequent process steps from damaging the word line 40, resulting in a decrease in product yield, electrical performance, and safety.

[0219] Step S142: forming a sacrificial material layer, wherein the sacrificial material layer fills the first trench.

[0220] like Fig.39 , Fig.40 As shown, refer to Fig.38 Any one of chemical vapor deposition, physical vapor deposition, atomic layer deposition or sputtering deposition processes or several deposition processes may be selected to deposit and form a sacrificial material layer 171 , which fills the first groove 161 and covers the top surface of the protective layer 192 .

[0221] Step S143: etching the sacrificial material layer until the top surface is lower than the top surface of the word line, so as to form a sacrificial layer in the first trench.

[0222] like Fig.41 , Fig.42 As shown, refer to Fig.39 , Fig.40 The sacrificial material layer 171 may be ground by chemical mechanical polishing to reduce the thickness of the etched sacrificial material layer 171. Then, the sacrificial material layer 171 may be etched by dry process or wet process to remove the sacrificial material layer 171 on the top surface of the second insulating layer 242, and the sacrificial material layer 171 in the first trench 161 is etched to be lower than the top surface of the word line 40, and the sacrificial material layer 171 retained in the first trench 161 forms the sacrificial layer 170.

[0223] The height of the sacrificial layer 170 defines the height of the subsequently formed air layer 70 . Therefore, the higher the height of the sacrificial layer 170 , the higher the height of the formed air layer 70 , and the better the effect of reducing the parasitic capacitance between adjacent word lines 40 . In this embodiment, the top surface of the sacrificial layer 170 is flush with the top surface of the word line 40 .

[0224] The material of the sacrificial layer 170 is selected to have a high etching selectivity ratio with the second insulating layer 242 and the protective layer 192 . In this embodiment, the material of the sacrificial layer 170 includes silicon nitride or silicon nitride oxide.

[0225] In step S150, Fig.43 , Fig.44 As shown, refer to Fig.41 , Fig.42 A top insulating layer 80 can be formed by depositing any one of chemical vapor deposition, physical vapor deposition, atomic layer deposition or sputtering processes, and the top insulating layer 80 covers the top surface of the sacrificial layer 170, the top surface of the second insulating layer 242 and fills the unfilled space of the first trench 161.

[0226] In this embodiment, the material of the top insulating layer 80 and the sacrificial layer 170 are selected to have a high etching selectivity ratio. In this embodiment, the material of the top insulating layer 80 includes silicon oxide.

[0227] In step S160, if Fig.45 As shown, refer to Fig.44 The sacrificial layer 170 can be removed by dissolving with hot phosphoric acid to expose the first groove 161 below the top insulating layer 80, and an air layer 70 is formed below the top insulating layer 80. The air layer 70 extends along the first direction D1. The air layer 70 is arranged between adjacent word lines 40. Along the second direction D2, the word lines 40 and the air layer 70 are alternately arranged, and the word lines 40 and the air layer 70 are separated by the protective layer 192.

[0228] The manufacturing method of the semiconductor structure of the present embodiment forms a sacrificial layer 170 in the first groove 161 between adjacent word lines 40, then forms a top insulating layer 80 covering the sacrificial layer 170, and then removes the sacrificial layer 170 to form an air layer 70 at the position where the sacrificial layer 170 is removed. In this way, the size of the air layer 70 formed between adjacent word lines 40 is large, which can reduce the parasitic capacitance between adjacent word lines 40 to a greater extent, avoid resistance and capacitance response delay, and improve the operating speed of the semiconductor structure.

[0229] In the method for manufacturing the semiconductor structure of the present embodiment, the initial insulating dielectric layer formed on the initial structure is an alternating stacked structure formed of oxide layers and nitride layers, and the oxide layers and the nitride layers have a high etching selectivity ratio. In etching the initial insulating dielectric layer, the top surface of the heterogeneous layer can be used as a stop layer, thereby reducing the difficulty of monitoring the process progress and improving the accuracy of process control.

[0230] The method for manufacturing the semiconductor structure of the present embodiment forms a third semiconductor layer with a larger size on the top surface of the second semiconductor column, and uses the third semiconductor layer as a mask to self-align and etch the initial insulating dielectric layer; when forming the work function layer, the insulating sidewall is used as a mask to self-align and form the work function layer; a second dielectric layer is formed on both sides of the second semiconductor column arranged along the first direction, the word line width is defined by the second dielectric layer, and the word line is formed by self-alignment and limitation through the second dielectric layer; the method for manufacturing the semiconductor structure of the present embodiment optimizes the device structure and the process flow, and uses the structure in the process to perform self-alignment and limitation during the process, thereby reducing the steps of using the photolithography process in the process. The present embodiment has lower requirements on the process, and the process is easier to control, reducing the process steps, saving production costs, and improving the product yield.

[0231] According to an exemplary embodiment, this embodiment includes all the steps of the above embodiment. The difference between this embodiment and the above embodiment is that the method for manufacturing the semiconductor structure of this embodiment further includes the following steps:

[0232] Step S170: forming a capacitor contact portion on the third semiconductor layer, wherein the capacitor contact portion covers a portion of the surface of the third semiconductor layer.

[0233] The material of the capacitor contact portion 90 may include metal silicide. For example, the material of the capacitor contact portion 90 may include at least one of cobalt silicide (CoSi), titanium silicide (TiSi), nickel silicide (NiSi) or tungsten silicide (WSi), but is not limited thereto.

[0234] In this embodiment, the capacitor contact portion 90 is formed on the third semiconductor layer 30, and the following implementation methods may be adopted:

[0235] First, if Fig.46 As shown, refer to Fig.45 , etch the top insulating layer 80, etch the top surface of the top insulating layer 80 to below the third semiconductor layer 30, and etch away the first gate dielectric material layer 411 and the second gate dielectric material layer 412 covering the surface of the third semiconductor layer 30 to expose the surface of the third semiconductor layer 30.

[0236] Then, if Fig.47 , Fig.48 , Fig.49 As shown, refer to Fig.46 , forming a third insulating layer 342, the third insulating layer 342 covers the top surface of the top insulating layer 80 and the third semiconductor layer 30, and the material of the third insulating layer 342 may include at least one of silicon oxide or silicon oxynitride.

[0237] Then, if Fig.51 , Fig.52As shown, second through holes 265 are formed in the third insulating layer 342, and each second through hole 265 penetrates the top insulating layer 80 and exposes at least a portion of the surface of the third semiconductor layer 30. Fig.50 As shown, refer to Fig.47 A photoresist layer 163 may be formed on the top surface of the top insulating layer 80, and a pattern of the second through hole 265 to be formed may be defined in the photoresist layer 163 by a photo irradiation process. The third insulating layer 342 is etched according to the photoresist layer 163 until the top surface covering the third semiconductor layer 30 is exposed, and a second through hole 265 is formed on each third semiconductor layer 30.

[0238] Then, if Fig.53 As shown, refer to Fig.52 , depositing a metal material into the second through hole 265, forming a metal material layer 193 on the top surface of the third semiconductor layer 30, wherein the metal material layer 193 includes at least one of cobalt, titanium, nickel or tungsten. Then, as Fig.54 , Fig.55 As shown, refer to Fig.53 , heat treat the third semiconductor layer 30 and the metal material layer 193 so that the metal atoms of the metal material layer 193 diffuse into the third semiconductor layer 30 to form metal silicide, and then remove the heat-treated metal material layer 193 by etching, and then fill the second through hole 265 with a conductive material to form a capacitor contact portion 90.

[0239] In this embodiment, metal atoms are diffused into the third semiconductor layer 30 to form metal silicide to form a capacitor contact portion 90 on the exposed surface of the third semiconductor layer 30, so that the third semiconductor layer 30 can form an ohmic contact with a device subsequently formed thereon (such as a capacitor) through the capacitor contact portion 90, thereby reducing the contact resistance between the third semiconductor layer 30 and the subsequently formed device, thereby further improving the electrical performance of the semiconductor structure.

[0240] According to an exemplary embodiment, a semiconductor structure is provided in this embodiment, such as Fig.54 , Fig.55 As shown, refer to Figure 2 The semiconductor structure includes an initial structure 10, a plurality of second semiconductor pillars 20, a word line 40, an air layer 70, and a top insulating layer 80. The initial structure 10 includes a plurality of first semiconductor pillars 12, Figure 3 , a plurality of first semiconductor columns 12 are arranged in a plurality of rows along a first direction D1, a plurality of second semiconductor columns 20 are arranged in a plurality of rows along a first direction D1, each second semiconductor column 20 is correspondingly disposed on each first semiconductor column 12 and connected to the first semiconductor column 12, referring to Fig.10As shown, the second semiconductor column 20 includes a first region 21, a second region 22 and a third region 23 sequentially arranged in a direction away from the first semiconductor column 12, the word line 40 extends along the first direction D1, and the word line 40 covers the side wall of the second region 22 of a row of second semiconductor columns 20 arranged along the first direction D1, the air layer 70 extends along the first direction D1, the air layer 70 is arranged between adjacent word lines 40, the top surface of the air layer 70 is lower than the top surface of the word line 40, and the top insulating layer 80 covers the top surface of the word line 40 and fills the space between the word lines 40 located above the air layer 70. In the semiconductor structure of this embodiment, the air layer 70 is arranged between adjacent word lines 40, and the air dielectric constant is relatively low, which can reduce the parasitic capacitance between adjacent word lines 40, avoid the parasitic capacitance between the word lines 40 causing the resistance and capacitance response delay, and is conducive to improving the response speed of the semiconductor structure and improving the electrical performance of the semiconductor structure.

[0241] Reference Figure 3 , Figure 3 , Figure 4 As shown, the initial structure 10 includes a substrate 11, a plurality of first semiconductor pillars 12 disposed on the substrate 11, and an isolation structure 13 filled between the first semiconductor pillars 12. The top surfaces of the first semiconductor pillars 12 and the isolation structure 13 are flush, and the initial structure 10 exposes the top surfaces of the plurality of first semiconductor pillars 12. The plurality of first semiconductor pillars 12 are disposed on the substrate 11 and connected to the substrate 11. The plurality of first semiconductor pillars 12 are arranged in a plurality of columns along a first direction D1. The plurality of columns of first semiconductor pillars 12 are arranged at intervals in a second direction D2. The first semiconductor pillars 12 extend along a third direction perpendicular to the top surface of the substrate 11, wherein the first direction D1 and the second direction D2 are parallel to the top surface of the substrate 11, and the first direction D1 and the second direction D2 are perpendicular. In this embodiment, the first semiconductor pillars 12 in two adjacent columns are arranged in an alternating manner to increase the distance between the first semiconductor pillars 12 in the two adjacent columns, which is conducive to increasing the arrangement density of the first semiconductor pillars 12 and improving the device integration density of the semiconductor structure. It can be understood that in other embodiments, the plurality of first semiconductor pillars 12 may be arranged in a rectangular array along the first direction D1 and the second direction D2.

[0242] In this embodiment, refer to Figure 2 The initial structure 10 further includes a plurality of bit lines 14, which are bent and extended in a curved shape, are arranged in parallel, and each bit line 14 covers a portion of the circumference of a column of first semiconductor pillars 12. A bit line contact layer 15 is arranged between the bit line 14 and the circumference of the first semiconductor pillar 12.

[0243] Reference Fig.54 , Fig.55 As shown, combined Fig.10Each second semiconductor column 20 is disposed on a corresponding first semiconductor column 12, the second semiconductor column 20 is connected to the first semiconductor column 12, the second semiconductor column 20 is arranged according to the arrangement of the first semiconductor column 12, and the second semiconductor column 20 is arranged in a plurality of rows along the first direction D1. The material of the second semiconductor column 20 may include silicon, germanium, or silicon germanium, silicon carbide, gallium arsenide, indium arsenide, indium phosphide or other materials with semiconductor properties, such as III / V group compounds or II / VI group compounds, and the first semiconductor column 12 may be doped with conductive ions.

[0244] Reference Fig.54 , Fig.55 As shown, a word line 40 is arranged above the initial structure 10, each word line 40 extends along the first direction D1 and covers the side wall of the second region 22 of a row of second semiconductor pillars 20 arranged along the first direction D1, and a plurality of word lines 40 are arranged at intervals in a second direction D2 perpendicular to the first direction D1. The word line 40 and the top surface of the initial structure 10 are also arranged separately, for example, other material layers may be arranged between the word line 40 and the top surface of the initial structure 10. The material of the word line 40 may include at least one of indium tin oxide, polysilicon, copper, tungsten, aluminum, copper alloy, titanium, titanium nitride, palladium nitride, and tantalum nitride. In this embodiment, the material of the word line 40 includes tungsten.

[0245] Reference Fig.54 , Fig.55 As shown, the air layer 70 is disposed between two word lines 40 adjacent to each other along the second direction D2, and the air layer 70 extends along the first direction D1, that is, along the second direction D2, the word lines 40 and the air layer 70 are alternately disposed above the initial structure 10. In this embodiment, the top surface of the air layer 70 is lower than the top surface of the word line 40, and the bottom surface of the air layer 70 is higher than the bottom surface of the word line 40, so as to avoid the air layer 70 from extending too large in the third direction between other devices, thereby increasing the risk of short-circuiting other devices in the semiconductor structure.

[0246] In some embodiments, reference Fig.54 , Fig.55 As shown, the semiconductor structure also includes a protective layer 192, which covers the side walls of the word line 40. The word line 40 and the air layer 70 are separated by the protective layer 192. The protective layer 192 is used to prevent the word line 40 from being exposed to the air layer 70, thereby preventing the material in the word line 40 from being oxidized and contaminated by the air, resulting in a decrease in the conductivity of the word line 40, thereby ensuring that the word line 40 has good conductivity.

[0247] In some embodiments, reference Fig.54 , Fig.55As shown, the semiconductor structure further includes a work function layer 50, which covers the sidewalls of the second region 22 of the second semiconductor pillar 20, and the word line 40 and the sidewalls of the second region 22 are connected through the work function layer 50. In this embodiment, the material of the work function layer 50 includes titanium nitride.

[0248] In some embodiments, reference Fig.26 As shown, the semiconductor structure further includes a gate dielectric layer 41 , and the gate dielectric layer 41 is disposed between the work function layer 50 and the sidewall of the second region 22 of the second semiconductor pillar 20 .

[0249] In some embodiments, from the sidewall of the second region 22 of the second semiconductor pillar 20 toward the work function layer 50 , the gate dielectric layer 41 includes a first gate dielectric material layer 411 and a second gate dielectric material layer 412 that are sequentially disposed.

[0250] The material of the first gate dielectric material layer 411 may be selected from at least one of silicon dioxide (SiO2), silicon oxynitride (SiON), silicon nitride, aluminum oxide (Al2O3), and aluminum oxynitride (AlON). In this embodiment, the material of the first gate dielectric material layer 411 includes silicon oxide, and the thickness of the first gate dielectric material layer 411 is 1.2 nm.

[0251] The material of the second gate dielectric material layer 412 is a high-k dielectric material (a dielectric material with a dielectric constant greater than or equal to 3.9). For example, the material of the second gate dielectric material layer 412 may include at least one of aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2), or strontium titanium oxide (SrTiO3). In this embodiment, the material of the second gate dielectric material layer 412 includes hafnium oxide, and the thickness of the second gate dielectric material layer 412 is 1.4 nm.

[0252] In some embodiments, reference Fig.54 , Fig.55 As shown, the semiconductor structure also includes an insulating dielectric layer 60, which is located below the air layer 70. The insulating dielectric layer 60 covers the top surface of the initial structure 10 and the side wall of the first region 21 of the second semiconductor column 20. The word line 40 and the initial structure 10 are separated by the insulating dielectric layer 60 to avoid short circuit between the word line 40 and the devices in the initial structure 10 (such as the bit line 14).

[0253] In this embodiment, the insulating dielectric layer 60 includes a first oxide layer 311 and a first nitride layer 312 sequentially disposed on the top surface of the initial structure 10 . The material of the first oxide layer 311 includes silicon oxide, and the material of the first nitride layer 312 includes silicon nitride.

[0254] In some embodiments, reference Fig.54 , Fig.55 As shown, the semiconductor structure also includes an insulating sidewall 140, which covers the sidewall of the third region 23 of the second semiconductor column 20. The insulating sidewall 140 is used to prevent the word line 40 and the device (such as a capacitor) located above the second semiconductor column 20 from short-circuiting and other problems that affect the performance of the semiconductor structure.

[0255] In some embodiments, the insulating sidewall 140 is an insulating structure in which a nitride layer wraps an oxide layer. The insulating sidewall 140 has better electrical isolation performance. The insulating sidewall 140 includes a third oxide layer 315 covering the side wall of the third region 23, and a first insulating layer 142 and a second nitride layer 314 coated on the outer surface of the third oxide layer 315. The materials of the first insulating layer 142 and the second nitride layer 314 both include nitrides with electrical insulation properties. The first insulating layer 142 and the second nitride layer 314 are connected to each other and jointly coat the third oxide layer 315.

[0256] In some embodiments, reference Fig.54 , Fig.55 As shown, the semiconductor structure further includes a third semiconductor layer 30, which covers the top surface of the second semiconductor column 20, and the projection formed by the second semiconductor column 20 on the initial structure 10 falls within the projection formed by the third semiconductor layer 30 on the initial structure 10. The material of the third semiconductor layer 30 may include polycrystalline silicon doped with conductive ions, and the third semiconductor layer 30 has lower resistance and better conductivity.

[0257] In some embodiments, a capacitor contact portion 90 is disposed on the top surface of the third semiconductor layer 30. The material of the capacitor contact portion 90 includes metal silicide, which is used to form an ohmic contact between the third semiconductor layer 30 and a device (such as a capacitor) disposed thereon, thereby reducing the total resistance of the semiconductor structure.

[0258] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0259] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: The following steps are involved: Providing an initial structure, the initial structure comprising a plurality of first semiconductor pillars, wherein the plurality of first semiconductor pillars are arranged in a plurality of columns along a first direction; forming a plurality of second semiconductor pillars, the plurality of second semiconductor pillars are arranged in a plurality of rows along the first direction, each second semiconductor pillar is correspondingly disposed on each first semiconductor pillar and connected to the first semiconductor pillar, and the second semiconductor pillar comprises a first region, a second region and a third region sequentially disposed in a direction away from the first semiconductor pillar; forming a word line, wherein the word line extends along the first direction, and the word line covers the sidewalls of the second regions of a column of the second semiconductor pillars arranged along the first direction; forming a sacrificial layer, wherein the sacrificial layer extends between adjacent word lines along the first direction, and the sacrificial layer at least fills a portion of the space between adjacent word lines; forming a top insulating layer, wherein the top insulating layer covers the top surface of the sacrificial layer and fills the unfilled space between two adjacent columns of the second semiconductor pillars arranged along the first direction; The sacrificial layer is removed, and an air layer is formed at a position where the sacrificial layer is removed.

2. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The production method further comprises: A work function layer is formed, wherein the work function layer covers the side wall of the second region of the second semiconductor column, and the word line and the side wall of the second region are connected through the work function layer.

3. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The production method further comprises: An insulating sidewall is formed, the insulating sidewall covering the sidewall of the third region of the second semiconductor column.

4. The method for manufacturing a semiconductor structure according to claim 1, characterized in that: The production method further comprises: An insulating dielectric layer is formed, the insulating dielectric layer covers the top surface of the initial structure and the sidewalls of the first region of the second semiconductor column, and the word line and the initial structure are separated by the insulating dielectric layer.

5. The method for manufacturing a semiconductor structure according to any one of claims 1 to 4, characterized in that: forming a plurality of second semiconductor pillars, comprising: forming an initial insulating dielectric layer, wherein the initial insulating dielectric layer covers a top surface of the initial structure; Etching the initial insulating dielectric layer to form a plurality of first through holes corresponding to the first semiconductor pillars in the initial insulating dielectric layer, wherein each of the first through holes exposes at least a portion of a top surface of the corresponding first semiconductor pillar; The second semiconductor pillars are formed in each of the first through holes.

6. The method for manufacturing a semiconductor structure according to claim 5, characterized in that: After forming a plurality of second semiconductor pillars, the method further includes the following steps: A third semiconductor layer is formed, wherein the third semiconductor layer covers a top surface of the second semiconductor column, and a projection of the second semiconductor column on the initial structure falls within a projection of the third semiconductor layer on the initial structure.

7. The method for manufacturing a semiconductor structure according to claim 6, characterized in that: After forming the third semiconductor layer, the method comprises: Using the third semiconductor layer as a mask, the initial insulating dielectric layer is etched to remove a portion of the initial insulating dielectric layer around the third region of the second semiconductor column, and the sidewall of the third region is covered by the initial insulating dielectric layer retained by the etching; forming a first insulating layer, wherein the first insulating layer covers the surface of the initial insulating dielectric layer retained by etching and the top surface of the third semiconductor layer; The first insulating layer is etched to remove the first insulating layer located on the top surface of the third semiconductor layer and the first insulating layer located on the top surface of the initial insulating dielectric layer, the first insulating layer covering the side wall of the third region is etched and retained, and the initial insulating dielectric layer and the first insulating layer covering the side wall of the third region together form an insulating side wall.

8. The method for manufacturing a semiconductor structure according to claim 7, characterized in that: After forming the insulating sidewall, the following steps are performed: forming a first dielectric layer, wherein the first dielectric layer covers the top surface of the initial insulating dielectric layer, the surface of the insulating sidewall and fills the space between the third regions; Etching and removing a portion of the first dielectric layer and a portion of the initial insulating dielectric layer to form a first trench, wherein the first trench extends between two adjacent columns of the second semiconductor pillars along the first direction, and the first trench exposes a portion of the surface of the insulating sidewall; A second dielectric layer is formed in the first trench, the second dielectric layer extends along the first direction, the second dielectric layer and the second semiconductor pillars are alternately arranged along a second direction perpendicular to the first direction, and the top surface of the second dielectric layer is higher than the top surface of the third semiconductor layer.

9. The method for manufacturing a semiconductor structure according to claim 8, characterized in that: After forming a second dielectric layer in the first trench, the method further includes: The first dielectric layer and a portion of the initial insulating dielectric layer are etched away to expose the sidewalls of the second region of the second semiconductor column. The initial insulating dielectric layer below the second dielectric layer is retained to form an insulating dielectric layer, and the insulating dielectric layer covers the sidewalls of the first region of the second semiconductor column.

10. The method for manufacturing a semiconductor structure according to claim 8, characterized in that: After forming the insulating dielectric layer, the method further includes: forming a gate dielectric layer, wherein the gate dielectric layer covers the sidewalls of the second region; forming a work function material layer, wherein the work function material layer covers a surface of the gate dielectric layer; The work function material layer is etched using the insulating sidewall as a mask, and the work function material layer shielded by the insulating sidewall is etched away to form a work function layer.

11. The method for manufacturing a semiconductor structure according to claim 10, characterized in that: Forming a word line, comprising: forming a conductive layer, the conductive layer covering the work function layer and filling unfilled spaces between the second semiconductor pillars; The conductive layer is etched to remove the conductive layer filled between the third regions, and the conductive layer is divided into the word lines extending along the first direction.

12. The method for manufacturing a semiconductor structure according to claim 8, characterized in that: A sacrificial layer is formed, comprising: removing the second dielectric layer to expose the first trench; forming a sacrificial material layer, wherein the sacrificial material layer fills the first trench; The sacrificial material layer is etched until a top surface is lower than a top surface of the word line, so as to form the sacrificial layer in the first trench.

13. The method for manufacturing a semiconductor structure according to claim 12, characterized in that: Before removing the second dielectric layer, the method further includes: A second insulating layer is formed, the second insulating layer filling unfilled spaces between the third regions of the second semiconductor pillars.

14. The method for manufacturing a semiconductor structure according to claim 6, characterized in that: The production method further comprises: A capacitor contact portion is formed on the third semiconductor layer, wherein the capacitor contact portion covers at least a portion of a surface of the third semiconductor layer.

15. The method for manufacturing a semiconductor structure according to claim 14, characterized in that: Forming a capacitor contact, including: forming a metal material layer on the top surface of the third semiconductor layer; thermally treating the third semiconductor layer and the metal material layer; The metal material layer after the heat treatment is removed, and the capacitor contact portion is formed on the third semiconductor layer.

16. A semiconductor structure, characterized in that: include: An initial structure, the initial structure comprising a plurality of first semiconductor pillars, wherein the plurality of first semiconductor pillars are arranged in a plurality of rows along a first direction; A plurality of second semiconductor pillars, wherein the plurality of second semiconductor pillars are arranged in a plurality of rows along the first direction, each second semiconductor pillar is correspondingly disposed on each first semiconductor pillar and connected to the first semiconductor pillar, and the second semiconductor pillar comprises a first region, a second region and a third region sequentially disposed in a direction away from the first semiconductor pillar; A word line extending along the first direction, the word line covering a side wall of the second region of a column of the second semiconductor pillars arranged along the first direction; an air layer, the air layer extending along the first direction, the air layer being arranged between adjacent word lines, and a top surface of the air layer being lower than a top surface of the word line; A top insulating layer covers top surfaces of the word lines and fills spaces between the word lines above the air layer.

17. The semiconductor structure according to claim 16, characterized in that: The semiconductor structure further comprises: A protection layer covers the sidewall of the word line, and the word line and the air layer are separated by the protection layer.

18. The semiconductor structure according to claim 16, characterized in that The semiconductor structure further comprises: A work function layer covers a side wall of the second region of the second semiconductor column, and the word line and the side wall of the second region are connected through the work function layer.

19. The semiconductor structure according to claim 16, characterized in that The semiconductor structure further comprises: an insulating dielectric layer, the insulating dielectric layer being located below the air layer, the insulating dielectric layer covering a top surface of the initial structure and a side wall of the first region of the second semiconductor column, the word line and the initial structure being separated by the insulating dielectric layer; An insulating sidewall covers a sidewall of the third region of the second semiconductor column.

20. The semiconductor structure according to claim 16, wherein: The semiconductor structure further comprises: A third semiconductor layer covers a top surface of the second semiconductor column, and a projection of the second semiconductor column on the initial structure falls within a projection of the third semiconductor layer on the initial structure.

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