Semiconductor phase change memory cell including embedded blade-like heating electrode
By designing an embedded blade-like heating electrode in the phase change memory, it directly acts inside the sulfur compound material layer, solving the problem of high operation power consumption of the phase change memory, achieving higher thermal efficiency and lower power consumption.
Patent Information
- Application Number
- CN202411735400.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-29
- Publication Date
- 2025-03-11
AI Technical Summary
The existing phase change memory consumes a lot of power during operation from crystal to amorphous state, which limits its large-scale application.
A semiconductor phase change memory unit containing an embedded blade-shaped heating electrode is designed. By embedding the heating electrode into the sulfur-based compound material layer, it acts directly inside the material, reducing heat loss and improving thermal efficiency.
This design reduces heat loss during operation, improves heating efficiency, reduces operating power consumption of phase change memory, and improves device stability and reliability.
Smart Images
Figure CN119603975A_ABST
Abstract
Description
Technical Field
[0001] The invention belongs to the field of microelectronics, and in particular relates to a semiconductor phase change memory unit comprising an embedded blade-shaped heating electrode. Background Art
[0002] With the rise of the Internet of Things, artificial intelligence, cloud computing, and 5G technology, human society has entered the era of big data, and information technology-related industries have also ushered in vigorous development, which has put forward higher requirements on the performance of memory. Among them, phase change memory stands out with its advantages of fast storage speed, long life, large switching ratio and compatibility with existing CMOS processes. In phase change memory, the current intensity passing through the heating electrode is controlled by adjusting the electrical operating parameters to regulate the temperature of the sulfur compound material, so that the sulfur compound material undergoes a reversible structural transition between a low-resistance crystalline state and a high-resistance amorphous state, and uses this difference in high and low resistance to store information. Among them, the operating power consumption from the crystalline state to the amorphous state is relatively large, which to a certain extent limits the large-scale application of phase change memory.
[0003] In order to reduce the operating power consumption of phase change memory, the main solutions currently include: developing new sulfur compound materials, reducing the size of the bottom electrode or adopting a restrictive structure to reduce the phase change area, etc. In recent years, with the rapid development of the integrated circuit industry and semiconductor process technology, more possibilities have been proposed for the low-power development of phase change memory. The present invention proposes an embedded blade-shaped heating electrode to concentrate heat inside the sulfur compound material. Through this storage unit structure, the heat loss during operation can be reduced, the heating efficiency can be improved, the device reliability can be improved, and ultimately the operating power consumption of the phase change memory can be reduced. Summary of the invention
[0004] The technical problem to be solved by the present invention is to provide a semiconductor phase change memory unit including an embedded blade-shaped heating electrode and a preparation method thereof, so as to achieve higher thermal efficiency, lower operating energy consumption and smaller device loss.
[0005] The present invention provides a semiconductor phase change memory unit including an embedded blade-shaped heating electrode, comprising a bottom contact circuit, a heating electrode, a barrier layer, a sulfur compound material layer, a hard mask, a top electrode and an insulating dielectric layer; the upper part of the sulfur compound material layer is electrically connected to the top electrode through the hard mask; the heating electrode is a blade-shaped structure, the top of which is embedded in the sulfur compound material layer and connected to the sulfur compound material layer, and the bottom of which is connected to the bottom contact circuit.
[0006] Preferably, the insulating dielectric layer includes a first insulating dielectric layer, a second insulating dielectric layer, a third insulating dielectric layer, a fourth insulating dielectric layer and a fifth insulating dielectric layer.
[0007] Preferably, the first insulating dielectric layer is located on the surface of the bottom contact circuit; the second insulating dielectric layer is located on the surface of the first insulating dielectric layer and is located at the periphery of the heating electrode; the barrier layer is located at the periphery of the heating electrode; the third insulating dielectric layer is located at the periphery of the barrier layer, and its lower part is in contact with the bottom contact circuit, and its upper part is in contact with the sulfur-based compound material layer; the fourth insulating dielectric layer is located at the periphery of the hard mask and the sulfur-based compound material layer; and the fifth insulating dielectric layer is located at the periphery of the fourth insulating dielectric layer.
[0008] Preferably, the bottom contact circuit is provided with a semiconductor device, a metal interconnection structure and an isolation structure.
[0009] The present invention also provides a method for preparing the semiconductor phase change memory unit including the embedded blade-shaped heating electrode, comprising the following steps:
[0010] S1: Provides bottom contact circuit;
[0011] S2: depositing a first insulating dielectric layer on the surface of the bottom contact circuit;
[0012] S3: forming a groove above the bottom contact circuit by etching the first insulating dielectric layer, and forming a second insulating dielectric layer on the side wall of the first insulating dielectric layer in the groove;
[0013] S4: forming a heating electrode on the surface of the second insulating dielectric layer; then forming a barrier layer on the surface of the heating electrode, and separating the heating electrode and the barrier layer at the bottom of the groove;
[0014] S5: forming a third insulating dielectric layer on the barrier layer, exposing the top of the blade-shaped heating electrode by chemical mechanical polishing, and making the blade-shaped heating electrode higher than the first insulating dielectric layer and the third insulating dielectric layer by plasma etching;
[0015] S6: depositing a chalcogenide compound material layer and a hard mask on top of the heating electrode, so that the heating electrode is embedded in the chalcogenide compound material layer and connected thereto;
[0016] S7: etching the chalcogenide material layer and the hard mask, and depositing a fourth insulating dielectric layer on the periphery; and then depositing a fifth insulating dielectric layer on the fourth insulating dielectric layer;
[0017] S8: forming a loop contact hole on the fourth insulating dielectric layer and the fifth insulating dielectric layer, and penetrating the fourth insulating dielectric layer and the fifth insulating dielectric layer;
[0018] S9: depositing a top electrode in the loop contact hole as a contact electrode connected to an external circuit, and forming independent memory cells after a patterning process.
[0019] Preferably, the preparation method of the heating electrode layer comprises atomic layer deposition; the material of the heating electrode layer includes but is not limited to any one of Ti, W, Ta, Cu, WCN, WN, TiN, TiSiN and TaN.
[0020] Preferably, the preparation methods of the first insulating dielectric layer, the second insulating dielectric layer, the barrier layer, the third insulating dielectric layer, the fourth insulating dielectric layer and the fifth insulating dielectric layer include but are not limited to chemical vapor deposition; the materials of the insulating dielectric layer and the barrier layer include any one of silicon nitride, silicon oxide or silicon oxynitride.
[0021] Preferably, the preparation method of the sulfur-based compound material layer comprises physical vapor deposition; the material of the sulfur-based compound material layer comprises any one of GeTe-Sb2Te3 system, GeTe-SnTe system, Sb2Te system, In3SbTe2 system or GeTe-Sb2Te3 system, GeTe-SnTe system, Sb2Te system, In3SbTe2 system containing doping elements; wherein the doping element comprises at least one of Sc, Ag, In, Al, C, S, Se, N, Cu or W.
[0022] Preferably, the preparation method of the hard mask comprises physical vapor deposition; the material of the hard mask comprises any one of Ti, W, Ta, Cu, WCN, WN, TiN or TaN.
[0023] Preferably, the preparation method of the top electrode includes but is not limited to chemical vapor deposition; the material of the top electrode includes but is not limited to any one of Ti, W, Ta, Cu, WCN, WN, TiN and TaN.
[0024] Beneficial Effects
[0025] (1) The semiconductor phase change memory unit device of the present invention embeds an "L"-shaped blade-shaped heating electrode into the sulfide compound material layer, so that the operating current directly acts on the inside of the sulfide compound material layer, which can reduce heat loss during operation, improve thermal efficiency, and thus reduce operating power consumption;
[0026] (2) The present invention can limit the effective structural phase change region within the sulfide compound material layer, thereby reducing the thermal disturbance and atomic migration at the interface between the sulfide compound material layer and the dielectric layer, and improving the stability of the phase change memory device;
[0027] (3) The preparation process of the present invention is simple and the production cost is low. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] Figure 1Schematic diagram of the structure of a semiconductor phase change memory with an embedded blade-shaped heating electrode in Embodiment 1 of the present invention.
[0029] Figure 2 Graph showing the internal temperature distribution of the semiconductor phase change memory with blade-shaped heating electrodes of different embedding depths in Embodiment 1 of the present invention.
[0030] Figure 3 Schematic diagram of the preparation process of the semiconductor phase change memory containing embedded blade-shaped heating electrodes in Example 1 of the present invention.
[0031] Figure 4 Schematic diagram of the structure of the bottom contact circuit in Example 1 of the present invention.
[0032] Figure 5 It is a schematic diagram of the structure after the first insulating dielectric layer is deposited in Example 1 of the present invention.
[0033] Figure 6 It is a schematic diagram of the structure after the grooves are formed by etching in Example 1 of the present invention.
[0034] Figure 7 It is a schematic diagram of the structure after depositing the second insulating dielectric layer in Example 1 of the present invention.
[0035] Figure 8 It is a schematic diagram of the structure of only retaining the second insulating dielectric layer on the side wall of the groove in Embodiment 1 of the present invention.
[0036] Fig. 9 It is a schematic diagram of the structure after the heating electrode is formed in Example 1 of the present invention.
[0037] Fig.10 It is a schematic diagram of the structure after forming a barrier layer in Example 1 of the present invention.
[0038] Fig.11 This is a schematic diagram of the structure after the heating electrode and the barrier layer at the bottom of the groove are separated in Example 1 of the present invention.
[0039] Fig.12 It is a schematic diagram of the structure after the third insulating dielectric layer is deposited in Example 1 of the present invention.
[0040] Fig.13 It is a schematic diagram of the structure after the top of the blade-shaped heating electrode is exposed in Example 1 of the present invention.
[0041] Fig.14 It is a schematic diagram of the structure after the sulfur compound material layer and the hard mask are deposited in Example 1 of the present invention.
[0042] Fig.15 It is a schematic diagram of the structure after etching the sulfur compound material layer and the hard mask in Example 1 of the present invention.
[0043] Fig.16 It is a schematic diagram of the structure after depositing the fourth insulating dielectric layer and the fifth insulating dielectric layer in Example 1 of the present invention.
[0044] Fig.17 It is a schematic diagram of the structure after the loop contact hole is formed in Example 1 of the present invention.
[0045] Figure numerals: 01-bottom contact circuit, 02-first insulating dielectric layer, 03-second insulating dielectric layer, 04-heating electrode, 05-blocking layer, 06-third insulating dielectric layer, 07-sulfur compound material layer, 08-hard mask, 09-fourth insulating dielectric layer, 10-fifth insulating dielectric layer, 11-top electrode. DETAILED DESCRIPTION
[0046] The present invention will be further described below in conjunction with specific embodiments. It should be understood that these embodiments are only used to illustrate the present invention and are not intended to limit the scope of the present invention. In addition, it should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms fall within the scope limited by the appended claims of the application equally.
[0047] Example
[0048] This embodiment provides a semiconductor phase change memory unit including an embedded blade-shaped heating electrode, the structure of which is as follows: Figure 1 As shown, the semiconductor phase change memory unit includes: a bottom contact circuit 01, a heating electrode 04, a barrier layer 05, a sulfur compound material layer 07, a hard mask 08, a top electrode 11 and an insulating dielectric layer; the upper part of the sulfur compound material layer 07 is electrically connected to the top electrode 11 through the hard mask 08; the heating electrode 04 is a blade-shaped structure, the top of which is embedded in the sulfur compound material layer 07 and connected to the sulfur compound material layer 07, and the bottom of which is connected to the bottom contact circuit 01.
[0049] The insulating dielectric layer includes a first insulating dielectric layer 02 , a second insulating dielectric layer 03 , a barrier layer 05 , a third insulating dielectric layer 06 , a fourth insulating dielectric layer 09 and a fifth insulating dielectric layer 10 .
[0050] The first insulating dielectric layer 02 is located on the surface of the bottom contact circuit 01; the second insulating dielectric layer 03 is located on the surface of the first insulating dielectric layer 02 and is located at the periphery of the heating electrode 04; the barrier layer 05 is located at the periphery of the heating electrode 04; the third insulating dielectric layer 06 is located at the periphery of the barrier layer 05, and its lower part is in contact with the bottom contact circuit 01, and its upper part is in contact with the sulfur-based compound material layer 07; the fourth insulating dielectric layer 09 is located at the periphery of the hard mask 08 and the sulfur-based compound material layer 07; the fifth insulating dielectric layer 10 is located at the periphery of the fourth insulating dielectric layer 09; the blade-shaped heating electrode 04 of each unit is isolated by the first insulating dielectric layer 02 and the third insulating dielectric layer 06; the sulfur-based compound material layer 07 and the hard mask 08 of each unit are isolated by the fourth insulating dielectric layer 09 and the fifth insulating dielectric layer 10. In this embodiment, the material of the first insulating dielectric layer 02, the third insulating dielectric layer 06 and the fifth insulating dielectric layer 10 is silicon dioxide, the material of the second insulating dielectric layer 03, the fourth insulating dielectric layer 09 and the barrier layer 05 is silicon nitride, the material of the heating electrode 04 is TaN, and the material of the sulfur-based compound material layer 07 is Ge2Sb2Te5.
[0051] Figure 2 The results of the temperature distribution inside the device of the blade-shaped heating electrode with different embedding depths according to the embodiment of the present invention are exemplified. The thermal simulation model includes a 5nm wide blade-shaped heating electrode and a 100nm thick sulfur compound material layer, and simulates the temperature distribution of the blade-shaped heating electrode at the embedding depths of 0nm, 10nm, 20nm, 30nm, 40nm, 50nm, 60nm and 70nm under the same operating current. When the embedding depth of the blade-shaped heating electrode is 40nm, the highest temperature in the sulfur compound material layer is 390K higher than when the heating electrode is not embedded, indicating that the embedded blade-shaped heating electrode phase change memory structure of the present invention can achieve higher heating efficiency. With the increase of embedding depth, the heat concentration area inside the sulfur compound material layer is far away from the bottom interface, which helps to improve the interface stability and thus improve the device reliability.
[0052] This embodiment provides a method for preparing the semiconductor phase change memory unit including the embedded blade-shaped heating electrode, comprising the following steps:
[0053] S1: Provide bottom contact circuit 01, such as Figure 4 As shown;
[0054] S2: Depositing a first insulating dielectric layer 02 on the surface of the bottom contact circuit 01 by a chemical vapor deposition method, such as Figure 5 As shown;
[0055] S3: Expose and etch the first insulating dielectric layer 02 by photolithography technology to form a groove above the bottom contact circuit 01, such as Figure 6 As shown; forming a second insulating dielectric layer 03 on the surface of the groove and the first insulating dielectric layer 02, such as Figure 7 As shown; the second insulating dielectric layer 03 is retained only on the side wall of the groove by etching back technology, such as Figure 8 As shown;
[0056] S4: forming a heating electrode 04 on the surface of the second insulating dielectric layer 03, such as Fig. 9 As shown; then a barrier layer 05 is formed on the surface of the heating electrode 04, as Fig.10 and exposing and etching the heating electrode 04 and the barrier layer 05 at the bottom of the groove by photolithography technology, as shown in FIG. Fig.11 As shown;
[0057] S5: forming a third insulating dielectric layer 06 on the barrier layer 05 by chemical vapor deposition, such as Fig.12 As shown; the top of the blade-shaped heating electrode 04 is exposed by chemical mechanical polishing, and the blade-shaped heating electrode 04 is made higher than the first insulating dielectric layer 02 and the third insulating dielectric layer 06 by plasma etching, as shown Fig.13 As shown;
[0058] S6: On top of the heating electrode 04, a sulfur compound material layer 07 and a hard mask 08 are formed by a physical vapor deposition method, so that the heating electrode 04 is embedded in the sulfur compound material layer 07 and connected thereto, such as Fig.14 As shown;
[0059] S7: Expose and etch the chalcogenide material layer 07 and the hard mask 08 by photolithography technology, such as Fig.15 As shown, a fourth insulating dielectric layer 09 is formed by chemical vapor deposition on the periphery of the chalcogenide material layer 07 and the hard mask 08, and then a fifth insulating dielectric layer 10 is deposited on the fourth insulating dielectric layer 09. Fig.16 As shown;
[0060] S8: Expose and etch by photolithography technology to form a loop contact hole on the fourth insulating dielectric layer 09 and the fifth insulating dielectric layer 10, and penetrate the fourth insulating dielectric layer 09 and the fifth insulating dielectric layer 10, such as Fig.17 As shown;
[0061] S9: In the loop contact hole, a top electrode 11 is deposited by chemical vapor deposition as a contact electrode connected to an external circuit, and after a patterning process, independent memory cells are formed and connected to subsequent metal interconnection lines, such as Figure 1 shown.
Claims
1. A semiconductor phase change memory cell comprising an embedded blade-shaped heating electrode, characterized in that: The invention comprises a bottom contact circuit (01), a heating electrode (04), a barrier layer (05), a sulfur compound material layer (07), a hard mask (08), a top electrode (11) and an insulating dielectric layer; the upper part of the sulfur compound material layer (07) is electrically connected to the top electrode (11) through the hard mask (08); the heating electrode (04) is a blade-shaped structure, the top of which is embedded in the sulfur compound material layer (07) and connected to the sulfur compound material layer (07), and the bottom of which is connected to the bottom contact circuit (01).
2. The semiconductor phase change memory unit comprising an embedded blade-shaped heating electrode according to claim 1, characterized in that: The insulating dielectric layer comprises a first insulating dielectric layer (02), a second insulating dielectric layer (03), a third insulating dielectric layer (06), a fourth insulating dielectric layer (09) and a fifth insulating dielectric layer (10).
3. The semiconductor phase change memory unit comprising an embedded blade-shaped heating electrode according to claim 2, characterized in that: The first insulating dielectric layer (02) is located on the surface of the bottom contact circuit (01); the second insulating dielectric layer (03) is located on the surface of the first insulating dielectric layer (02) and is located at the periphery of the heating electrode (04); the barrier layer (05) is located at the periphery of the heating electrode (04); the third insulating dielectric layer (06) is located at the periphery of the barrier layer (05), and its lower part is in contact with the bottom contact circuit (01), and its upper part is in contact with the sulfur-based compound material layer (07); the fourth insulating dielectric layer (09) is located at the periphery of the hard mask (08) and the sulfur-based compound material layer (07); and the fifth insulating dielectric layer (10) is located at the periphery of the fourth insulating dielectric layer (09).
4. The semiconductor phase change memory unit comprising an embedded blade-shaped heating electrode according to claim 1, characterized in that: The bottom contact circuit (01) is provided with a semiconductor device, a metal interconnection structure and an isolation structure.
5. A method for preparing a semiconductor phase change memory unit comprising an embedded blade-shaped heating electrode as claimed in any one of claims 1 to 4, comprising the following steps: S1: Provides bottom contact circuit (01); S2: depositing a first insulating dielectric layer (02) on the surface of the bottom contact circuit (01); S3: forming a groove above the bottom contact circuit (01) by etching the first insulating dielectric layer (02), and forming a second insulating dielectric layer (03) on the side wall of the first insulating dielectric layer (02) in the groove; S4: forming a heating electrode (04) on the surface of the second insulating dielectric layer (03); then forming a barrier layer (05) on the surface of the heating electrode (04), and separating the heating electrode (04) and the barrier layer (05) at the bottom of the groove; S5: forming a third insulating dielectric layer (06) on the barrier layer (05), exposing the top of the blade-shaped heating electrode (04) by chemical mechanical polishing, and making the blade-shaped heating electrode (04) higher than the first insulating dielectric layer 02 and the third insulating dielectric layer (06) by plasma etching; S6: depositing a sulfur-based compound material layer (07) and a hard mask (08) on the top of the heating electrode (04), so that the heating electrode (04) is embedded in the sulfur-based compound material layer (07) and connected thereto; S7: etching the chalcogenide material layer (07) and the hard mask (08), and depositing a fourth insulating dielectric layer (09) on the periphery; and then depositing a fifth insulating dielectric layer (10) on the fourth insulating dielectric layer (09); S8: forming a loop contact hole on the fourth insulating dielectric layer (09) and the fifth insulating dielectric layer (10), and penetrating the fourth insulating dielectric layer (09) and the fifth insulating dielectric layer (10); S9: depositing a top electrode (11) in the loop contact hole as a contact electrode connected to an external circuit, and forming independent memory cells after a patterning process.
6. The preparation method according to claim 5, characterized in that: The preparation method of the heating electrode (04) in step S4 comprises atomic layer deposition; the material of the heating electrode (04) comprises any one of Ti, W, Ta, Cu, WCN, WN, TiN, TiSiN and TaN.
7. The preparation method according to claim 5, characterized in that: The preparation method of the first insulating dielectric layer (02), the second insulating dielectric layer (03), the barrier layer (05), the third insulating dielectric layer (06), the fourth insulating dielectric layer (09) and the fifth insulating dielectric layer (10) comprises chemical vapor deposition; the material of the insulating dielectric layer and the barrier layer (05) comprises any one of silicon nitride, silicon oxide or silicon oxynitride.
8. The preparation method according to claim 5, characterized in that: The preparation method of the sulfur-based compound material layer (07) comprises physical vapor deposition; the material of the sulfur-based compound material layer (07) comprises any one of a GeTe-Sb2Te3 system, a GeTe-SnTe system, a Sb2Te system, an In3SbTe2 system or a GeTe-Sb2Te3 system, a GeTe-SnTe system, a Sb2Te system, an In3SbTe2 system containing doping elements; wherein the doping element comprises at least one of Sc, Ag, In, Al, C, S, Se, N, Cu or W.
9. The preparation method according to claim 5, characterized in that: The preparation method of the hard mask (08) comprises physical vapor deposition; the material of the hard mask (08) comprises any one of Ti, W, Ta, Cu, WCN, WN, TiN or TaN.
10. The preparation method according to claim 5, characterized in that: The preparation method of the top electrode (11) comprises chemical vapor deposition; the material of the top electrode (11) comprises any one of Ti, W, Ta, Cu, WCN, WN, TiN and TaN.