Input signal acquisition board card and signal processing method thereof

Abstract

The invention discloses an input signal acquisition board card and a signal processing method thereof. The input signal acquisition board card comprises a main system input board card, a standby system input board card and an internal output control module, and the main system input board card and the standby system input board card are in redundant connection; the main system input board card comprises a main system main control chip and a plurality of main system units; the main system units are in redundant connection; the standby input board card comprises a standby main control chip and a plurality of standby units; the standby units are in redundant connection; each main system unit and each standby system unit respectively comprise a signal input circuit, a self-checking circuit and a signal acquisition circuit, the self-checking circuit of each unit is connected to the input end of the signal input circuit of the corresponding unit, and the signal input circuit of each unit is connected with the signal acquisition circuit of the corresponding unit; and the internal output control module is respectively connected with the signal input circuit and the self-checking circuit of each unit.

Description

Technical Field

[0001] The present invention relates to the technical field of acquisition boards, and in particular to an input signal acquisition board and a signal processing method thereof. Background Art

[0002] On EMU trains, input and output modules have the largest number of devices, which are distributed in the electrical cabinet of each carriage. They are mainly responsible for the transmission and control of instructions between the train control network system and non-intelligent devices on the vehicle. The control and signal acquisition in the subsystems in the vehicle are aggregated to the electrical cabinet of each carriage through hard wires, and then the mutual communication with the EMU network backbone is completed through the input and output modules. The input and output modules are composed of control boards, communication boards, input boards, output boards and other boards.

[0003] Currently, the circuits used by input boards are mostly fixed-level input acquisition or fixed-frequency single dynamic pulse sequence acquisition methods. The defects of fixed-level input acquisition are: 1) When electromagnetic interference is introduced from the external environment, the fixed-level signal will fluctuate, causing the input system to acquire the wrong level signal; 2) When the acquisition hardware circuit fails, such as the signal line short circuit or open circuit, the system cannot detect and eliminate the fault in time. Summary of the invention

[0004] In view of the problems in the prior art, an embodiment of the present invention provides an input signal acquisition board and a signal processing method thereof, which can ensure the validity of the input signal and quickly and accurately locate the fault type.

[0005] An embodiment of the present invention provides an input signal acquisition board, comprising a main system input board, a backup system input board, and an internal output control module, wherein the main system input board and the backup system input board are redundantly connected;

[0006] The main system input board includes a main system main control chip and a plurality of main system units; each main system unit is redundantly connected;

[0007] The backup system input board includes a backup system main control chip and a plurality of backup system units; each backup system unit is redundantly connected;

[0008] Each main system unit and each standby system unit includes a signal input circuit, a self-test circuit, and a signal acquisition circuit. The self-test circuit of each unit is connected to the input end of the signal input circuit of the corresponding unit, and the signal input circuit of each unit is connected to the signal acquisition circuit of the corresponding unit.

[0009] The internal output control module is respectively connected to the signal input circuit and the self-test circuit of each unit;

[0010] The signal input circuit of each unit is respectively connected to the input terminal of the input signal acquisition board;

[0011] The signal acquisition circuit of each main system unit is respectively connected to the main system main control chip;

[0012] The signal acquisition circuit of each standby system unit is respectively connected to the standby system main control chip;

[0013] The main control chip of the main system and the main control chip of the standby system are respectively connected to the output end of the input signal acquisition board.

[0014] In one embodiment, the main system input board includes a main system unit 1 and a main system unit 2. The main system unit 1 includes a first signal input circuit, a first self-test circuit, and a first signal acquisition circuit; the main system unit 2 includes a second signal input circuit, a second self-test circuit, and a second signal acquisition circuit.

[0015] In one embodiment, the first self-test circuit includes a first diode and a first photocoupler, the first input end of the first photocoupler is connected to the internal output control module, the second input end of the first photocoupler receives an onboard level signal, the first output end of the first photocoupler is grounded, the second output end of the first photocoupler is connected to the anode of the first diode, and the cathode of the first diode is connected to the first signal input circuit.

[0016] In one embodiment, the first signal input circuit includes a second diode, a first voltage regulator diode, a first resistor, a second voltage regulator diode, a switch tube, a second photocoupler, a second resistor, and a third resistor. The anode of the second diode receives the input signal to be sampled, the cathode of the second diode is connected to the first end of the first resistor, the second end of the first resistor is connected to the first end of the switch tube, the second end of the switch tube is connected to the internal output control module, the third end of the switch tube is connected to the anode of the second voltage regulator diode, and the cathode of the second voltage regulator diode outputs the signal to be sampled; the second photocoupler is a common structure of the first signal input circuit and the first signal acquisition circuit, the first input end of the second photocoupler is connected to the first end of the third resistor, the second end of the third resistor is connected to the cathode of the first voltage regulator diode, the anode of the first voltage regulator diode is connected to the first end of the first resistor, the second input end of the second photocoupler receives the onboard level signal, the first output end of the second photocoupler is connected to the first end of the second resistor, the second end of the second resistor is connected to the first end of the switch tube, and the second output end of the second photocoupler is connected to the first signal acquisition circuit.

[0017] In one embodiment, the first signal acquisition circuit includes a fourth resistor and a fifth resistor, the second output end of the second photoelectric coupler is connected to the first end of the fourth resistor, the second end of the fourth resistor is connected to the main system main control chip, the first end of the fifth resistor is connected to the main system main control chip, and the second end of the fifth resistor is grounded.

[0018] In one embodiment, the standby system input board includes a standby system unit 1 and a standby system unit 2; the standby system unit 1 includes a third signal input circuit, a third self-test circuit, and a third signal acquisition circuit; the standby system unit 2 includes a fourth signal input circuit, a fourth self-test circuit, and a fourth signal acquisition circuit.

[0019] In one embodiment, the main system input board and the standby system input board are isolated from each other and are powered independently.

[0020] In one embodiment, the units of the main system input board and the standby system input board are isolated from each other and are powered independently.

[0021] In one embodiment, each operation cycle of the input signal acquisition board includes a self-test cycle and a sampling cycle; during the self-test cycle, the input signal acquisition board performs hardware self-test; during the sampling cycle, the input signal acquisition board performs signal acquisition.

[0022] In one embodiment, the internal output control module controls the opening and closing of the switch tube connected in series with the self-test circuit signal source of each unit at a preset frequency and duty cycle in each sampling cycle, so that the level of the self-test circuit of each unit jumps between high and low levels, and the self-test signal and the signal to be sampled are collected by the signal acquisition circuit of each unit in the same way.

[0023] In one embodiment, when the switch tube of the self-test circuit of each unit is turned on and the level is high, the self-test circuit of each unit is used to detect whether there is a circuit breakage in each unit; when the switch tube of the self-test circuit of each unit is turned off and the level is low, the self-test circuit of each unit is used to detect whether there is a short circuit in each unit.

[0024] In one embodiment, the main system input board, the standby system input board, and the internal output control module all use TMS5701227 chips.

[0025] An embodiment of the present invention further provides a signal processing method for the input signal acquisition board as described in any one of the above items, the signal processing method comprising:

[0026] The main control chip of the main system receives the self-test signal of the self-test circuit of each main system unit to perform signal voting and determine whether the main system input board card has passed the self-test;

[0027] If the main control chip of the main system determines that the self-test of the main system input board card has passed, a signal vote is performed on the to-be-sampled signal of the corresponding signal input circuit collected by the signal collection circuit of each main system unit;

[0028] If the vote is passed, the output signal value of the main system input board will be output; otherwise, a main system input board failure will be reported.

[0029] In one embodiment, if the main system main control chip determines that the main system input board card fails the self-test, it reports that the main system input board card fails.

[0030] In one embodiment, when a fault is reported in the main system input board, the main control chip of the standby system determines whether the standby system input board has passed self-test;

[0031] If the standby system input board passes the self-test, a signal vote is performed on the signal to be sampled of the corresponding signal input circuit collected by the signal acquisition circuit of each standby system unit; if the vote passes, the output signal value of the standby system input board is output, otherwise the standby system input board fault is reported.

[0032] In one embodiment, if the standby system input board fails the self-test, a standby system input board failure is reported.

[0033] In one embodiment, when both the main system input board and the standby system input board work normally, the output signal value of the main system input board is output.

[0034] An embodiment of the present invention provides an input signal acquisition board and a signal processing method thereof. The present invention proposes a hardware self-checking scheme for the entire process from input signal acquisition to recording, to ensure the validity of the input signal, and to quickly and accurately locate the fault type. The present invention also proposes a hot standby redundant, dual-path decision-making input signal acquisition board architecture. Both the main system input board and the backup system input board perform dual-path voting, and the main system input board and the backup system input board serve as hot standby for each other, greatly improving the availability and reliability of the input signal acquisition board. The input signal acquisition board of the present invention can ensure the normal operation of basic functions without causing functional failure after a failure occurs in either the main system input board or the backup system input board. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the prior art descriptions. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0036] Figure 1 This is a schematic diagram of the structure of an input signal acquisition board in an embodiment of the present invention;

[0037] Figure 2 A schematic diagram of a self-test circuit of an input signal acquisition board in an embodiment of the present invention;

[0038] Figure 3 A schematic diagram of a signal input circuit and a signal acquisition circuit of an input signal acquisition board in an embodiment of the present invention;

[0039] Figure 4 A schematic diagram of a self-test circuit, a signal input circuit, and a signal acquisition circuit of an input signal acquisition board in an embodiment of the present invention;

[0040] Figure 5 A timing diagram of a self-test signal and a sampling signal of an input signal acquisition board in an embodiment of the present invention;

[0041] Figure 6 This is a schematic flow chart of a signal processing method of an input signal acquisition board in an embodiment of the present invention;

[0042] Figure 7 The present invention is a flowchart of another signal processing method of an input signal acquisition board in an embodiment of the present invention. DETAILED DESCRIPTION

[0043] To make the purpose, technical solution and advantages of the embodiments of the present invention more clear, the embodiments of the present invention are further described in detail below in conjunction with the accompanying drawings. Here, the exemplary embodiments of the present invention and their descriptions are used to explain the present invention, but are not intended to limit the present invention.

[0044] In order to facilitate understanding of the technical solution provided by this application, the research background of the technical solution of this application is briefly described below.

[0045] During the operation of the train, a considerable number of signal quantities and their key functions, such as emergency braking, door lock status, cab activation, traction cut-off instructions, etc., require more reliable signal input boards to control. Existing input boards cannot ensure the safety and reliability of signals. Without sufficient safety margin and redundancy, signal errors or confusion will lead to incorrect operation of train control and cause major safety accidents.

[0046] To solve the above technical problems, Figure 1As shown, an embodiment of the present invention provides an input signal acquisition board, which includes a main system input board 19, a backup system input board 20, and an internal output control module 21. The main system input board 19 and the backup system input board 20 are redundantly connected; after the sampled signal is connected to the input signal acquisition board through the wiring terminal, it passes through the anti-reverse connection diode and then is shunted through the resistance circuit to enter the main system input board 19 and the backup system input board 20 respectively.

[0047] The main system input board 19 includes a main system main control chip 17 and several main system units (at least two, such as main system unit 13 and main system unit 2 14); each main system unit is redundantly connected; the main system main control chip 17 is used to perform signal voting on each main system unit and determine the output signal value of the main system input board 19.

[0048] The standby system input board 20 includes a standby system main control chip 18 and a plurality of standby system units (at least two, such as a standby system unit 15 and a standby system unit 2 16 ); each standby system unit is redundantly connected; the standby system main control chip 18 is used to perform signal voting on each standby system unit and determine the output signal value of the standby system input board 20 .

[0049] The signal to be sampled enters the signal acquisition circuit of each unit of the main system input board 19 and the standby system input board 20 at the same time, and is recorded by the main control chip of each system input board. The main control chip of each system input board simultaneously votes on the read signal value. The signal is valid if and only if the signal values ​​read by the two are consistent. If they are inconsistent, a fault is reported. Specifically, the signal is valid if the signal jump situation is consistent within the preset operation cycle.

[0050] Each main system unit and each backup system unit includes a signal input circuit, a self-test circuit, and a signal acquisition circuit. The self-test circuit of each unit is connected to the input end of the signal input circuit of the corresponding unit, and the signal input circuit of each unit is connected to the signal acquisition circuit of the corresponding unit.

[0051] The input signal acquisition board performs signal voting on the self-test circuit self-test signals collected by the signal acquisition circuits of each unit through the main control chips of each system to realize the hardware self-test function.

[0052] The input signal acquisition board performs signal voting on the to-be-sampled signals of the signal input circuits acquired by the signal acquisition circuits of each unit through the main control chips of each system to realize the signal acquisition function.

[0053] The internal output control module 21 is respectively connected to the signal input circuit and self-test circuit of each unit; the internal output control module 21 periodically sends control signals to the self-test circuit and signal input circuit of each unit to realize hardware self-test function and signal acquisition function.

[0054] The signal input circuit of each unit is connected to the input end of the input signal acquisition board card respectively.

[0055] The signal acquisition circuit of each main system unit is connected to the main system main control chip 17 respectively.

[0056] The signal acquisition circuit of each standby system unit is connected to the standby system main control chip 18 respectively.

[0057] The main control chip 17 of the main system and the main control chip 18 of the standby system are respectively connected to the output end of the input signal acquisition board.

[0058] Specifically, Figure 1 and Figure 2 As shown, the internal output control module 21 sends an output control signal A to the self-test circuit, such as Figure 1 and Figure 3 As shown, the internal output control module 21 sends an output control signal B to the signal input circuit. After the main control chip of each input board receives the self-test signal of the self-test circuit (the self-test signal is the signal in the photoelectric coupler in the self-test circuit), it compares whether the jump condition of the collected signal is consistent with the preset condition. If it is consistent, the self-test is successful and the hardware function is normal, otherwise it reports a fault.

[0059] In one embodiment, the present invention uses at least two input boards to form a redundant architecture, one of which is set as the main input board 19, and the other input boards are set as the standby input board 20. The input boards of each system can adopt the same specifications or different specifications, and each circuit of each board adopts the same design. A main control chip and several units (each input board has at least two units to form a redundant architecture) are provided in the main input board 19 and the standby input board 20, and each unit is redundantly connected. The main control chip is used to determine whether there is a hardware fault and determine the output signal value. Each unit includes a signal input circuit, a self-test circuit, and a signal acquisition circuit. The input signal acquisition board performs signal voting on the self-test circuit self-test signal collected by the signal acquisition circuit of each unit through the main control chip of each system to realize the hardware self-test function; the input signal acquisition board performs signal voting on the signal input circuit to be sampled collected by the signal acquisition circuit of each unit through the main control chip of each system to realize the signal acquisition function. Compared with the prior art, the input signal acquisition board of the present invention has a self-checking function on the basis of a dual redundant architecture, which greatly improves the availability and reliability of the input signal acquisition board.

[0060] In one embodiment, Figure 1As shown, the main system input board 19 includes a main system unit 13 and a main system unit 14. The main system unit 14 includes a first signal input circuit 1, a first self-test circuit 2, and a first signal acquisition circuit 3; the main system unit 14 includes a second signal input circuit 4, a second self-test circuit 5, and a second signal acquisition circuit 6; the first self-test circuit 2 is connected to the input end of the first signal input circuit 1, and the first signal input circuit 1 is connected to the first signal acquisition circuit 3; the second self-test circuit 5 is connected to the input end of the second signal input circuit 4, and the second signal input circuit 4 is connected to the second signal acquisition circuit 6.

[0061] Specifically, taking the case where the main system input board 19 includes two main system units (main system unit 1 13 and main system unit 2 14) as an example, when there are three or more main system units in the main system input board 19, the same circuit structure design is also adopted. The circuits of each unit of the main system input board and the standby system input board can adopt the same design concept.

[0062] like Figure 1 and Figure 4 As shown, taking the main system unit 14 in the main system input board 19 of the input signal acquisition board as an example, the first self-test circuit 2 is connected to the input end of the first signal input circuit 1 through the first reverse connection protection diode 101, so that the self-test signal of the first self-test circuit 2 and the signal to be sampled can be collected by the first signal acquisition circuit 3 in the same way. The first signal acquisition circuit 3 is connected to the first signal input circuit 1 through the second photoelectric coupler 108.

[0063] More specifically, the first self-test circuit 2 includes a first diode 101 and a first photocoupler 102. The first input end of the first photocoupler 102 is connected to the internal output control module to receive the output control signal A, the second input end of the first photocoupler 102 receives the onboard 5V high-level signal, the first output end of the first photocoupler 102 is grounded, the second output end of the first photocoupler 102 is connected to the anode of the first diode 101, and the cathode of the first diode 101 is connected to the first signal input circuit 1.

[0064] It is worth noting that after the input signal to be sampled passes through the voltage regulator tube, it drives the optocoupler switch to close, so that the signal of the signal acquisition circuit is at a high level. At this time, the GPIO port of the main control chip recognizes the high level, that is, it is determined that the board has a signal input. However, if the switch tube is broken down or the circuit is open, the main control chip cannot be sure whether the signal is correct. Therefore, a self-test circuit is added to the signal input source. Adding a self-test circuit can ensure that the hardware through which the input signal to be sampled passes is working normally, and the self-test circuit is connected to the input end of the signal input circuit, so that the self-test signal and the signal to be sampled can be collected by the signal acquisition circuit in the same way. This design can prevent the self-test signal of the self-test circuit from interfering with the input signal to be sampled.

[0065] In one embodiment, taking the main system input board as an example, the control logic of the first self-test circuit of the main system unit 1 and the second self-test circuit of the main system unit 2 in the main system input board is as follows:

[0066] Step 1: before collecting the input signal to be sampled each time, the internal output control module sends a self-test enable signal to the first self-test circuit of the main system unit 1 and the second self-test circuit of the main system unit 2 respectively during the self-test cycle, so that the first self-test circuit of the main system unit 1 and the second self-test circuit of the main system unit 2 are maintained at a high level. The voltage source can be the external power supply of the main system input board or the internal power supply of the main system input board.

[0067] Step 2: The main control chip of the main system reads the self-test signal of the main system unit 1 and the self-test signal of the main system unit 2. If it is "1", it indicates that the main system input board card is working normally at this time.

[0068] Step 3: After the self-test cycle ends, the internal output control module stops sending the self-test enable signal to the first self-test circuit of the main system unit 1 and the second self-test circuit of the main system unit 2.

[0069] Step 4: At this time, the main control chip of the main system reads the self-test signal of the main system unit 1 and the self-test signal of the main system unit 2. If it is "0", it indicates that the main system input board card is working normally at this time.

[0070] Step 5: The first signal acquisition circuit of the main system unit 1 and the second signal acquisition circuit of the main system unit 2 start to acquire the signal to be sampled.

[0071] In particular, the duration of step 2 and step 4 is set to a special cycle combination (for example, 15ms high level, 15ms low level), so that it has certain identification characteristics, which can prevent the influence of external interference on self-test. In addition, in order to improve efficiency, a self-test cycle can be performed after multiple sampling cycles, and the specific allocation ratio (for example, sampling cycle: self-test cycle = 10:1) shall be based on the signal reliability requirements in the work.

[0072] More specifically, the first signal input circuit includes a second diode 103, a first voltage stabilizing diode 104, a first resistor 105, a second voltage stabilizing diode 106, a switch tube 107 (MOS tube can be used, MOS is the abbreviation of Metal-Oxide-SemiconductorField-Effect Transistor, MOS tube is metal-oxide semiconductor field effect transistor, referred to as metal-oxide semiconductor field effect transistor), a second photocoupler 108, a second resistor 109, and a third resistor 110. The anode of the second diode 103 receives the input signal C to be sampled, the cathode of the second diode 103 is connected to the first end of the first resistor 105, the second end of the first resistor 105 is connected to the first end of the switch tube 107, the second end of the switch tube 107 receives the output control signal B, the third end of the switch tube 107 is connected to the anode of the second voltage stabilizing diode 106, and the cathode of the second voltage stabilizing diode 106 outputs the signal D to be sampled. The second photocoupler 108 is a common structure of the first signal input circuit 1 and the first signal acquisition circuit 3. The first input end of the second photocoupler 108 is connected to the first end of the third resistor 110, the second end of the third resistor 110 is connected to the cathode of the first voltage-regulating diode 104, and the anode of the first voltage-regulating diode 104 is connected to the first end of the first resistor 105. The second input end of the second photocoupler 108 receives an onboard 5V high-level signal, the first output end of the second photocoupler 108 is connected to the first end of the second resistor 109, and the second end of the second resistor 109 is connected to the first end of the switch tube 107. The second output end of the second photocoupler 108 is connected to the first signal acquisition circuit 3.

[0073] More specifically, the first signal acquisition circuit 3 includes a fourth resistor 111 and a fifth resistor 112. The second output end of the second photocoupler 108 is connected to the first end of the fourth resistor 111. The second end of the fourth resistor 111 is connected to the main system main control chip 17. The first end of the fifth resistor 112 is connected to the main system main control chip 17. The main system main control chip 17 receives the signal E. The second end of the fifth resistor 112 is grounded.

[0074] In each operation cycle, the GPIO interface (output control signal A) of the single-chip microcomputer controlled by software generates a jump between "0" and "1", and the interface (output control signal B) of the single-chip microcomputer controlled by software also generates a jump between "0" and "1" to close or open the switch tube 107. GPIO (General Purpose Input Output) is referred to as IO port, also called bus expander. The GPIO port is composed of pins and function registers. The GPIO package in different architectures is different, and the number of pins and registers used is different. The present invention can be set according to needs.

[0075] In one embodiment, during the self-test cycle, the self-test circuit works, the GPIO interface (output control signal A) of the single-chip microcomputer is controlled by software to generate a jump between "0" and "1", and the GPIO interface (output control signal B) of the single-chip microcomputer is controlled by software to output a low level, and the switch tube 107 is disconnected. At this time, it can be ensured that the self-test circuit is not affected by the signal to be sampled when it works. When the output control signal A outputs a high level, the level signal passes through the first photocoupler 102, the first photocoupler 102 collects the level signal, turns on the internal switch, and conducts the onboard 5V high level signal to the signal input circuit. At this time, the second photocoupler 108 is turned on, the signal acquisition circuit collects a high level, and the main control chip collects the signal port to read "1". When the output control signal A outputs a low level, the first photocoupler 102 is disconnected, and the signal acquisition circuit collects "0". The level jump mode of the signal acquisition circuit is consistent with the jump mode of the output control signal B, proving that the signal input circuit can input high and low levels, and the signal acquisition circuit can read high and low levels.

[0076] During the sampling period, the self-test circuit does not work. The GPIO interface (output control signal B) of the microcontroller is controlled by software to output high and low levels according to a specific period, and then close or open the switch tube 107. When the input signal to be sampled is "1", the switch tube 107 is closed at this time, and the signal acquisition circuit collects "1"; the switch tube 107 is disconnected, and the signal acquisition circuit collects "0". The dynamically changing numerical value proves that both the signal input circuit and the signal acquisition circuit are controllable, so it can be believed that the signal to be sampled is "1". When the signal to be sampled is "0", the signal acquisition circuit directly collects "0" and does not jump with the jump of the GPIO interface (output control signal B). At this time, the acquisition level is "0".

[0077] In one embodiment, the standby system input board 20 includes a standby system unit 15 and a standby system unit 26; the standby system unit 15 includes a third signal input circuit 7, a third self-test circuit 8, and a third signal acquisition circuit 9; the standby system unit 2 16 includes a fourth signal input circuit 10, a fourth self-test circuit 11, and a fourth signal acquisition circuit 12; the self-test circuit of each unit is connected to the input end of the signal input circuit of the corresponding unit, and the signal input circuit of each unit is connected to the signal acquisition circuit of the corresponding unit. Specifically, the standby system input board 20 and the main system input board 19 use the same software and hardware design to ensure the accuracy of the output signal, which will not be repeated here.

[0078] Specifically, the input signal to be sampled is simultaneously input into each unit of the main system input board 19 and the standby system input board 20, for a total of four channels. Under normal circumstances, the main system input board 19 works normally, and the standby system input board 20 works normally together as a hot standby board, but does not output any signal to the backplane bus. The two input signals on the main system input board are collected by the signal acquisition circuit and analyzed by the main control chip, and then voted. If the two signals on the main system input board are consistent, they are output to the backplane bus. At this time, the standby system input board 20 only votes and does not output. If the two signals of the main system input board 19 fail to vote (that is, the two signals on the main system input board are inconsistent), a fault message is output. At this time, the central processing unit outputs the signal of the standby system input board 20 to the backplane bus, that is, the standby system input board 20 is switched to the main system input board 19.

[0079] It is worth noting that the conditions for switching the master and standby system boards of the present invention not only occur when the master input board 19 votes and fails, but also include but are not limited to the failure of the hardware self-check of the master input board 19, the power failure of the master input board 19, the failure of the master control chip 17 of the master input board 19, etc. All software and hardware failures that cause the failure of the input signal to be sampled will trigger the master and standby system switching of the board.

[0080] In one embodiment, the main system input board card 19 and the standby system input board card 20 are isolated from each other and are powered independently.

[0081] Specifically, the main system input board 19 and the backup system input board 20 are independently powered and independently collect signals. This ensures that the main system input board 19 and the backup system input board 20 do not interfere with each other. When the main system input board 19 fails, the backup system input board 20 can also ensure that the input signal collection board collects signals normally.

[0082] In one embodiment, the units of the main system input board 19 and the standby system input board 20 are isolated from each other and powered independently. This ensures that the units do not interfere with each other, and when one unit fails, the other units can ensure that the input signal acquisition board can normally acquire signals.

[0083] Specifically, for the same signal acquisition channel, when the outside world enters the acquisition board, it will be divided into four parts independently without affecting each other. Two parts enter the two units of the main system input board respectively, and the other two parts enter the two units of the backup system input board respectively. This can ensure that the voting is not affected by common mode interference.

[0084] In one embodiment, each operation cycle of the input signal acquisition board includes a self-test cycle and a sampling cycle; during the self-test cycle, the input signal acquisition board performs hardware self-test; during the sampling cycle, the input signal acquisition board performs signal acquisition.

[0085] Specifically, Figure 5 As shown, each operation cycle may include a self-check cycle and one or more sampling cycles. For example, one self-check cycle is followed by one sampling cycle, and the sampling cycle and the self-check cycle do not overlap, or one self-check cycle is followed by 10 consecutive sampling cycles. This can be customized as needed. A certain safety margin is left between the self-check cycle and the sampling cycle to avoid signal errors or confusion that may lead to erroneous operations of the train control.

[0086] In one embodiment, the internal output control module controls the opening and closing of the switch tube connected in series with the self-test circuit signal source of each unit at a preset frequency and duty cycle in each sampling cycle, so that the level of the self-test circuit of each unit jumps between high and low levels, and the self-test signal and the signal to be sampled are collected by the signal acquisition circuit of each unit in the same way.

[0087] Specifically, in the self-check period, the self-check enable signal (output control signal A) is set to a high level; in the sampling period, the enable signal to be sampled (output control signal B) is set to a high level.

[0088] In one embodiment, when the switch tube of the self-test circuit of each unit is turned on and the level is high, the self-test circuit of each unit is used to detect whether there is a circuit break in each unit; when the switch tube of the self-test circuit of each unit is turned off and the level is low, the self-test circuit of each unit is used to detect whether there is a short circuit in each unit. The present invention proposes a hardware self-test solution for the entire process from input signal acquisition to recording, ensuring the validity of the input signal and quickly and accurately locating the fault type.

[0089] Table 1

[0090]

[0091] In one embodiment, the input signal acquisition board will periodically self-check and dynamically acquire signals. Therefore, when the signal to be sampled is "1", and the "1" and "0" acquired by the signal acquisition circuit can change with the closing and opening of the switch tube 107, the dynamically changing high level has the highest credibility. Therefore, the judgment standard of which board the fault occurs is based on the "dynamically changing high level" as the highest priority, followed by the acquisition of "0".

[0092] Specifically, the sampling results are voted according to the logic in Table 1.

[0093] Specifically, when the sampling results of the main system unit 1 and the main system unit 2 of the main system input board are both at the expected high level, the sampling result of the main system main control chip is "1", and the output sampling result is "1", indicating that the signal is valid.

[0094] When the sampling result of the main system unit 1 of the main system input board is an unexpected high level and the sampling result of the main system unit 2 is an expected high level, the sampling result of the main system main control chip is "fault". At this time, the main system input board is reported to be faulty, and the standby input board is switched to the main system input board.

[0095] When the sampling result of the main system unit 1 of the main system input board is an unexpected high level and the sampling result of the main system unit 2 is an expected high level, the sampling result of the main system main control chip is "fault". At this time, the main system input board is reported to be faulty, and the standby input board is switched to the main system input board.

[0096] When the sampling result of the main system unit 1 of the main system input board is the expected high level and the sampling result of the main system unit 2 is the unexpected high level, the sampling result of the main system main control chip is "fault". At this time, the main system input board is reported to be faulty, and the standby input board is switched to the main system input board.

[0097] When the sampling result of the main system unit 1 of the main system input board is the expected high level and the sampling result of the main system unit 2 is the expected low level, the sampling result of the main system main control chip is "fault". At this time, the main system input board is reported to be faulty, and the standby input board is switched to the main system input board.

[0098] When the sampling result of the main system unit 1 of the main system input board is low level and the sampling result of the main system unit 2 is the expected high level, the sampling result of the main system main control chip is "fault". At this time, the main system input board is reported to be faulty, and the standby input board is switched to the main system input board.

[0099] When the sampling result of the main system unit 1 of the main system input board is low level and the sampling result of the main system unit 2 is low level, the sampling result of the main system main control chip is "0". At this time, the output sampling result is "0", indicating that the signal is valid.

[0100] In one embodiment, the main system input board and the standby system input board use the same voting logic.

[0101] In one embodiment, in order to ensure that the abnormality of the input signal is detected in a relatively short time, an input result decision logic based on the main and standby system boards is proposed. Figure 4 It can be seen from the circuit that when the input signal is "1", in order to ensure the validity of the signal, the circuit will generate dynamic high and low levels due to the output control signal B periodically controlling the dynamic switching of the switch tube 107. After the dynamically changing level is collected, it can be trusted as a valid "1" signal; when the input signal is "0", there is no voltage in the circuit, and it is impossible to confirm whether the "0" signal is valid. Therefore, the comparison decision mechanism of the main system unit 1 and the main system unit 2 of the main system input board is introduced here, as shown in Table 1.

[0102] In particular, based on the results of laboratory and application assessments, the probability of both the main system input board and the backup system input board failing at the same time when the input signal is "0" is extremely low. Therefore, if the sampling results of the main and backup system boards are both "0", the signal can be trusted; if the sampling results of the main and backup system boards are "0" and "1" respectively, the signal "1" is confirmed to be trustworthy, and the board with a sampling value of "0" is a faulty board.

[0103] In one embodiment, the main system input board, the standby system input board, the internal output control module, and each unit all use TMS5701227 chips. Other chips may also be used, which are not listed here one by one.

[0104] Specifically, the TMS5701227 chip is a high-performance automotive-grade microcontroller. This chip integrates an ARMCortex-R4F floating-point CPU that can run at up to 180MHz and provide 298DMIPS performance. The TMS5701227 chip is designed to meet the needs of safety systems and has a range of safety features, including lock-step dual CPUs, CPU and memory BIST logic, ECC (error checking and correction) on flash and data SRAM, parity on peripheral memory, and loopback capability on peripheral I / O. In addition, the chip also supports EMAC (Ethernet Media Access Control) functionality and has 2x 12-bit ADC (analog-to-digital converter) and 24 channels.

[0105] The present invention proposes a hardware self-checking scheme for the entire process from input signal acquisition to recording, ensuring the validity of the input signal and quickly and accurately locating the fault type. The present invention also proposes a hot standby redundant, dual-path decision-making input signal acquisition board architecture, where both the main system input board and the backup system input board perform dual-path voting, and the main system input board and the backup system input board serve as hot standby for each other, greatly improving the availability and reliability of the input signal acquisition board. The input signal acquisition board of the present invention can ensure the normal operation of basic functions after a failure occurs in either the main system input board or the backup system input board, without causing functional failure.

[0106] like Figure 6 As shown, an embodiment of the present invention further provides a signal processing method for the input signal acquisition board as described in any one of the above items, and the signal processing method includes:

[0107] The main control chip of the main system receives the self-test signal of the self-test circuit of each main system unit to perform signal voting and determine whether the main system input board card has passed the self-test;

[0108] If the main control chip of the main system determines that the self-test of the main system input board card has passed, a signal vote is performed on the to-be-sampled signal of the corresponding signal input circuit collected by the signal collection circuit of each main system unit;

[0109] If the vote is passed, the output signal value of the main system input board will be output; otherwise, a main system input board failure will be reported.

[0110] Specifically, after the signal to be sampled is connected to the input signal acquisition board of the present invention, the central processing unit controls the internal output control module to periodically send a self-test enable signal to the self-test circuit. After the self-test circuit is turned on, the self-test signal is sent to the signal acquisition circuit. The main control chip obtains the self-test signal through the signal acquisition circuit and performs self-test. The main control chip of the main system input board and the standby main control chip of the standby input board perform self-tests at the same time. When the self-test signal of the main system unit one is consistent with the self-test signal of the main system unit two, the main control chip of the main system determines that the main system input board has passed the self-test. When the main system input board passes the self-test, the main control chip of the main system performs a signal vote on the signal to be sampled of the corresponding signal input circuit collected by the signal acquisition circuit of the main system unit one and the main system unit two; when the signal to be sampled of the main system unit one and the main system unit two is consistent, the vote is passed and the output signal value of the main system input board is output; otherwise, the main system input board is reported to be faulty.

[0111] In one embodiment, Figure 7 As shown, if the main system main control chip determines that the main system input board card fails the self-test, it reports that the main system input board card is faulty.

[0112] Specifically, when the self-test signal of the main system unit 1 is inconsistent with the self-test signal of the main system unit 2, the main system main control chip determines that the main system input board card self-test fails and reports that the main system input board card is faulty.

[0113] In one embodiment, when a fault is reported in the main system input board, the main control chip of the standby system determines whether the standby system input board has passed self-test;

[0114] If the standby system input board passes the self-test, a signal vote is performed on the signal to be sampled of the corresponding signal input circuit collected by the signal acquisition circuit of each standby system unit; if the vote passes, the output signal value of the standby system input board is output, otherwise the standby system input board fault is reported.

[0115] Specifically, when reporting a main system input card failure, the central processing unit determines whether the standby system input card has passed the self-test through the standby system main control chip; when the self-test signal of the standby system unit 1 is consistent with the self-test signal of the standby system unit 2, the standby system main control chip determines that the standby system input card has passed the self-test. If the standby system input card has passed the self-test, a signal vote is performed on the to-be-sampled signal of the corresponding signal input circuit collected by the signal collection circuit of each standby system unit; if the vote is passed, the output signal value of the standby system input card is output, otherwise the standby system input card failure is reported.

[0116] In one embodiment, if the standby system input board fails the self-test, a standby system input board failure is reported.

[0117] Specifically, when the self-test signal of the standby system unit 1 is inconsistent with the self-test signal of the standby system unit 2, the standby system main control chip determines that the standby system input board fails the self-test and reports that the standby system input board fails.

[0118] In one embodiment, when both the main system input board and the standby system input board work normally, the output signal value of the main system input board is output.

[0119] Specifically, when the main system input board and the backup system input board are working normally, the central processing unit only uses the output signal value of the main system input board, that is, the input signal acquisition board of the present invention only outputs the output signal value of the main system input board.

[0120] It is worth noting that when the main system input board and the backup system input board each have two units, a two-out-of-two voting mechanism is adopted, that is, when the signal values ​​of the two units of the main system input board are consistent, it indicates that the signal is valid, otherwise the signal is invalid. When the signal values ​​of the two units of the backup system input board are consistent, it indicates that the signal is valid, otherwise the signal is invalid. When the main system input board and the backup system input board each have multiple units, for example, when the main system input board has three main system units, a three-out-of-two voting mechanism can be adopted, and when the main system input board has five main system units, a five-out-of-three voting mechanism can be adopted. The voting mechanism is not specifically limited.

[0121] The present invention proposes a hardware self-checking scheme for the entire process from input signal acquisition to recording, ensuring the validity of the input signal and quickly and accurately locating the fault type. The present invention also proposes a hot standby redundant, dual-path decision-making input signal acquisition board architecture, where both the main system input board and the backup system input board perform dual-path voting, and the main system input board and the backup system input board serve as hot standby for each other, greatly improving the availability and reliability of the input signal acquisition board. The input signal acquisition board of the present invention can ensure the normal operation of basic functions after a failure occurs in either the main system input board or the backup system input board, without causing functional failure.

[0122] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0123] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0124] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0125] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0126] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. An input signal acquisition board, characterized in that: The input signal acquisition board includes a main system input board, a backup system input board, and an internal output control module, and the main system input board and the backup system input board are redundantly connected; The main system input board includes a main system main control chip and a plurality of main system units; each main system unit is redundantly connected; The backup system input board includes a backup system main control chip and a plurality of backup system units; each backup system unit is redundantly connected; Each main system unit and each standby system unit includes a signal input circuit, a self-test circuit, and a signal acquisition circuit. The self-test circuit of each unit is connected to the input end of the signal input circuit of the corresponding unit, and the signal input circuit of each unit is connected to the signal acquisition circuit of the corresponding unit. The internal output control module is respectively connected to the signal input circuit and the self-test circuit of each unit; The signal input circuit of each unit is respectively connected to the input terminal of the input signal acquisition board; The signal acquisition circuit of each main system unit is respectively connected to the main system main control chip; The signal acquisition circuit of each standby system unit is respectively connected to the standby system main control chip; The main control chip of the main system and the main control chip of the standby system are respectively connected to the output end of the input signal acquisition board.

2. The input signal acquisition board as claimed in claim 1, characterized in that: The main system input board includes a main system unit 1 and a main system unit 2. The main system unit 1 includes a first signal input circuit, a first self-test circuit, and a first signal acquisition circuit; the main system unit 2 includes a second signal input circuit, a second self-test circuit, and a second signal acquisition circuit.

3. The input signal acquisition board as claimed in claim 2, characterized in that: The first self-test circuit includes a first diode and a first photocoupler, wherein a first input end of the first photocoupler is connected to the internal output control module, a second input end of the first photocoupler receives an onboard level signal, a first output end of the first photocoupler is grounded, a second output end of the first photocoupler is connected to the anode of the first diode, and a cathode of the first diode is connected to the first signal input circuit.

4. The input signal acquisition board as claimed in claim 3, characterized in that: The first signal input circuit includes a second diode, a first voltage-stabilizing diode, a first resistor, a second voltage-stabilizing diode, a switch tube, a second photocoupler, a second resistor, and a third resistor, wherein the anode of the second diode receives the input signal to be sampled, the cathode of the second diode is connected to the first end of the first resistor, the second end of the first resistor is connected to the first end of the switch tube, the second end of the switch tube is connected to the internal output control module, the third end of the switch tube is connected to the anode of the second voltage-stabilizing diode, and the cathode of the second voltage-stabilizing diode outputs the signal to be sampled; The second photocoupler is a common structure of the first signal input circuit and the first signal acquisition circuit. The first input end of the second photocoupler is connected to the first end of the third resistor, the second end of the third resistor is connected to the cathode of the first voltage-regulating diode, the anode of the first voltage-regulating diode is connected to the first end of the first resistor, the second input end of the second photocoupler receives an onboard level signal, the first output end of the second photocoupler is connected to the first end of the second resistor, the second end of the second resistor is connected to the first end of the switch tube, and the second output end of the second photocoupler is connected to the first signal acquisition circuit.

5. The input signal acquisition board as claimed in claim 4, characterized in that: The first signal acquisition circuit includes a fourth resistor and a fifth resistor. The second output end of the second photoelectric coupler is connected to the first end of the fourth resistor, the second end of the fourth resistor is connected to the main system main control chip, the first end of the fifth resistor is connected to the main system main control chip, and the second end of the fifth resistor is grounded.

6. The input signal acquisition board as claimed in claim 1, characterized in that: The standby system input board includes a standby system unit 1 and a standby system unit 2; the standby system unit 1 includes a third signal input circuit, a third self-test circuit, and a third signal acquisition circuit; the standby system unit 2 includes a fourth signal input circuit, a fourth self-test circuit, and a fourth signal acquisition circuit.

7. The input signal acquisition board as claimed in claim 1, characterized in that: The main system input board card and the standby system input board card are isolated from each other and are powered independently.

8. The input signal acquisition board as claimed in claim 1, characterized in that: The units of the main system input board and the standby system input board are isolated from each other and are powered independently.

9. The input signal acquisition board as claimed in claim 1, characterized in that: Each operation cycle of the input signal acquisition board includes a self-check cycle and a sampling cycle; during the self-check cycle, the input signal acquisition board performs hardware self-check; during the sampling cycle, the input signal acquisition board performs signal acquisition.

10. The input signal acquisition board as claimed in claim 9, characterized in that: The internal output control module controls the opening and closing of the switch tube connected in series with the self-test circuit signal source of each unit at a preset frequency and duty cycle in each sampling cycle, so that the level of the self-test circuit of each unit jumps between high and low levels, and the self-test signal and the signal to be sampled are collected by the signal collection circuit of each unit in the same way.

11. The input signal acquisition board as claimed in claim 10, characterized in that: When the switch tube of the self-test circuit of each unit is turned on and the level is high, the self-test circuit of each unit is used to detect whether there is a circuit breakage in each unit; when the switch tube of the self-test circuit of each unit is turned off and the level is low, the self-test circuit of each unit is used to detect whether there is a short circuit in each unit.

12. The input signal acquisition board according to any one of claims 1 to 11, characterized in that: The main system input board, the standby system input board and the internal output control module all use the TMS5701227 chip.

13. A signal processing method for the input signal acquisition board as claimed in any one of claims 1 to 12, characterized in that: The signal processing method comprises: The main control chip of the main system receives the self-test signal of the self-test circuit of each main system unit to perform signal voting and determine whether the main system input board card has passed the self-test; If the main control chip of the main system determines that the self-test of the main system input board card has passed, a signal vote is performed on the to-be-sampled signal of the corresponding signal input circuit collected by the signal collection circuit of each main system unit; If the vote is passed, the output signal value of the main system input board will be output; otherwise, a main system input board failure will be reported.

14. The signal processing method according to claim 13, characterized in that: If the main system main control chip determines that the main system input board card fails the self-test, it reports a main system input board card failure.

15. The signal processing method according to claim 13 or 14, characterized in that: When a main system input card failure is reported, the standby system main control chip determines whether the standby system input card has passed the self-test; If the self-test of the standby system input board card passes, a signal vote is performed on the to-be-sampled signal of the corresponding signal input circuit collected by the signal collection circuit of each standby system unit; If the vote is passed, the output signal value of the standby system input board card will be output, otherwise the standby system input board card failure will be reported.

16. The signal processing method according to claim 15, characterized in that: If the standby system input board fails the self-test, a standby system input board failure is reported.

17. The signal processing method according to claim 16, characterized in that: When both the main system input board and the standby system input board operate normally, the output signal value of the main system input board is output.

Images