True random number generator circuit based on jitter accumulation binarization

Abstract

The present invention discloses a true random number generator circuit based on jitter accumulation binarization, comprising: an entropy source generation module including a 3N-stage ring oscillator; a true random number generation module including a jitter accumulation binarization circuit and a counting register circuit, wherein the jitter accumulation binarization circuit includes an exclusive-OR gate, a delay unit, and a reset circuit, wherein two input ends of the exclusive-OR gate are respectively connected to two output ends of the entropy source generation module, an output end of the exclusive-OR gate is connected to the input end of the delay unit and the reset circuit, and the output end of the delay unit is also connected to the input end of the reset circuit, and the output end of the reset circuit serves as the output end of the jitter accumulation binarization circuit to reset the 3N-stage ring oscillator when the pulse width of the random number entropy source signal output by the exclusive-OR gate is greater than the delay width threshold of the delay signal; the counting register circuit is connected to the other output end of the entropy source generation module and the output end of the jitter accumulation binarization circuit; and a post-processing module connected to the counting register circuit for outputting a true random number sequence.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a true random number generator circuit based on jitter accumulation binarization. Background Art

[0002] Random number generators have become an essential component of secure communication and information systems. They play a key role in a wide range of cryptographic applications, including authentication protocols, data encryption, and random padding. In addition, numerical simulations and random experiments in software also require a large number of high-quality random numbers. However, pseudo-random number generators (PRNGs) rely on deterministic mathematical models and initial states (also known as seeds), which makes them vulnerable to attack. In contrast, true random number generators (TRNGs) utilize the inherent non-deterministic physical processes of various solid-state devices, including thermal noise, jitter, and chaos, to generate bit streams with ultra-high entropy. This unpredictability is crucial to strengthening system security, making true random number generators a key solution for ensuring the security of sensitive information and applications.

[0003] Various types of true random number generators have been disclosed in the prior art, such as the currently disclosed high-performance true random number generator based on random clock jitter design of a ring oscillator, which achieves a true random number generator with excellent randomness by utilizing the collapse time of two competing edges of the ring oscillator. For example, Figure 1 In the illustrated true random number generator circuit, entropy is generated using a 3N-stage ring oscillator 1. This 3N-stage ring oscillator 1 may include three cascaded inverter oscillator circuits. The three inverter oscillator circuits are controlled by the same enable signal RO_EN, and the outputs of the three inverter oscillator circuits are highly synchronized, with similar jitter noise levels. This is also known as a three-edge ring oscillator. Due to jitter accumulation in this true random number generator circuit, frequency collapse (FC) is inevitable after RO_EN is asserted. The frequency collapse time is used as the main entropy source. However, to accurately detect the frequency collapse time, the post-processing phase-frequency detector (PFD) 3 always requires an additional reference ring oscillator 2, resulting in a large power consumption design overhead. In addition, since the frequency collapse time, which is mainly due to jitter, varies in each cycle, and the fixed period of RO_EN, i.e., the entropy sampling period, must be greater than the maximum frequency collapse time, redundant oscillations exist in most cycles, resulting in power consumption and throughput loss. Summary of the Invention

[0004] The present invention provides a true random number generator circuit based on jitter accumulation binarization to solve the technical problems that the existing true random number generator circuit requires an additional reference ring oscillator and has redundant oscillations in most sampling and extraction cycles during entropy source sampling and extraction, resulting in power consumption and throughput loss.

[0005] To solve the above technical problems, the present invention provides a true random number generator circuit based on jitter accumulation binarization, comprising:

[0006] An entropy source generation module, comprising a 3N-stage ring oscillator, for generating three random number entropy source signals;

[0007] A true random number generation module includes a jitter accumulation binarization circuit and a counting register circuit. The jitter accumulation binarization circuit includes an exclusive-OR gate, a delay unit, and a reset circuit. The two input ends of the exclusive-OR gate are respectively connected to the two output ends of the entropy source generation module, and its output end is connected to the input end of the delay unit and the input end of the reset circuit. The output end of the delay unit is connected to the input end of the reset circuit. The output end of the reset circuit serves as the output end of the jitter accumulation binarization circuit to reset the 3N-stage ring oscillator when the pulse width of the random number entropy source signal output by the exclusive-OR gate is greater than the delay width threshold of the delay signal. The counting register circuit is connected to the other output end of the entropy source generation module and the output end of the jitter accumulation binarization circuit.

[0008] The post-processing module is connected to the output end of the counting register circuit and is used to output a true random number sequence.

[0009] Compared with the prior art, the present invention is based on a true random number generator circuit of jitter accumulation binarization. A random number entropy source signal output by a 3N-stage ring oscillator is subjected to entropy extraction and quantization by a counting register circuit in a true random number generation module. The other two random number entropy source signals output by the 3N-stage ring oscillator are subjected to XOR processing by an XOR gate in a jitter accumulation binarization circuit. The random number entropy source signal after XOR processing is then subjected to phase delay shifting by a delay unit. The random number entropy source delayed signal after phase delay shifting and the random number entropy source signal after XOR processing are processed by a reset circuit to reset the 3N-stage ring oscillator when the pulse width of the random number entropy source signal output by the XOR gate is greater than the delay width threshold of the random number entropy source delay signal, so that the 3N-stage ring oscillator is reset when the pulse width of the random number entropy source signal output by the XOR gate is greater than the delay width threshold of the random number entropy source delay signal. The N-stage ring oscillator enters the next entropy sampling cycle, and at the same time latches the random number entropy source signal sampled and quantized in the counting register circuit, and is cleared to enter the next entropy counting latch cycle and recount. The post-processing module processes the random number entropy source signal sampled and quantized in the counting register circuit, thereby outputting a corresponding true random number sequence. It can be seen that the true random number generator circuit based on jitter accumulation binarization of the present invention does not require an additional reference ring oscillator, which can reduce power consumption, and the entropy sampling period can be adaptively set through the reset output of the jitter accumulation binarization circuit, which can eliminate the redundant oscillation caused by the fixed period of RO_EN in the prior art must be greater than the maximum value of the frequency collapse time, which can further reduce power consumption and throughput loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0011] Figure 1 It is a circuit block diagram of a true random number generator circuit in an embodiment of the prior art.

[0012] Figure 2 1 is a circuit block diagram of a true random number generator circuit based on jitter accumulation binarization in one embodiment of the present invention.

[0013] Figure 3 yes Figure 2 The figure shows a specific circuit diagram of a jitter accumulation binarization circuit in a true random number generator circuit based on jitter accumulation binarization.

[0014] Figure 4 yes Figure 2 The figure shows a specific circuit diagram of a counting register circuit in a true random number generator circuit based on jitter accumulation binarization.

[0015] Figure 5 yes Figure 2 The figure shows a specific circuit diagram of a three-stage XOR chain circuit in a true random number generator circuit based on jitter accumulation binarization.

[0016] Figure 6 yes Figure 2 The figure shows a specific circuit diagram of a 3N-stage ring oscillator in a true random number generator circuit based on jitter accumulation binarization.

[0017] Figure 7 yes Figure 2 The waveform diagram of the true random number generator circuit based on jitter accumulation binarization is shown.

[0018] Figure 8 yes Figure 3 The waveform diagram of the jitter accumulation binarization circuit shown.

[0019] Figure 9 The figure is a schematic diagram of the test effect of the true random number generator circuit based on jitter accumulation binarization provided by an embodiment of the present invention.

[0020] Figure 10 This is another schematic diagram of test results of a true random number generator circuit based on jitter accumulation binarization provided by an embodiment of the present invention.

[0021] Figure 11 This is another schematic diagram of test results of the true random number generator circuit based on jitter accumulation binarization provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0022] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0023] Reference Figures 2 to 8 , Figures 2 to 8 A specific embodiment of the true random number generator circuit based on jitter accumulation binarization of the present invention is shown. In the embodiment shown in the accompanying drawings, the true random number generator circuit based on jitter accumulation binarization includes an entropy source generation module 10, a true random number generation module 20, and a post-processing module 30, wherein the entropy source generation module 10 includes a 3N-stage ring oscillator 11 for generating three random number entropy source signals; the true random number generation module 20 includes a jitter accumulation binarization circuit 21 and a counting register circuit 22, an input end of the counting register circuit 22 is connected to an output end of the entropy source generation module 10 to sample and quantize the random number entropy source signal, combined with Figure 3 The jitter accumulation binarization circuit 21 includes an XOR gate XOR1, a delay unit 212 and a reset circuit. The two input ends of the XOR gate XOR1 are respectively connected to the two output ends of the entropy source generation module 10, and its output end is connected to the input end of the delay unit 212 and the input end of the reset circuit. The output end of the delay unit 212 is connected to the input end of the reset circuit. The output end of the reset circuit serves as the output end of the jitter accumulation binarization circuit 21, so that the pulse width of the random number entropy source signal output by the XOR gate XOR1 is greater than the delay of the delay signal. The 3N-stage ring oscillator 11 is reset when the width threshold is reached, so that the 3N-stage ring oscillator 11 enters the next entropy sampling cycle; the counting register circuit 22 is also connected to the output end of the jitter accumulation binarization circuit 21 to latch the random number entropy source signal of this sampling quantization when the pulse width of the random number entropy source signal output by the exclusive OR gate XOR1 is greater than the delay width threshold of the delay signal, and clear it to enter the next entropy counting latch cycle and recount; the post-processing module 30 is connected to the output end of the counting register circuit 22 for outputting a true random number sequence.

[0024] Based on the above design, the true random number generator circuit of the present invention performs jitter accumulation judgment on the random number entropy source signal through the jitter accumulation binarization circuit 21. When the pulse width of the random number entropy source signal output by the exclusive OR gate XOR1 is greater than the delay width threshold of the random number entropy source delay signal output by the delay unit 212, the 3N-stage ring oscillator 11 is reset, so that the 3N-stage ring oscillator 11 enters the next entropy sampling cycle. At the same time, the random number entropy source signal sampled and quantized in this time in the counting register circuit 22 is latched and cleared to enter the next entropy counting latch cycle. The entropy sampling cycle can be adaptively set to improve detection accuracy, eliminate redundant oscillations caused by the fixed period of RO_EN in the prior art that must be greater than the maximum frequency collapse time, further reduce power consumption and throughput loss, and do not require an additional reference ring oscillator.

[0025] Continue to refer to Figure 3In some embodiments, the delay unit 212 includes a plurality of inverters connected in series, the reset circuit includes a reset NAND gate 213 and an enable signal generator, the enable signal generator includes a first pulse generator U1, a second pulse generator U2, a first AND gate 233, a second AND gate 234 and a reset register 235, wherein the two input ends of the reset NAND gate 213 are respectively connected to the output end of the delay unit 212 and the XOR gate XOR1, the enable end of the second pulse generator U2 and an input end of the first AND gate 233 receive an external enable signal Enable, the enable end of the first pulse generator U1 is connected to the output end of the reset NAND gate 213, and its output end is connected to the other input end of the first AND gate 233, and through a buffer The first and second AND gates 233 and 234 are connected to the reset and enable terminals of the reset register 235, respectively. The output terminal of the reset register 235 is connected to the entropy source generating module 10 and the counting register circuit 22 to send an enable signal RO_EN to the 3N-stage ring oscillator 11 and the counting register circuit 22. When the pulse width of the random number entropy source signal output by the exclusive OR gate XOR1 is greater than the delay width threshold of the delay signal, the enable signal RO_EN is reset, thereby resetting the 3N-stage ring oscillator 11 and causing the counting register circuit 22 to enter the next entropy counting latch cycle. Based on the above design, when the reset NAND gate 213 generates the reset signal RST, the reset signal RST is transmitted to the first pulse generator U1 to reset the enable signal RO_EN input to the 3N-stage ring oscillator 11 and the counting register circuit 22, so that the 3N-stage ring oscillator 11 enters the next entropy sampling cycle, and the counting register circuit 22 enters the next entropy counting latch cycle.

[0026] It can be understood that in order to quantify the degree of jitter accumulation, the present invention provides a jitter accumulation binarization circuit 21 having a delay unit 212, which converts the two output signals (such as Figure 3 As shown, OUT1 and OUT2 are processed by XOR respectively, and the random number entropy source signal J generated after XOR processing is A The pulse width PW of JA is dominated by jitter noise and is caused by jitter accumulation between cycles. JA Increase, by the time threshold of the preset delay width threshold PWth, the random number entropy source signal J from the XOR gate XOR1 is shifted A phase and generates a new signal J B , that is, the random number entropy source delay signal, the random number entropy source signal J output by the XOR gate XOR1 Aand random number entropy source delayed signal J B is fed into the reset NAND gate 213. Once PW JA Greater than PWth (where PW JA Equal to PW JB ), it will automatically generate a reset signal RST. Figure 8 It can be seen that PWth is the pulse width PW JA The sum of the preset delay shift width and the preset delay shift width / preset delay time can be randomly set, and the jitter accumulation is judged to be sufficient by the PWth preset in the delay unit 212, and the time J to reach the above jitter accumulation binarization is used. JAT (like Figure 7 as entropy source.

[0027] Continue to refer to Figure 2 and Figure 4 In some embodiments, the counting register circuit 22 includes a signal flip counter 221 and a data latch module 222. The input end of the signal flip counter 221 is connected to an output end of the entropy source generation module 10 to count and record the number of flips of the random number entropy source signal. The output end of the signal flip counter 221 is connected to an input end of the data latch module 222. The other input end of the data latch module 222 is connected to the output end of the reset circuit, and is used to latch the data from the signal flip counter 221. When the enable signal RO_EN is reset, the signal flip counter 221 is cleared and the counting is restarted. The output end of the data latch module 222 is connected to the post-processing module 30. Preferably, in this embodiment, the data latch module 222 latches the data of the signal flip counter 221 at the falling edge of the enable signal RO_EN. The data latch module 222 includes a D flip-flop. In the present invention, the signal flip counter 221 observes the input random number entropy source signal OUT3, and once the random number entropy source signal OUT3 is observed to flip, the cumulative count is performed to record the number of flips of the random number entropy source signal OUT3, wherein the number of flips specifically includes: the number of flips of the random number entropy source signal from a high level to a low level and the number of flips from a low level to a high level, that is, the flip of the random number entropy source signal OUT3 from "1" to "0" or from "0" to "1" is counted as one flip; and the data latch module 222 latches the current random number entropy source sequence at the falling edge of the enable signal RO_EN, and maintains the latched data when the enable signal RO_EN is reset, and clears the signal flip counter 221 to restart counting.

[0028] Because the larger the PWth, the JATThe wider the distribution, in order to achieve a good balance between the sampling frequency of the true random number generator circuit of the present invention and the maximum random bit that can be extracted per sampling, in this embodiment, the preset delay width threshold PWth is set to 99ps, and the bit width M of the signal flip counter 221 is set to 3. The true random number generator circuit based on jitter accumulation binarization of the present invention can have three output bit channels RN[1:3]. Then, the post-processing module 30 includes three three-stage XOR chain circuits 31 to output three bit streams. Figure 5 , Figure 5 The specific circuit structure of a three-stage XOR chain circuit 31 is shown in the figure. As shown in the figure, the three-stage XOR chain circuit 31 includes a first D flip-flop D1, a second D flip-flop D2, a third D flip-flop D3, a first XOR gate XOR2, a second XOR gate XOR4 and a third XOR gate XOR3. The output end of the counting register circuit 22 is connected to the data input end of the first D flip-flop D1 and one input end of the first XOR gate XOR2, the output end of the first D flip-flop D1 is connected to the other input end of the first XOR gate XOR2 and the data input end of the second D flip-flop D2, the output end of the second D flip-flop D2 is connected to one input end of the second XOR gate XOR4 and the data input end of the third D flip-flop D3, the output end of the third D flip-flop D3 is connected to the other input end of the second XOR gate XOR4, the output ends of the second XOR gate XOR4 and the first XOR gate XOR2 are respectively connected to the two input ends of the third XOR gate XOR3, and the output end of the third XOR gate XOR3 serves as the output end of the true random number generator circuit to output a true random number sequence RN.

[0029] In some embodiments, the 3N-stage ring oscillator 11 includes three oscillation circuits connected in series, each of which includes a NAND gate and N inverters connected in series to the output of the NAND gate. The output of the inverter serves as an output of the 3N-stage ring oscillator 11. One input of the NAND gate receives an enable signal RO_EN, and the other input is connected to the output of another oscillation circuit. Specifically, Figure 6As shown, the 3N-stage ring oscillator 11 includes three oscillator circuits, namely a first oscillator circuit, a second oscillator circuit, and a third oscillator circuit, connected in cascade. The first oscillator circuit includes a NAND gate 111 and N inverters 112. The second oscillator circuit includes a NAND gate 121 and N inverters 122. The third oscillator circuit includes a NAND gate 131 and N inverters 132. The output of inverter 112 is connected to an input of NAND gate 121, the output of inverter 122 is connected to an input of NAND gate 131, and the output of inverter 132 is connected to an input of NAND gate 111. The other inputs of NAND gates 111, 121, and 131 are all connected to the output of an enable signal generator to receive an enable signal RO_EN. Preferably, the number of inverters in the oscillator circuit can be 7, i.e., N=7.

[0030] The performance of the true random number generator circuit based on jitter accumulation binarization of the present invention is verified below:

[0031] In order to verify the proposed true random number generator circuit design, the true random number generator circuit based on jitter accumulation binarization of the present invention was fabricated using a 65nm, 1.2V standard CMOS process. The entire silicon area is 630μm 2 (ie the normalized area is 149KF 2 ). In order to quantitatively evaluate the randomness of the fabricated true random number generator circuit, the SP800-22 and SP800-90B test tools of the National Institute of Standards and Technology (NIST) of the United States were used to evaluate the randomness of the generated bit stream. Specifically, the 10M-bit data streams corresponding to the output RN[1:3] of the true random number generator circuit were collected, divided into 10 groups, and input into the NIST test tool. Table 1 shows the test results of NIST SP800-22. It is observed that the confidence (P) of all sub-test items is greater than 0.01, which well demonstrates the high randomness of the proposed true random number generator circuit based on jitter accumulation binarization. In the test results of NIST SP800-90B shown in Table 2, all three bit channels also successfully passed the four independent and identically distributed (IID) test items in NIST SP800-90B. The lowest minimum entropy in the IID test item is equal to 0.99825. In addition, the autocorrelation function (ACF) is used to further verify the randomness of the true random number generator. The test results are as follows: Figure 9 As shown in (c), the value of the autocorrelation function is ±0.000627, with a confidence level of 95%.

[0032]

[0033] Table 1

[0034]

[0035] Table 2

[0036] In addition, in order to observe whether there are periodic changes in a large number of random numbers, Figure 9 Figures (a) and (b) in the figure respectively show the speckle pattern of 1 million random bits generated by the true random number generator circuit of the present invention and the amplitude spectrum of the 1 million random bits subjected to fast Fourier transform (FFT) using a Hanning window. Figure 9 In (a), black and white dots are evenly distributed, and the black and white dots represent "0" and "1" respectively. Figure 9 A flat amplitude spectrum can be observed in (b), which further verifies the uncertainty and non-periodic characteristics of the true random number generator circuit of the present invention.

[0037] Reference Figure 10 , Figure 10 The Shannon entropy measurements and average values ​​of 10 true random number generator circuits are shown over the industrial temperature range of -40°C to 125°C and the power supply voltage range of 1.0V to 1.4V. As can be seen from the figure, within the above voltage-temperature range, the minimum Shannon entropy of the true random number generator circuit is 0.999998, which fully demonstrates the excellent process-voltage-temperature tolerance of the true random number generator circuit based on jitter accumulation binarization of the present invention.

[0038] Reference Figure 11 , Figure 11 The measured power consumption of the true random number generator at different power supply voltages ranging from 1V to 1.4V is demonstrated. According to reports, its energy efficiency is 1.46pJ / bit when the power supply voltage is 1V, which is about 1.01 to 18.68 times higher than the energy efficiency of some ring oscillator-based true random number generators in the existing technology.

[0039] In summary, the true random number generator circuit based on jitter accumulation binarization of the present invention extracts and quantizes entropy from a random number entropy source signal output by a 3N-stage ring oscillator through a counting register circuit in a true random number generation module. The other two random number entropy source signals output by the 3N-stage ring oscillator are XOR-processed by an XOR gate in the jitter accumulation binarization circuit. The random number entropy source signal after XOR processing is then phase-delayed and shifted by a delay unit. The random number entropy source delayed signal after the phase delay shift and the random number entropy source signal after XOR processing are processed by a reset circuit to output a reset signal when the pulse width of the random number entropy source signal output by the XOR gate is greater than the delay width threshold of the random number entropy source delayed signal, thereby resetting the enable signal of the 3N-stage ring oscillator, so that the 3N-stage ring oscillator enters the next entropy sampling cycle, and at the same time latches the random number entropy source signal sampled and quantized this time in the counting register circuit, and clears it to enter the next entropy counting latch cycle. During the recounting and sampling quantization process, the post-processing module processes the sampled and quantized random number entropy source signal, thereby outputting a corresponding true random number sequence. It can be seen that the true random number generator circuit of the present invention performs jitter accumulation judgment on the random number entropy source signal through the jitter accumulation binarization circuit, and outputs a reset signal when the pulse width of the random number entropy source signal output by the XOR gate is greater than the delay width threshold of the random number entropy source delay signal, thereby resetting the enable signal of the 3N-stage ring oscillator, so that the 3N-stage ring oscillator enters the next entropy sampling cycle, and at the same time latches the random number entropy source signal sampled and quantized in this time in the counting register circuit, and clears it to enter the next entropy counting latch cycle. The period of the enable signal RO_EN can be adaptively set, thereby improving detection accuracy, eliminating redundant oscillations caused by the fixed period of RO_EN in the prior art that must be greater than the maximum frequency collapse time, further reducing power consumption and throughput loss, and eliminating the need for an additional reference ring oscillator.

[0040] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention, and should all be included in the scope of protection of the present invention.

Claims

1. A true random number generator circuit based on jitter accumulation binarization, characterized in that: include: An entropy source generation module, comprising a 3N-stage ring oscillator, for generating three random number entropy source signals; A true random number generation module includes a jitter accumulation binarization circuit and a counting register circuit. The jitter accumulation binarization circuit includes an exclusive-OR gate, a delay unit, and a reset circuit. The two input ends of the exclusive-OR gate are respectively connected to the two output ends of the entropy source generation module, and its output end is connected to the input end of the delay unit and the input end of the reset circuit. The output end of the delay unit is connected to the input end of the reset circuit. The output end of the reset circuit serves as the output end of the jitter accumulation binarization circuit to reset the 3N-stage ring oscillator when the pulse width of the random number entropy source signal output by the exclusive-OR gate is greater than the delay width threshold of the delay signal. The counting register circuit is connected to the other output end of the entropy source generation module and the output end of the jitter accumulation binarization circuit. The post-processing module is connected to the output end of the counting register circuit and is used to output a true random number sequence.

2. The true random number generator circuit based on jitter accumulation binarization according to claim 1, characterized in that: The delay unit includes a plurality of inverters connected in series.

3. The true random number generator circuit based on jitter accumulation binarization according to claim 1, characterized in that: The reset circuit includes a reset NAND gate and an enable signal generator. The enable signal generator includes a first pulse generator, a second pulse generator, a first AND gate, a second AND gate, and a reset register. The two input ends of the reset NAND gate are respectively connected to the output ends of the delay unit and the XOR gate. The enable end of the second pulse generator and one input end of the first AND gate receive an external enable signal. The enable end of the first pulse generator is connected to the output end of the reset NAND gate, and its output end is connected to the other input end of the first AND gate and connected to one input end of the second AND gate through a buffer. The other input end of the second AND gate is connected to the output end of the second pulse generator. The output ends of the first AND gate and the second AND gate are respectively connected to the reset end and enable end of the reset register. The output end of the reset register is connected to the entropy source generation module and the counting register circuit to send an enable signal to the 3N-stage ring oscillator and the counting register circuit. When the pulse width of the random number entropy source signal output by the XOR gate is greater than the delay width threshold of the delay signal, the enable signal is reset, thereby resetting the 3N-stage ring oscillator.

4. The true random number generator circuit based on jitter accumulation binarization according to claim 3, characterized in that: The counting register circuit includes a signal flip counter and a data latch module. The input end of the signal flip counter is connected to an output end of the entropy source generation module to record the number of flips of the random number entropy source signal. The output end of the signal flip counter is connected to an input end of the data latch module. The other input end of the data latch module is connected to the output end of the reset circuit for latching data from the signal flip counter and clearing the signal flip counter to zero and recounting when the enable signal is reset. The output end of the data latch module is connected to the post-processing module.

5. The true random number generator circuit based on jitter accumulation binarization according to claim 4, characterized in that: The data latch module latches the data of the signal inversion counter at the falling edge of the enable signal.

6. The true random number generator circuit based on jitter accumulation binarization according to claim 4, characterized in that: The flipping times specifically include: the flipping times of the random number entropy source signal from a high level to a low level and the flipping times from a low level to a high level.

7. The true random number generator circuit based on jitter accumulation binarization according to claim 4, characterized in that: The data latch module includes a D flip-flop.

8. The true random number generator circuit based on jitter accumulation binarization according to claim 1, characterized in that: The post-processing module includes at least one three-stage XOR chain circuit, which includes a first D flip-flop, a second D flip-flop, a third D flip-flop, a first XOR gate, a second XOR gate, and a third XOR gate. The output of the counting register circuit is connected to a data input of the first D flip-flop and an input of the first XOR gate, the output of the first D flip-flop is connected to the other input of the first XOR gate and the data input of the second D flip-flop, the output of the second D flip-flop is connected to an input of the second XOR gate and the data input of the third D flip-flop, the output of the third D flip-flop is connected to the other input of the second XOR gate, the outputs of the second and first XOR gates are respectively connected to the two inputs of the third XOR gate, and the output of the third XOR gate serves as the output of the true random number generator circuit to output a true random number sequence.

9. The true random number generator circuit based on jitter accumulation binarization according to claim 1, characterized in that: The 3N-stage ring oscillator includes three oscillation circuits cascaded in sequence. The oscillation circuit includes a NAND gate and N inverters connected in series to the output end of the NAND gate. The output end of the inverter serves as an output end of the 3N-stage ring oscillator. One input end of the NAND gate receives an enable signal, and the other input end is connected to the output end of another oscillation circuit.

10. The true random number generator circuit based on jitter accumulation binarization according to claim 9, characterized in that: The number of inverters in the oscillation circuit is 7.

Images