FPGA board card remote upgrading method and system

Abstract

The invention discloses an FPGA (Field Programmable Gate Array) board card upgrading method and system, the method is applied to a system in which an FPGA board card and a CPU (Central Processing Unit) are interconnected through PCIE (Peripheral Component Interface Express), and the method comprises the following steps: in the running process of a CPU operating system, loading an SPI (Serial Peripheral Interface) driver and an MTD (Multimedia Transfer Device) driver through a preset command; calling a preset registration code by the PCIE equipment driver, and registering an SPI controller to call the SPI driver; the SPI drive calls the MTD drive and is connected with an SPI flash memory; the MTD driver generates a corresponding MTD block device under a specified directory; and the CPU operating system sends an FPGA board card upgrading program to the MTD block device, and the MTD block device programs the FPGA board card upgrading program into the SPI flash memory so as to complete FPGA board card upgrading. According to the FPGA board card upgrading scheme provided by the invention, remote upgrading of the FPGA board card can be realized.

Description

Technical Field

[0001] The present invention relates to the technical field of intelligent hardware, and in particular to a method and system for upgrading an FPGA board. Background Art

[0002] There are two main ways to upgrade existing FPGA (Field Programmable Gate Array) boards:

[0003] Method 1: A technician needs to go to the site and remove the card from the chassis. Figure 1 As shown, a computer is connected to the circuit board using a burner, and the upgrade program is downloaded to the memory using a tool on the computer. The board is then installed back into the chassis. The entire process is cumbersome, costly, and prone to error.

[0004] Method 2: If Figure 2 As shown, if the circuit board has Ethernet, the upgrade program can be sent to the onboard MCU (Microcontroller Unit) through Ethernet. The MCU is connected to the FPGA board through USB or serial port. Custom programs need to be developed between the MCU and the FPGA board, and between the FPGA board and the memory. The upgrade program is downloaded to the memory through program control to complete the program upgrade. Compared with method one, it can avoid the need for technicians to go to the site and dismantle the chassis, and solve the problems of too many intermediate adapter programs, long development cycle, and poor stability. Summary of the invention

[0005] The purpose of the embodiments of the present invention is to provide a method and device for upgrading an FPGA board, which can solve the problems existing in the prior art of having too many adaptation programs, a long development cycle and poor stability.

[0006] In order to solve the above technical problems, the present invention provides the following technical solutions:

[0007] An embodiment of the present invention provides a method for upgrading an FPGA (Field Programmable Gate Array) board, which is applied to a system in which an FPGA board and a CPU (Central Processing Unit) are interconnected via PCIE, and the method includes:

[0008] During the operation of the CPU operating system, the SPI driver and the MTD driver are loaded through a preset command;

[0009] The PCIE device driver calls a preset registration code to register the SPI controller to call the SPI driver;

[0010] The SPI driver calls the MTD driver and connects to the SPI flash memory;

[0011] The MTD driver generates a corresponding MTD block device in a specified directory;

[0012] The CPU operating system sends the FPGA board upgrade program to the MTD block device, and the MTD block device burns the FPGA board upgrade program into the SPI flash memory to complete the FPGA board upgrade.

[0013] Optionally, during the operation of the CPU operating system, the step of loading the SPI driver and the MTD driver through a preset command includes:

[0014] During the operation of the CPU operating system, the SPI driver and the MTD driver are loaded using the insmod command or the modprobe command.

[0015] Optionally, a serial communication interface (QSPI) is preset in the FPGA, and the serial communication interface (QSPI) is connected to the PCIE through an interconnection network based on the AXI protocol, and the other end of the PCIE is connected to the CPU.

[0016] Optionally, the step of the PCIE device driver calling a preset registration code to register the SPI controller to call the SPI driver includes:

[0017] Defining an abstract SPI controller pointer in a private data structure of the FPGA board;

[0018] Using the registration code preset in the probe function code part of the FPGA board, create an SPI controller, and assign the SPI controller address to the SPI controller pointer;

[0019] Initializing the internal data of the SPI controller;

[0020] Use the spi_bitbang_start function to start the SPI bus and call the SPI driver.

[0021] Optionally, after the step of the MTD block device burning the FPGA board upgrade program into the SPI flash memory, the method further includes:

[0022] The MTD block device is used to read the burned upgrade program from the SPI flash memory, and the upgrade program is compared with the upgrade program written into the SPI flash memory by the MTD block device to complete the upgrade program verification.

[0023] The embodiment of the present invention further provides an FPGA board upgrade system, wherein the system comprises: an FPGA board and a CPU interconnected by PCIE, and the CPU comprises:

[0024] A loading module, used to load the SPI driver and the MTD driver through a preset command during the operation of the CPU operating system;

[0025] The FPGA board includes:

[0026] A first calling module is used to call a preset registration code through a PCIE device driver to register an SPI controller to call the SPI driver;

[0027] A second calling module is used to call the MTD driver through the SPI driver and connect to the SPI flash memory;

[0028] A generation module, used to generate a corresponding MTD block device in a specified directory through the MTD driver;

[0029] The CPU also includes:

[0030] The sending module is used to send the FPGA board upgrade program to the MTD block device, and burn the FPGA board upgrade program into the SPI flash memory through the MTD block device to complete the FPGA board upgrade.

[0031] Optionally, the loading module is specifically used for:

[0032] During the operation of the CPU operating system, the SPI driver and the MTD driver are loaded using the insmod command or the modprobe command.

[0033] Optionally, a serial communication interface (QSPI) is preset in the FPGA, and the serial communication interface (QSPI) is connected to the PCIE through an interconnection network based on the AXI protocol, and the other end of the PCIE is connected to the CPU.

[0034] Optionally, the first calling module includes:

[0035] The first submodule is used to define an abstract SPI controller pointer in the private data structure of the FPGA board;

[0036] The second submodule is used to create an SPI controller using the registration code preset in the probe function code part of the FPGA board, and assign the SPI controller address to the SPI controller pointer;

[0037] The third submodule is used to initialize the internal data of the SPI controller;

[0038] The fourth submodule is used to use the spi_bitbang_start function to start the SPI bus to start working, so as to call the SPI driver.

[0039] Optionally, the CPU further includes:

[0040] The verification module is used to burn the FPGA board upgrade program into the SPI flash memory by operating the MTD block device, then use the MTD block device to read the burned upgrade program from the SPI flash memory, and compare the upgrade program with the upgrade program written into the SPI flash memory by the MTD block device to complete the upgrade program verification.

[0041] The FPGA board upgrade solution disclosed in the present invention loads the SPI driver and the MTD driver through a preset command during the operation of the CPU operating system; the PCIE device driver calls the preset registration code, registers the SPI controller to call the SPI driver; the SPI driver calls the MTD driver and connects the SPI flash memory; the MTD driver generates the corresponding MTD block device under the specified directory; the CPU operating system sends the FPGA board upgrade program to the MTD block device, and the MTD block device burns the FPGA board upgrade program into the SPI flash memory to complete the FPGA board upgrade. The FPGA board upgrade solution provided in the embodiment of the present application can realize the remote upgrade of the FPGA board by adding a small amount of code such as a preset registration code in the FPGA board driver. Since only a small amount of code is added, it has the advantages of short development cycle, high stability, and strong adaptability. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 It is a structural block diagram showing a FPGA board upgrade system in the prior art;

[0043] Figure 2 It is a structural block diagram showing another FPGA board upgrade system in the prior art;

[0044] Figure 3 is a schematic diagram showing the working mode of the FPGA board in an embodiment of the present application;

[0045] Figure 4 is a flowchart showing the steps of the FPGA board upgrade method of the embodiment of the present application;

[0046] Figure 5 It is a logic diagram showing the internal interconnection between the FPGA board and the PCIE of the embodiment of the present application;

[0047] Figure 6 is a schematic diagram showing the structure of an operating system according to an embodiment of the present application;

[0048] Figure 7 It is a structural block diagram of an FPGA board upgrade system according to an embodiment of the present application. DETAILED DESCRIPTION

[0049] In order to make the technical problems, technical solutions and advantages to be solved by the present invention more clear, a detailed description will be given below with reference to the accompanying drawings and specific embodiments.

[0050] In order to solve the above problems existing in the prior art, this application provides a remote upgrade solution for FPGA boards such as PCIE acceleration cards and acquisition cards. The solution is suitable for Figure 3 Remote upgrade of the FPGA board in the working mode shown. The FPGA board is connected to the CPU mainboard through the PCIE interface, and the CPU communicates with the FPGA board through the PCIE interface and controls the FPGA board. This application uses public and open source module resources (including IP cores integrated in the FPGA board development environment, standard drivers of the operating system, and open source software tools) on this PCIE architecture, and can realize the remote upgrade function by adding a small amount of code to the FPGA board driver. Among them, PCIE is the third generation I / O bus after ISA and PCI buses. The PCIE protocol is an end-to-end interconnection protocol. The CPU communicates with the FPGA board through PCIE, and the two comply with the PCIE protocol specification when communicating.

[0051] The FPGA board upgrade solution provided in the embodiment of the present application is described in detail below through specific embodiments and their application scenarios in conjunction with the accompanying drawings.

[0052] As attached Figure 4 As shown, the FPGA board upgrade method of the embodiment of the present application includes the following steps:

[0053] Step 101: During the operation of the CPU operating system, the SPI driver and the MTD driver are loaded through a preset command.

[0054] In this application, an "AXI_Quad_SPI" module is added to the FPGA software logic, which is a software module that comes with the software development tool. AXIQuad SPI (four-wire serial peripheral interface) is a serial communication interface that is widely used in FPGAs and other integrated circuits to connect SPI (serial peripheral interface) devices such as Flash memory. It supports single-wire, two-wire and four-wire modes. The more lines there are, the faster the data transmission speed. The "AXI_Quad_SPI" module is a module that comes with the software development tool.

[0055] like Figure 5As shown, a serial communication interface (such as an "AXI_Quad_SPI" module) is preset in the FPGA, and the serial communication interface is connected to the PCIE module through an AXI-based interconnection network, and the other end of the PCIE module is connected to the CPU, wherein the AXI interconnection network is provided by the AXI Interconnect module, and a PCIE module is provided in the FPGA for connecting to one end of the PCIE, and the other end of the PCIE is connected to the CPU. The "AXI_Interconnect module" connects the "PCIE module" to the "AXI_Quad_SPI" module, and the "AXI_Interconnect module" is a module that comes with the software development tool.

[0056] In actual use, you can use the Address Editor tool to assign addresses to the "AXI_Quad_SPI module". The starting address can be freely configured, and the address space can be 64K bytes. In the constraint file, constrain the pins of the "AXI_Quad_SPI module", including: spi_iso, spi_osi, spi_cs, spi_clk. The pin positions and voltages must be consistent with the circuit board design.

[0057] Figure 6 Schematic diagram of the operating system structure of the embodiment of the present application; Figure 6 As shown in the figure, the operating system is divided into a kernel layer and an application layer. The application layer interacts with the kernel layer through Shell commands. The application layer also includes mtd-utils, which is a set of tools for managing the MTD (Memory Technology Device, a storage device using a memory chip) subsystem. It provides a powerful storage device management function for the embedded operating system. The kernel layer of the operating system includes the MTD driver, the SPI (Serial Peripheral Interface, a serial peripheral device interface) driver, and the PCIE driver. Each driver is driven when the operating system starts.

[0058] An optional method of loading the SPI driver and the MTD driver by using a preset command during the operation of the CPU operating system may be: using an insmod command or a modprobe command to load the SPI driver and the MTD driver during the operation of the CPU operating system.

[0059] The "AXI_Quad_SPI" module can be further controlled through the SPI driver to access data in the SPI flash memory. The MTD driver can generate an MTD block device, which can trigger the operation of burning the FPGA board upgrade program into the SPI flash memory.

[0060] The insmod command can only load one specific device driver at a time and requires the specific address of the driver. An exemplary insmod command may be insmod drv.ko.

[0061] modprobe can load all dependent drivers into the kernel at once without adding the specific address of the driver, but the driver module needs to be installed in the manner of make modules_intall when installing the file system. An exemplary modprobe command may be modprobe drv.

[0062] Step 102: The PCIE device driver calls a preset registration code to register the SPI controller to call the SPI driver.

[0063] In the embodiment of the present application, a registration code is preset in the probe function code part of the FPGA board, and the registration code is used to register the SPI controller. After the SPI controller is registered, the communication link between the CPU, PCIE, FPGA board and SPI flash memory can be opened.

[0064] An optional method for a PCIE device driver to call a preset registration code and register an SPI controller to call an SPI driver may be:

[0065] First, define an abstract SPI controller pointer in the private data structure of the FPGA board;

[0066] That is, define a struct_spi_master pointer spimaster. struct_spi_master abstracts the controller hardware. In SoC, it refers to the internal SPI controller. When registering an SPI controller to the SPI core layer, such a structure variable needs to be provided.

[0067] Secondly, use the preset registration code in the probe function code section of the FPGA board to create an SPI controller and assign the SPI controller address to the SPI controller pointer;

[0068] The registration code can be the spi_alloc_master function. The prototype of the spi_alloc_master function is as follows:

[0069] struct_spi_master*spi_alloc_master(struct device*dev, unsigned size)

[0070] The parameter dev is the dev pointed to by the FPGA board, and size is the size of the struct_spi_master structure.

[0071] Again, initialize the internal data of the SPI controller;

[0072] Finally, use the spi_bitbang_start function to start the SPI bus and call the SPI driver.

[0073] Step 103: The SPI driver calls the MTD driver and connects to the SPI flash memory.

[0074] The SPI driver will call the MTD driver and automatically scan and load the connected SPI flash memory.

[0075] SPI Flash (SPI Flash) is a non-volatile memory chip based on the Serial Peripheral Interface (SPI) protocol. It is widely used in embedded systems and various portable devices. SPI Flash memory is widely used because of its small size, low cost, fast read and write speed, and strong durability. Figure 3 The memory shown in .

[0076] Step 104: The MTD driver generates a corresponding MTD block device in the specified directory.

[0077] In the actual implementation process, the MTD driver can automatically generate a corresponding MTD block device in the / dev directory, for example, it can be named "mtd0".

[0078] Step 105: The CPU operating system sends the FPGA board upgrade program to the MTD block device, and the MTD block device burns the FPGA board upgrade program into the SPI flash memory to complete the FPGA board upgrade.

[0079] It should be noted that the FPGA board upgrade method provided in this application can not only remotely update the FPGA board upgrade program in the SPI flash memory, but also store other key data in the SPI flash memory remotely by the CPU.

[0080] In an optional embodiment, after the MTD block device burns the FPGA board upgrade program into the SPI flash memory, the MTD block device can also be used to read the burned upgrade program from the SPI flash memory, and compare the read upgrade program with the upgrade program written into the SPI flash memory by the MTD block device to complete the upgrade program verification.

[0081] The verification can determine whether the upgrade program written into the SPI flash memory is accurate, thereby ensuring the reliability of the FPGA board program upgrade.

[0082] When the upgrade program verification result is an upgrade failure, the FPGA's MultiBoot technology can be used to implement upgrade failure rollback. If the upgrade fails, the program can be rolled back to the version before the upgrade, further improving system stability.

[0083] In an optional embodiment, when the FPGA board is successfully upgraded, hot loading can be implemented using technologies such as WarmBoot, and the program upgrade can be achieved without restarting the FPGA board.

[0084] In situations where security is high and the FPGA board cannot be connected to the outside world via Ethernet, the upgrade package can be copied through a USB flash drive, CD, etc. to achieve FPGA upgrade.

[0085] The FPGA board upgrade method provided in the embodiment of the present application, during the operation of the CPU operating system, loads the SPI driver and the MTD driver through a preset command; the PCIE device driver calls the preset registration code, registers the SPI controller to call the SPI driver; the SPI driver calls the MTD driver and connects the SPI flash memory; the MTD driver generates the corresponding MTD block device in the specified directory; the CPU operating system sends the FPGA board upgrade program to the MTD block device, and the MTD block device burns the FPGA board upgrade program into the SPI flash memory to complete the FPGA board upgrade. The FPGA board upgrade solution provided in the embodiment of the present application can realize the remote upgrade of the FPGA board by adding a small amount of code such as the preset registration code to the FPGA board driver. Since only a small amount of code is added, it has the advantages of short development cycle, high stability, and strong adaptability.

[0086] The following is a specific example to illustrate the FPGA board upgrade method of the embodiment of the present application.

[0087] This specific example provides a remote upgrade solution for FPGA boards such as PCIE accelerator cards and acquisition cards. This solution is suitable for Figure 3 Remote upgrade of the FPGA board in the working mode shown. The FPGA board is connected to the CPU mainboard through the PCIE interface, and the CPU communicates with the FPGA board through the PCIE interface and controls the FPGA board. In this specific example, on this PCIE architecture, by using public and open source module resources (including IP cores integrated in the FPGA board development environment, standard drivers of the operating system, and open source software tools), a small amount of code is added to the FPGA board driver to achieve the remote upgrade function.

[0088] FPGA board part:

[0089] Add the "AXI_Quad_SPI" module and "AXI_Interconnect" module to the FPGA board software logic, as shown in the attached Figure 5 As shown, the "AXI_Interconnect module" connects the "PCIE module" to the "AXI_Quad_SPI" module, and the "AXI_Interconnect module" also comes with the software development tool.

[0090] Use the Address Editor tool to assign addresses to the "AXI_Quad_SPI module". The starting address can be freely configured and the address space is 64K bytes.

[0091] In the constraint file, constrain the pins of the "AXI_Quad_SPI module", including spi_iso, spi_osi, spi_cs, and spi_clk. The pin positions and voltages should be consistent with the circuit board design.

[0092] The structural diagram of the operating system is as follows Figure 6 As shown, the operating system has been adjusted as follows:

[0093] In Linux-based operating systems, use the insmod or modprobe command to load the SPI and MTD drivers. Commonly used SPI Flashes are supported by the Linux kernel MTD driver, and the driver will scan the corresponding chip model to complete the loading.

[0094] The FPGA board driver has been adjusted as follows. When performing a remote upgrade of the FPGA board, perform the following operations:

[0095] Add the code for registering the SPI controller in the probe code section of the FPGA board;

[0096] The SPI driver will call the MTD driver and automatically scan and load the connected SPI Flash;

[0097] The MTD driver will automatically generate the corresponding MTD block device in the / dev directory, such as "mtd0";

[0098] By operating this block device, you can operate the SPI Flash and burn the upgrade program into the SPI Flash;

[0099] Use the tool to read the data in the SPI Flash and verify it.

[0100] The FPGA board upgrade method provided in the embodiment of the present application, on the one hand, utilizes the existing FPGA development environment IP core and operating system standard driver to reduce additional development work; on the second hand, it can realize the remote upgrade of the FPGA board, thereby improving the development efficiency and system stability; on the third hand, the method has good adaptability and can be widely used in different types of FPGA boards.

[0101] Figure 7 This is a structural block diagram of an FPGA board upgrade system for implementing an embodiment of the present application.

[0102] The FPGA board upgrade system provided in the embodiment of the present application includes: an FPGA board 702 and a CPU 703 interconnected by a PCIE 701, wherein the CPU 703 includes:

[0103] A loading module 7031 is used to load the SPI driver and the MTD driver through a preset command during the operation of the CPU operating system;

[0104] The FPGA board 702 includes:

[0105] The first calling module 7021 is used to call a preset registration code through a PCIE device driver to register an SPI controller to call the SPI driver;

[0106] The second calling module 7022 is used to call the MTD driver through the SPI driver and connect to the SPI flash memory;

[0107] A generation module 7023, used to generate a corresponding MTD block device in a specified directory through the MTD driver;

[0108] The CPU 703 also includes:

[0109] The sending module 7032 is used to send the FPGA board upgrade program to the MTD block device through the PCIE, and burn the FPGA board upgrade program into the SPI flash memory through the MTD block device to complete the FPGA board upgrade.

[0110] Optionally, the loading module is specifically used for:

[0111] During the operation of the CPU operating system, the SPI driver and the MTD driver are loaded using the insmod command or the modprobe command.

[0112] Optionally, a serial communication interface is preset in the FPGA, and the serial communication interface is connected to the PCIE module through an interconnection network based on the AXI protocol, and the other end of the PCIE module is connected to the CPU.

[0113] Optionally, the first calling module includes:

[0114] The first submodule is used to define an abstract SPI controller pointer in the private data structure of the FPGA board;

[0115] The second submodule is used to create an SPI controller using the registration code preset in the probe function code part of the FPGA board, and assign the SPI controller address to the SPI controller pointer;

[0116] The third submodule is used to initialize the internal data of the SPI controller;

[0117] The fourth submodule is used to use the spi_bitbang_start function to start the SPI bus to start working, so as to call the SPI driver.

[0118] Optionally, the CPU further includes:

[0119] The verification module is used to burn the FPGA board upgrade program into the SPI flash memory by operating the MTD block device, then use the MTD block device to read the burned upgrade program from the SPI flash memory, and compare the upgrade program with the upgrade program written into the SPI flash memory by the MTD block device to complete the upgrade program verification.

[0120] The embodiments of the present application provide Figure 7 The FPGA board upgrade system shown can achieve Figure 4 To avoid repetition, the various processes implemented by the method embodiment are not described here.

[0121] The FPGA board upgrade system provided in the embodiment of the present application loads the SPI driver and the MTD driver through a preset command during the operation of the CPU operating system; the PCIE device driver calls the preset registration code, registers the SPI controller to call the SPI driver; the SPI driver calls the MTD driver and connects the SPI flash memory; the MTD driver generates the corresponding MTD block device in the specified directory; the CPU operating system sends the FPGA board upgrade program to the MTD block device, and the MTD block device burns the FPGA board upgrade program into the SPI flash memory to complete the FPGA board upgrade. By adding a small amount of code such as the preset registration code to the FPGA board driver, the remote upgrade of the FPGA board can be realized. Since only a small amount of code is added, it has the advantages of short development cycle, high stability, and strong adaptability.

[0122] An embodiment of the present invention further provides an electronic device, including a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus.

[0123] Memory, used to store computer programs;

[0124] The processor is used to execute the program stored in the memory to implement the relevant operations performed by the CPU in the FPGA board upgrade method shown in the above method embodiment.

[0125] The communication bus mentioned in the above terminal can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The communication bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0126] The communication interface is used for communication between the above terminal and other devices.

[0127] The memory may include a random access memory (RAM) or a non-volatile memory, such as at least one disk memory. Optionally, the memory may also be at least one storage device located away from the aforementioned processor.

[0128] The above-mentioned processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

[0129] In another embodiment provided by the present invention, a computer-readable storage medium is also provided, which stores instructions. When the computer-readable storage medium is executed on a computer, the computer implements the steps executed by the CPU in the FPGA board upgrade method described in any of the above embodiments.

[0130] In another embodiment provided by the present invention, a computer program product containing instructions is also provided. When the computer is run on the computer, the computer implements the steps executed by the CPU in the FPGA board upgrade method described in any of the above embodiments.

[0131] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0132] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A method for upgrading an FPGA board, characterized in that: Applicable to a system where an FPGA board and a CPU are interconnected via PCIE, the method comprising: During the operation of the CPU operating system, the SPI driver and the MTD driver are loaded through a preset command; The PCIE device driver calls a preset registration code to register the SPI controller to call the SPI driver; The SPI driver calls the MTD driver and connects to the SPI flash memory; The MTD driver generates a corresponding MTD block device in a specified directory; The CPU operating system sends the FPGA board upgrade program to the MTD block device, and the MTD block device burns the FPGA board upgrade program into the SPI flash memory to complete the FPGA board upgrade.

2. The method according to claim 1, characterized in that During the operation of the CPU operating system, the steps of loading the SPI driver and the MTD driver through a preset command include: During the operation of the CPU operating system, the SPI driver and the MTD driver are loaded using the insmod command or the modprobe command.

3. The method according to claim 1, characterized in that A serial communication interface is preset in the FPGA, and the serial communication interface is connected to the PCIE module through an interconnection network based on the AXI protocol, and the other end of the PCIE module is connected to the CPU.

4. The method according to claim 1, characterized in that: The step of the PCIE device driver calling a preset registration code and registering the SPI controller to call the SPI driver includes: Defining an abstract SPI controller pointer in a private data structure of the FPGA board; Using the registration code preset in the probe function code part of the FPGA board, create an SPI controller, and assign the SPI controller address to the SPI controller pointer; Initializing the internal data of the SPI controller; Use the spi_bitbang_start function to start the SPI bus and call the SPI driver.

5. The method according to claim 1, characterized in that After the step of the MTD block device burning the FPGA board upgrade program into the SPI flash memory, the method further includes: The MTD block device is used to read the burned upgrade program from the SPI flash memory, and the upgrade program is compared with the upgrade program written into the SPI flash memory by the MTD block device to complete the upgrade program verification.

6. An FPGA board upgrade system, characterized in that: The system includes: an FPGA board and a CPU interconnected by PCIE, and the CPU includes: A loading module, used to load the SPI driver and the MTD driver through a preset command during the operation of the CPU operating system; The FPGA board includes: A first calling module is used to call a preset registration code through a PCIE device driver to register an SPI controller to call the SPI driver; A second calling module is used to call the MTD driver through the SPI driver and connect to the SPI flash memory; A generation module, used to generate a corresponding MTD block device in a specified directory through the MTD driver; The CPU also includes: The sending module is used to send the FPGA board upgrade program to the MTD block device through the PCIE, and burn the FPGA board upgrade program into the SPI flash memory through the MTD block device to complete the FPGA board upgrade.

7. The FPGA board upgrade system according to claim 6, characterized in that: The loading module is specifically used for: During the operation of the CPU operating system, the SPI driver and the MTD driver are loaded using the insmod command or the modprobe command.

8. The FPGA board upgrade system according to claim 6, characterized in that: A serial communication interface is preset in the FPGA, and the serial communication interface is connected to the PCIE through an interconnection network based on the AXI protocol, and the other end of the PCIE is connected to the CPU.

9. The FPGA board upgrade system according to claim 6, characterized in that: The first calling module includes: The first submodule is used to define an abstract SPI controller pointer in the private data structure of the FPGA board; The second submodule is used to create an SPI controller using the registration code preset in the probe function code part of the FPGA board, and assign the SPI controller address to the SPI controller pointer; The third submodule is used to initialize the internal data of the SPI controller; The fourth submodule is used to use the spi_bitbang_start function to start the SPI bus to start working, so as to call the SPI driver.

10. The FPGA board upgrade system according to claim 6, characterized in that: The CPU also includes: The verification module is used to burn the FPGA board upgrade program into the SPI flash memory by operating the MTD block device, then use the MTD block device to read the burned upgrade program from the SPI flash memory, and compare the upgrade program with the upgrade program written into the SPI flash memory by the MTD block device to complete the upgrade program verification.

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