Upper computer communication method, system, device and program

Abstract

The invention discloses an upper computer communication method, system, equipment and program. The method comprises the following steps: judging the number of data packets which can be received by a lower computer; wherein when the number of the data packets capable of being received reaches a preset standard, the lower computer turns over a datainready signal; when the upper computer detects that the datainready signal is overturned, the upper computer writes 1 into the datainstart register through the peripheral interface, and the upper computer starts to write data into the lower computer through the peripheral interface; when data writing is completed, the upper computer writes 1 to the dataintone register through the peripheral interface; when the lower computer detects that the upper computer writes 1 to the dataindone register, starting to process data; after the data processing of the lower computer is completed, a dataoutlay signal is turned over; and when the upper computer detects that the data output signal is overturned, the upper computer reads back data from the lower computer through the peripheral interface, and writes 1 to the data output register through the peripheral interface. Through the processing scheme disclosed by the invention, the acquisition speed of the chip state of the lower computer by the upper computer can be increased, and meanwhile, the occupation of the bandwidth of an external interface is reduced.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a host computer communication method, system, device and program. Background Art

[0002] When the lower computer and the upper computer communicate through the peripheral interface, the upper computer is usually the host and the lower computer is the slave. However, most peripheral slave interfaces cannot actively send requests to the upper computer, and the upper computer can only obtain the status of the lower computer by querying. This requires the CPU to continuously send read requests to the lower computer through the peripheral interface in order to obtain the status of the lower computer in time, resulting in a waste of CPU resources and peripheral interface bandwidth.

[0003] It can be seen that the above existing communication methods are still inconvenient and defective in use, and are in urgent need of further improvement. How to create a new host computer communication method has become a goal that the industry urgently needs to improve. Summary of the invention

[0004] In view of this, an embodiment of the present disclosure provides a host computer communication method, which at least partially solves the problems existing in the prior art.

[0005] In a first aspect, an embodiment of the present disclosure provides a host computer communication method, the method comprising the following steps:

[0006] Determine the number of data packets that can be received by the lower computer; wherein, when the number of receivable data packets reaches a preset standard, the lower computer flips the data_in_ready signal;

[0007] When the host computer detects that the data_in_ready signal flips, the host computer writes 1 to the data_in_start register through the peripheral interface, and the host computer starts to write data to the lower computer through the peripheral interface; when the data writing is completed, the host computer writes 1 to the data_in_done register through the peripheral interface;

[0008] When the lower computer detects that the upper computer writes 1 to the data_in_done register, it starts processing data; after the lower computer completes data processing, it flips the data_out_ready signal;

[0009] When the host computer detects that the data_out_ready signal flips, the host computer reads back the data from the slave computer through the peripheral interface and writes 1 to the data_out_done register through the peripheral interface.

[0010] According to a specific implementation manner of the embodiment of the present disclosure, the detection includes: software polling and / or double-edge interrupt detection.

[0011] According to a specific implementation of the embodiment of the present disclosure, the determining the number of data packets that can be received by the lower computer includes:

[0012] The number of data packets that can be received by the internal buffer is obtained based on a predetermined module in the lower computer; wherein the predetermined module includes: a programmable processor, a programmable counter and buffer detection hardware.

[0013] According to a specific implementation manner of the embodiment of the present disclosure, the method further includes: when the number of receivable data packets does not reach a preset standard, the lower computer only processes existing data packets and does not receive new data packets.

[0014] In a second aspect, an embodiment of the present disclosure provides a host computer communication method system, the system comprising:

[0015] The judging module is configured to judge the number of data packets that can be received by the lower computer; wherein, when the number of data packets that can be received reaches a preset standard, the lower computer flips the data_in_ready signal;

[0016] The write module is configured to write 1 to the data_in_start register through the peripheral interface when the host computer detects that the data_in_ready signal is flipped, and the host computer starts to write data to the lower computer through the peripheral interface; when the writing of data is completed, the host computer writes 1 to the data_in_done register through the peripheral interface; and,

[0017] When the lower computer detects that the upper computer writes 1 to the data_in_done register, it starts processing data; after the lower computer completes data processing, it flips the data_out_ready signal;

[0018] The readback module is configured to read back data from the slave computer through the peripheral interface when the host computer detects that the data_out_ready signal is flipped, and write 1 to the data_out_done register through the peripheral interface.

[0019] In a third aspect, an embodiment of the present disclosure further provides an electronic device, the electronic device comprising:

[0020] at least one processor; and,

[0021] a memory communicatively connected to the at least one processor; wherein,

[0022] The memory stores instructions that can be executed by the at least one processor. When the instructions are executed by the at least one processor, the at least one processor implements the host computer communication method described in any one of the first aspect or any one of the implementations of the first aspect.

[0023] In a fourth aspect, an embodiment of the present disclosure further provides a computer program product, wherein the computer program product includes a computer program stored on a non-transitory computer-readable storage medium, wherein the computer program includes program instructions, and when the program instructions are executed by a computer, the computer executes the host computer communication method in the aforementioned first aspect or any implementation method of the first aspect.

[0024] The host computer communication method in the disclosed embodiment communicates with the host computer through the mechanism of the peripheral interface and IO, and uses the peripheral interface to transmit data while using the IO of the lower computer to notify the host computer of the state change of the lower computer. The host computer processes the IO signal sent by the chip in an interrupt manner, which can increase the acquisition speed of the host computer to the chip state of the lower computer and reduce the occupation of the bandwidth of the peripheral interface. It can ensure that there will be no mis-transmission of data, duplication or missing of signals between the IO and the standard peripheral interface, and the reliability of data transmission can be guaranteed. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and specific implementation methods.

[0026] Figure 1 A schematic diagram of a host computer communication method flow chart provided in an embodiment of the present disclosure;

[0027] Figure 2 A schematic diagram of signal connection provided by an embodiment of the present disclosure for a lower computer to communicate with an upper computer through an external design interface and IO;

[0028] Figure 3 A schematic diagram of the system structure of a host computer communication method provided by an embodiment of the present disclosure; and

[0029] Figure 4 A schematic diagram of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0030] The embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0031] The following describes the embodiments of the present disclosure through specific examples, and those skilled in the art can easily understand other advantages and effects of the present disclosure from the contents disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. The present disclosure can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present disclosure.

[0032] It should be noted that various aspects of the embodiments within the scope of the appended claims are described below. It should be apparent that the aspects described herein may be embodied in a wide variety of forms, and any specific structure and / or function described herein is merely illustrative. Based on the present disclosure, it should be understood by those skilled in the art that an aspect described herein may be implemented independently of any other aspect, and two or more of these aspects may be combined in various ways. For example, any number of aspects described herein may be used to implement a device and / or practice a method. In addition, other structures and / or functionalities other than one or more of the aspects described herein may be used to implement this device and / or practice this method.

[0033] Additionally, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, it will be understood by those skilled in the art that the aspects described may be practiced without these specific details.

[0034] In some applications, when the host computer wants to send data to the lower computer, it is necessary to prevent data loss due to the lower computer's buffer being full. Therefore, the host computer needs to obtain the status of the lower computer, send data to the lower computer when there is enough space, and notify the lower computer to start processing the data. Then the host computer needs to obtain the status of the lower computer and read the data back after the lower computer has processed it.

[0035] In order to realize the status communication between the upper computer and the lower computer, the following single-bit registers are set in the lower computer for the upper computer to read and write through the peripheral interface:

[0036]

[0037] The existing technology performs a complete data transmission process completely through the peripheral interface as follows:

[0038] 1. Whenever there is enough space in the lower computer buffer to receive a packet of data, the lower computer flips the data_in_ready signal;

[0039] 2. The host computer queries the data_in_ready register through the peripheral interface until it detects that the register flips;

[0040] 3. The host computer writes 1 to the data_in_start register through the peripheral interface to notify the slave computer that it has detected the flip of data_in_ready and is about to start writing a packet of data;

[0041] 4. The upper computer writes a packet of data to the lower computer through the peripheral interface;

[0042] 5. The host computer writes 1 to the data_in_done register through the peripheral interface to notify the slave computer that the data has been written and can start processing the data;

[0043] 6. The lower computer detects that the upper computer writes 1 to the data_in_done register and starts processing data;

[0044] 7. After the lower computer processes the data, it flips the data_out_ready register;

[0045] 8. The host computer continuously queries the data_out_ready register through the peripheral interface and detects its flip;

[0046] 9. The upper computer reads back a packet of data from the lower computer through the peripheral interface.

[0047] 10. The host computer writes 1 to the data_out_done register through the peripheral interface to notify the slave computer that it has finished reading a packet of data.

[0048] In the communication between the upper computer and the lower computer, the lower computer usually cannot actively send its own status information to the upper computer through the peripheral interface, and the upper computer needs to constantly query the status of the lower computer through the peripheral interface. The upper computer constantly queries the data_in_ready register and data_out_ready register, which will occupy CPU resources and peripheral interface bandwidth.

[0049] Therefore, the present invention directly outputs the values ​​of the data_in_ready register and the data_out_ready register to the host computer through the lower IO, and the host computer can quickly obtain the status of the lower computer through software polling or double edge interrupt detection, thereby reducing the occupation of CPU resources and peripheral interface bandwidth.

[0050] Figure 1 A schematic diagram of the host computer communication method process provided in an embodiment of the present disclosure.

[0051] Figure 2 This is a signal connection diagram for the lower computer to communicate with the upper computer through the external design interface and IO.

[0052] like Figure 1 As shown, at step S110, the number of data packets that can be received by the lower computer is determined; wherein, when the number of receivable data packets reaches a preset standard, the lower computer flips the data_in_ready signal.

[0053] In an embodiment of the present invention, the determination of the number of data packets that the lower computer can receive includes: obtaining the number of data packets that the internal buffer can receive based on a predetermined module in the lower computer; wherein the predetermined module includes: a programmable processor, a programmable counter and buffer detection hardware.

[0054] More specifically, the number of data packets that can be received by the lower computer is determined based on a programmable processor (such as a CPU, a programmable algorithm core, etc.), a programmable counter, a specially designed buffer detection hardware, etc.

[0055] In an embodiment of the present invention, the method further includes: when the number of receivable data packets does not reach a preset standard, the lower computer only processes existing data packets and does not receive new data packets.

[0056] More specifically, the process proceeds to step S120.

[0057] At step S120, when the host computer detects that the data_in_ready signal flips, the host computer writes 1 to the data_in_start register through the peripheral interface, and the host computer starts to write data to the subordinate computer through the peripheral interface; when the data writing is completed, the host computer writes 1 to the data_in_done register through the peripheral interface.

[0058] In the embodiment of the present invention, the detection includes: software polling and / or double-edge interrupt detection.

[0059] Next, go to step S130.

[0060] In step S130, when the lower computer detects that the upper computer writes 1 to the data_in_done register, it starts processing data; when the lower computer completes data processing, it flips the data_out_ready signal.

[0061] Next, go to step S140.

[0062] At step S140 , when the host computer detects that the data_out_ready signal flips, the host computer reads back the data from the slave computer through the peripheral interface, and writes 1 to the data_out_done register through the peripheral interface.

[0063] More specifically, the present invention is described below by way of detailed examples.

[0064] The process of using peripheral interfaces and IO to perform a complete data transfer is as follows:

[0065] 1. The CPU of the lower computer records the number of data packets that can be received in the internal buffer. Whenever there is enough space in the buffer area of ​​the lower computer to receive a packet of data, the lower computer flips the data_in_ready signal;

[0066] 2. The host computer interrupt detects that the data_in_ready signal flips;

[0067] 3. The host computer writes 1 to the data_in_start register through the peripheral interface to notify the slave computer that it has detected the flip of data_in_ready and is about to start writing a packet of data;

[0068] 4. The upper computer writes a packet of data to the lower computer through the peripheral interface;

[0069] 5. The host computer writes 1 to the data_in_done register through the peripheral interface to notify the slave computer that the data has been written and can start processing the data;

[0070] 6. The lower computer detects that the upper computer writes 1 to the data_in_done register and starts processing data;

[0071] 7. After the lower computer processes the data, it flips the data_out_ready signal;

[0072] 8. The host computer interrupt detects that the data_out_ready signal flips;

[0073] 9. The upper computer reads back a packet of data from the lower computer through the peripheral interface.

[0074] 10. The host computer writes 1 to the data_out_done register through the peripheral interface to notify the slave computer that it has finished reading a packet of data.

[0075] To speed up data processing efficiency, the above process can be implemented in a pipeline manner. While the lower computer processes the data packet, the upper computer can read and write the data packet through the peripheral interface. The overall processing flow remains unchanged. The flip of the data_in_ready signal must meet the following two conditions at the same time:

[0076] 1. After the last register flip, the data_in_start register is written to 1 by the host computer;

[0077] 2. There is enough space in the lower computer buffer to receive data.

[0078] The flip of the data_out_ready signal must meet the following two conditions at the same time:

[0079] 1. After the last register flip, the data_out_done register is written to 1 by the host computer;

[0080] 2. There is enough data in the lower computer buffer for the upper computer to read.

[0081] Example:

[0082] Assume that the input buffer in the lower computer can store 2 packets of data, and the output buffer can store 2 packets of data.

[0083] At the beginning, the lower computer CPU records the number of packets that can be received in the input buffer as 2, and the number of packets in the output buffer as 0.

[0084] The CPU of the lower computer flips the data_in_ready signal to notify the upper computer that a packet of data can be written.

[0085] After the upper computer detects the flip of data_in_ready, it writes 1 to the data_in_start register through the peripheral interface to notify the lower computer that the flip of data_in_ready has been detected and a packet of data is about to be written;

[0086] The lower computer detects that the data_in_start register has been written, and the input buffer count decreases by 1 and becomes 1. Since the input buffer count is still greater than 0, the lower computer flips the data_in_ready register again to notify the upper computer that it can continue to write the next packet of data.

[0087] The host computer detects that the data_in_ready signal flips again, records this situation, and continues to write the next packet of data after the first packet of data is written.

[0088] The upper computer writes the first packet of data to the lower computer.

[0089] After the first packet of data is written, the host computer writes 1 to the data_in_done register through the peripheral interface.

[0090] After the lower computer detects that the data_in_done register is written to 1, it starts processing the first received data packet.

[0091] Since the data_in_ready signal flip has been detected before, the host computer writes 1 to the data_in_start register again through the peripheral interface.

[0092] The lower computer detects that the data_in_start register has been written, and the input buffer count decreases by 1 and becomes 0.

[0093] The upper computer writes the second packet of data to the lower computer.

[0094] After the second packet of data is written, the host computer writes 1 to the data_in_done register through the peripheral interface.

[0095] After the lower computer detects that the data_in_done register is written to 1, it can start processing the second packet of data after processing the first packet of data.

[0096] After the lower computer processes the first packet of data, the input buffer count increases by 1 and becomes 1. The output buffer count increases by 1 and becomes 1. Since the input buffer count is greater than 1, the lower computer flips the data_in_ready signal. Since the output buffer count is greater than 1, the lower computer flips the data_out_ready signal.

[0097] After the host computer detects that the data_out_ready signal flips, it starts reading the first packet of data.

[0098] The lower computer has processed the second packet of data, and the input buffer count increases by 1, becoming 2. The output buffer count increases by 1, becoming 2. Since the upper computer has not received a write to the data_in_start register, the data_in_ready signal does not flip. Since the upper computer has not received a write to the data_out_done register, the data_out_ready signal does not flip.

[0099] After the host computer finishes reading the first packet of data, it writes 1 to the data_out_done register through the peripheral interface to notify the slave computer that it has finished reading a packet of data.

[0100] The lower computer detects that the data_out_done register is written, and the output buffer count decreases by 1 and becomes 1. Since the output buffer count is greater than 1, the lower computer flips the data_out_ready signal.

[0101] After the host computer detects that the data_out_ready signal flips, it starts reading the second packet of data.

[0102] After the host computer finishes reading the second packet of data, it writes 1 to the data_out_done register through the peripheral interface to notify the slave computer that it has finished reading a packet of data.

[0103] The lower computer detects that the data_out_done register has been written, and the output buffer count decreases by 1 and becomes 0.

[0104] In data communication application scenarios, the standard peripheral interface is usually used in the communication between the host computer and the slave computer. The host computer performs status query and control by reading the register in the slave computer. The slave computer cannot actively initiate a request to the host computer, and it is not necessary in most applications. However, in special application scenarios, in scenarios with requirements for resource occupancy, interface bandwidth, response speed, etc., the slave computer needs to actively initiate a request to the host computer to reduce the CPU resources and communication interface bandwidth consumed by the host computer polling. Therefore, the present invention solves the above problem by introducing an additional IO, and provides a use process for the interaction between IO and the standard peripheral interface. The process can ensure that there will be no mis-transmission of data, duplication or missing of signals before IO and the standard peripheral interface, and the reliability of data transmission can be guaranteed.

[0105] Figure 3 The upper computer communication method system 300 provided by the present invention is shown, including a judgment module 310 , a writing module 320 and a reading back module 330 .

[0106] The judgment module 310 is used to judge the number of data packets that can be received by the lower computer; wherein, when the number of data packets that can be received reaches a preset standard, the lower computer flips the data_in_ready signal;

[0107] The write module 320 is used for when the host computer detects that the data_in_ready signal flips, the host computer writes 1 to the data_in_start register through the peripheral interface, and the host computer starts to write data to the lower computer through the peripheral interface; when the data writing is completed, the host computer writes 1 to the data_in_done register through the peripheral interface; and,

[0108] When the lower computer detects that the upper computer writes 1 to the data_in_done register, it starts processing data; after the lower computer completes data processing, it flips the data_out_ready signal;

[0109] The read-back module 330 is used for the upper computer to read back data from the lower computer through the peripheral interface when the upper computer detects that the data_out_ready signal is flipped, and to write 1 to the data_out_done register through the peripheral interface.

[0110] See also Figure 4 The present disclosure also provides an electronic device 40, which includes:

[0111] at least one processor; and,

[0112] a memory communicatively connected to the at least one processor; wherein,

[0113] The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the host computer communication method in the aforementioned method embodiment.

[0114] The embodiment of the present disclosure further provides a non-transitory computer-readable storage medium, which stores computer instructions, and the computer instructions are used to enable the computer to execute the host computer communication method in the aforementioned method embodiment.

[0115] The embodiment of the present disclosure also provides a computer program product, which includes a computer program stored on a non-transitory computer-readable storage medium. The computer program includes program instructions. When the program instructions are executed by a computer, the computer executes the host computer communication method in the aforementioned method embodiment.

[0116] Reference below Figure 4 , which shows a schematic diagram of the structure of an electronic device 40 suitable for implementing the embodiment of the present disclosure. The electronic device in the embodiment of the present disclosure may include, but is not limited to, mobile terminals such as mobile phones, notebook computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Figure 4 The electronic device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0117] like Figure 4 As shown, the electronic device 40 may include a processing device (e.g., a central processing unit, a graphics processing unit, etc.) 401, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 402 or a program loaded from a storage device 408 to a random access memory (RAM) 403. In the RAM 403, various programs and data required for the operation of the electronic device 40 are also stored. The processing device 401, the ROM 402, and the RAM 403 are connected to each other via a bus 404. An input / output (I / O) interface 405 is also connected to the bus 404.

[0118] Typically, the following devices may be connected to the I / O interface 405: input devices 406 including, for example, a touch screen, a touchpad, a keyboard, a mouse, an image sensor, a microphone, an accelerometer, a gyroscope, etc.; output devices 407 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; storage devices 408 including, for example, a magnetic tape, a hard disk, etc.; and communication devices 409. The communication device 409 may allow the electronic device 40 to communicate wirelessly or wired with other devices to exchange data. Although the electronic device 40 with various devices is shown in the figure, it should be understood that it is not required to implement or have all the devices shown. More or fewer devices may be implemented or have instead.

[0119] In particular, according to an embodiment of the present disclosure, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program contains program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from the network through the communication device 409, or installed from the storage device 408, or installed from the ROM 402. When the computer program is executed by the processing device 401, the above-mentioned functions defined in the method of the embodiment of the present disclosure are executed.

[0120] It should be noted that the computer-readable medium disclosed above may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program that may be used by or in combination with an instruction execution system, device or device. In the present disclosure, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, in which a computer-readable program code is carried. This propagated data signal may take a variety of forms, including but not limited to an electromagnetic signal, an optical signal, or any suitable combination of the above. The computer readable signal medium may also be any computer readable medium other than a computer readable storage medium, which may send, propagate or transmit a program for use by or in conjunction with an instruction execution system, apparatus or device. The program code contained on the computer readable medium may be transmitted using any suitable medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.

[0121] The computer-readable medium may be included in the electronic device, or may exist independently without being incorporated into the electronic device.

[0122] The computer-readable medium carries one or more programs. When the one or more programs are executed by the electronic device, the electronic device: obtains at least two Internet Protocol addresses; sends a node evaluation request including the at least two Internet Protocol addresses to a node evaluation device, wherein the node evaluation device selects an Internet Protocol address from the at least two Internet Protocol addresses and returns it; receives the Internet Protocol address returned by the node evaluation device; wherein the obtained Internet Protocol address indicates an edge node in a content distribution network.

[0123] Alternatively, the computer-readable medium carries one or more programs, and when the one or more programs are executed by the electronic device, the electronic device: receives a node evaluation request including at least two Internet Protocol addresses; selects an Internet Protocol address from the at least two Internet Protocol addresses; and returns the selected Internet Protocol address; wherein the received Internet Protocol address indicates an edge node in a content distribution network.

[0124] Computer program code for performing the operations of the present disclosure may be written in one or more programming languages, or a combination thereof, including object-oriented programming languages, such as Java, Smalltalk, C++, and conventional procedural programming languages, such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., through the Internet using an Internet service provider).

[0125] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present disclosure. In this regard, each square box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some implementations as replacements, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0126] The units involved in the embodiments described in the present disclosure may be implemented by software or hardware. The name of a unit does not limit the unit itself in some cases. For example, the first acquisition unit may also be described as a "unit for acquiring at least two Internet Protocol addresses".

[0127] It should be understood that various parts of the present disclosure may be implemented in hardware, software, firmware, or a combination thereof.

[0128] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present disclosure should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A host computer communication method, characterized in that: The method comprises the following steps: Determine the number of data packets that can be received by the lower computer; wherein, when the number of receivable data packets reaches a preset standard, the lower computer flips the data_in_ready signal; When the host computer detects that the data_in_ready signal flips, the host computer writes 1 to the data_in_start register through the peripheral interface, and the host computer starts to write data to the lower computer through the peripheral interface; when the data writing is completed, the host computer writes 1 to the data_in_done register through the peripheral interface; When the lower computer detects that the upper computer writes 1 to the data_in_done register, it starts processing data; after the lower computer completes data processing, it flips the data_out_ready signal; When the host computer detects that the data_out_ready signal flips, the host computer reads back the data from the slave computer through the peripheral interface and writes 1 to the data_out_done register through the peripheral interface.

2. The host computer communication method according to claim 1, characterized in that: The detection includes: software polling and / or double edge interrupt detection.

3. The host computer communication method according to claim 1, characterized in that: The determining the number of data packets that can be received by the lower computer includes: The number of data packets that can be received by the internal buffer is obtained based on a predetermined module in the lower computer; wherein the predetermined module includes: a programmable processor, a programmable counter and buffer detection hardware.

4. The host computer communication method according to claim 1, characterized in that: The method further includes: when the number of receivable data packets does not reach a preset standard, the lower computer only processes existing data packets and does not receive new data packets.

5. A host computer communication method system, characterized in that: The system comprises: The judging module is configured to judge the number of data packets that can be received by the lower computer; wherein, when the number of data packets that can be received reaches a preset standard, the lower computer flips the data_in_ready signal; The write module is configured to write 1 to the data_in_start register through the peripheral interface when the host computer detects that the data_in_ready signal is flipped, and the host computer starts to write data to the lower computer through the peripheral interface; when the writing of data is completed, the host computer writes 1 to the data_in_done register through the peripheral interface; and, When the lower computer detects that the upper computer writes 1 to the data_in_done register, it starts processing data; after the lower computer completes data processing, it flips the data_out_ready signal; The readback module is configured to read back data from the slave computer through the peripheral interface when the host computer detects that the data_out_ready signal is flipped, and write 1 to the data_out_done register through the peripheral interface.

6. An electronic device, characterized in that: The electronic device includes: at least one processor; and, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and when the instructions are executed by the at least one processor, the at least one processor executes the host computer communication method according to any one of claims 1 to 4.

7. A computer program product, characterized in that The computer program product includes a computer program stored on a non-transitory computer-readable storage medium, and the computer program includes program instructions. When the program instructions are executed by a computer, the computer executes the host computer communication method as described in any one of claims 1 to 4.

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