Chip built-in self-test memory grouping method based on BPPC algorithm

Abstract

The invention discloses a chip built-in self-test memory grouping method based on a BPPC algorithm, and belongs to the technical field of calculation, reckoning or counting. The method comprises the following steps: extracting memory file information, preprocessing, and storing in a memory information structure array; through a K-means + + algorithm, performing preliminary clustering on the memories according to the attributes of the memories; constructing a constraint relationship between the memories through distance constraint, and representing the constraint relationship by using a conflict matrix; a compatible memory group is decomposed into memory groups without a distance relation by using a vertex coloring problem model, the memory groups without a constraint relation are subjected to one-dimensional boxing by using an FFD method, a grouping condition is optimized by using a particle swarm algorithm, and the grouping condition is assigned to a corresponding controller. A BPPC algorithm and an MBIST test method are combined, and an optimal solution with the minimum number of controllers is sought under the limitation of the memory distance and the maximum power consumption. According to the method, a multi-stage optimization method and a multi-target method are adopted, so that the grouping result is more accurate.

Description

Technical Field

[0001] The invention belongs to the technical field of integrated circuits, and in particular relates to a chip built-in self-test memory grouping method based on a BPPC algorithm. Background Art

[0002] The testability of memory cells is an important issue in the DFT design of digital circuits. In digital chips of various sizes, especially in large-scale SOC, CPU, GPU, FPGA or AI-ASIC chips, memory cells of different sizes and functions and different ports are widely distributed. These memory cells are also scattered throughout the chip in physical space. At present, the industry usually uses the MBIST memory built-in self-test method to effectively test these memory cells.

[0003] MBIST circuits generally include a controller and a corresponding memory interface. The controller is responsible for generating corresponding test addresses, test data, read-write control and other memory function control signals according to the test algorithm, and passing these signals to the memory interface; the controller is also responsible for receiving feedback on the output data of the memory and comparing the output data. The MBIST controller structure used in the modern industry can realize one controller connection and multiple memories are tested simultaneously. Since the circuits inserted by DFT (including the MBIST controller and the test network linked to the controller) belong to auxiliary test circuits, in theory, under the premise of meeting the test coverage requirements, these circuits are used as little as possible in the design. The less they are used, the less extra chip area they occupy, and they have a higher cost-effectiveness ratio. Therefore, the shared MBIST method is the current and future mainstream design.

[0004] In actual chip design projects, there are many constraints that restrict grouping, such as area, test power consumption, timing, test algorithm, BIST structure, memory structure, etc. To obtain a better grouping result, it is necessary to comprehensively consider many aspects. Some of these constraints are mutually restrictive and need to be compromised to a certain extent. Conventional methods for dealing with this problem include using heuristic algorithms, etc., which have low program execution efficiency and are difficult to understand the memory grouping process. Summary of the invention

[0005] To achieve the above-mentioned purpose, the technical scheme of the present invention is as follows: The present invention aims to provide an MBIST built-in self-test memory grouping method based on a conflict-based bin packing problem algorithm, which allocates memory to a controller to reduce the area occupied by the auxiliary test circuit caused by DFT insertion. By reading the memory file provided by a chip design company, analyzing the memory parameters involved in the file, clustering and grouping are performed according to the constraints mentioned in the file, and finally outputting a separated list of all storage unit instances contained in the list file. By converting the complex memory grouping problem into a simple bin packing problem, it is beneficial to enhance the understanding of memory grouping; using a common greedy algorithm to solve the bin packing problem after conversion, compared with the traditional heuristic algorithm, it saves the more cumbersome parameter adjustment problem, and it has been proved that the algorithm has a polynomial time complexity, and the algorithm is simple, effective and easy to implement. The graph is represented in the form of an adjacency matrix, which further speeds up the execution efficiency of the program.

[0006] The present invention adopts the following technical scheme to achieve the above-mentioned invention object: a chip built-in self-test memory grouping method based on BPPC algorithm, comprising the following steps:

[0007] Step 1: extract built-in self-test memory parameter information and pre-process the data.

[0008] Step 2: Use an unsupervised learning algorithm to preliminarily group the memories according to their attributes.

[0009] Step 3: For each compatible memory group obtained in step 2, a constraint relationship between memories is constructed according to the distance and the relationship is represented by constructing a conflict graph.

[0010] Step 4: subdivide the compatible memory group into a plurality of compatible memory groups without internal conflict relationships according to the constraint relationship.

[0011] Step 5: Use the FFD method to pack the memory for testing and assign the memory to the corresponding controller.

[0012] Step six, use the particle swarm optimization algorithm to globally optimize the storage grouping and output the grouping results.

[0013] As an improvement of the present invention, the method of extracting and preprocessing the design memory file in step 1 is as follows:

[0014] Design a memory array to accommodate the memory attribute files in the chip design case, including the memory number, instance name, model, physical coordinates of the instance, clock domain, type, test algorithm, logical port, operation set, address bit width, power consumption, etc. Read from the memory design file and store it in the array, delete or supplement missing data, normalize or standardize numerical features, and encode categorical variables.

[0015] As an improvement of the present invention, in step 2, the memory is preliminarily grouped and clustered to obtain a compatible memory group as follows:

[0016] According to the memory information array extracted in step 1, the attributes except power consumption and distance are clustered using the K-means++ algorithm in unsupervised learning, and the memory is divided into multiple clusters to obtain preliminary clustering results.

[0017] As an improvement of the present invention, in step 3, a method of constructing a constraint relationship between memories according to the distance and expressing the relationship by constructing a conflict graph is as follows:

[0018] Establish an undirected conflict graph G(V,E), where the vertex set V represents the memory in the compatible group without internal constraints, and the edge set E represents the conflict relationship between the memories. i ,v j )∈E describes the vertex v i and v j The conflict relationship exists. The free vertices in the conflict graph, i.e., the free memories, will be processed in the subsequent program steps. The adjacency matrix is ​​used to represent the conflict graph. The physical distance and hierarchical distance between memories are calculated according to the memory information file.

[0019] As an improvement of the present invention, the method of step 4 of subdividing the compatible memory group into a plurality of compatible memory groups without internal conflict relationships according to the constraint relationship is:

[0020] Based on the vertex coloring problem model, the compatible memory groups without intrinsic constraints are subdivided into compatible memory groups without distance restriction constraints using a greedy algorithm according to the conflict graph and adjacency matrix between memories induced by memory distance restrictions in step three.

[0021] As an improvement of the present invention, the method of packaging the memory for testing in step 5 is as follows:

[0022] Using the First Fit Decreasing method, the power consumption of the compatible memory and control area without distance restrictions after the subdivision in step 4 is sorted in descending order, and the memory group is packed using the greedy algorithm. After the free memory is sorted in descending order, it is packed in the controller with remaining capacity first, and the rest are packed independently.

[0023] As an improvement of the present invention, the method of globally optimizing the grouping situation in step 6 is:

[0024] Use the particle swarm optimization algorithm to evaluate particles (memory allocation schemes) and establish the fitness function of particles according to the power consumption constraint and the number of controller groups. Search for the local optimal solution of the memory allocation scheme through multiple iterations, and finally approach the global optimal solution. Run the above program in the Ubuntu 22.04 operating system to output the memory grouping results.

[0025] Compared with the prior art, the beneficial effects of the present invention are:

[0026] (1) The present invention transforms the complex storage unit planning grouping problem in MBIST into a simple and intuitive bin packing problem model, and solves it using a greedy algorithm, thereby avoiding the complex parameter adjustment process of a common heuristic algorithm. The algorithm process is easy to understand and implement, and is suitable for processing large-scale memory data and for large-scale EDA software development.

[0027] (2) The present invention introduces a particle swarm optimization (PSO) algorithm to globally optimize the memory allocation scheme. Through multiple rounds of iterative searches by a particle swarm, the optimal memory allocation scheme can be found under multiple constraints. The particle swarm optimization algorithm can effectively reduce the number of controllers, optimize power consumption, and avoid conflicts between memories by defining a fitness function and comprehensively considering factors such as power consumption, the number of controllers, and memory conflicts. Particle swarm optimization can not only avoid the problem of local optimal solutions, but also accelerate the optimization process, ensuring that the final result reaches the optimal or approximately optimal solution under multiple objective constraints.

[0028] (3) Through the effective combination of K-means++ clustering, greedy algorithm and particle swarm optimization algorithm, the present invention significantly reduces the computational complexity in the memory grouping process. In the preliminary grouping stage, the K-means++ clustering algorithm improves the stability and computational efficiency of clustering by optimizing the selection of initial centers; in the group refinement stage, the greedy algorithm ensures conflict-free grouping through fast vertex coloring processing, reducing the amount of calculation in subsequent steps; finally, the particle swarm optimization algorithm further optimizes the allocation scheme through global search, avoiding redundant calculations and ensuring that the program can obtain the optimal solution within a reasonable time. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 It is a flow chart of a chip built-in self-test memory grouping method based on BPPC algorithm of the present invention;

[0030] Figure 2 It is a flow chart of the algorithm for solving the packing problem of memory band conflict relationship of the present invention;

[0031] Figure 3 It is the overall process flow chart of the present invention for solving the memory grouping;

[0032] Figure 4 It is a schematic diagram of the present invention using the FFD method to pack internal non-conflicting compatible memory groups and free memories. DETAILED DESCRIPTION

[0033] The present invention will be further explained below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the following specific embodiments are only used to illustrate the present invention and are not used to limit the scope of the present invention.

[0034] Example: Figure 1 As shown, in the following description, many specific details are elaborated to facilitate a full understanding of the present invention, but the present invention can also be implemented in other ways different from those described herein, and those skilled in the art can make similar generalizations without violating the connotation of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed below.

[0035] The present invention will be further described below in conjunction with the accompanying drawings. Figure 1 As shown, it includes S1 to S5.

[0036] S1. By reading the case memory type model, memory name name, physical coordinates x, y, and clock clock, the basic storage information of the chip is obtained from the above reading process, and the specific types used in the case are clarified. On this basis, only the related files of these types are read to reduce the time of invalid reading. Read the lvlib file to obtain type, algorithm, logicalAddressMaP, logicalPorts, operationSet, shadow, and possible MilliWattsPerMegaHertz. If this condition is not met, if there is a .summ file, the power in the file shall prevail; if the above two conditions do not match, the power consumption information of the target can be searched in the *.ds file. Check whether there are missing attribute values. If there are fewer missing fields, delete them directly; if there are more missing fields, fill them. Normalize the attributes such as physical coordinates: Standardize properties such as power consumption and address width: Encode the attribute value. In the above parameters, X is the attribute feature value, X max is the maximum eigenvalue of the attribute, X min is the minimum eigenvalue. μ is the mean of the eigenvalue, and σ is the standard deviation of the eigenvalue.

[0037] S2. According to the relevant attributes obtained by extracting memory information, the attributes other than distance and power consumption, such as type and address width, are also grouped and clustered by K-means++. A cluster center is randomly selected and the distance D(x i ), calculate the probability of each point being selected as the cluster center next time: Select the point with the highest probability as the next clustering center. The objective function of clustering is to minimize the square error within the cluster: where c i represents the i-th cluster; x j represents the jth data point, i.e., the attribute of a memory in the data set; μ i In order to obtain the appropriate grouping, the total square error under different cluster numbers is calculated and its change curve is plotted to find the point where the error drops sharply. The K value corresponding to this point is generally the optimal number of compatible memory groups.

[0038] S3. First, we need to determine the conflict relationship of the memories based on the distance and use a conflict graph to represent this relationship. The conflict graph G(V,E) is an undirected graph, whose vertex set V represents the memories in the compatible group, and the edge set E represents the conflict relationship between memories. i and v j When there is a conflict relationship between the memories represented by (v i ,v j )∈E. The degree of all vertices in set V is greater than 0. Vertices with degree 0 (hereinafter referred to as free vertices) will be processed separately in the subsequent procedures, that is, V = {v i |deg(v i )>0}. The conflict graph is described by an N×N adjacency matrix D, where the matrix element m ij It can be expressed by formula (1).

[0039]

[0040] When the .def file exists, the distance between memories is expressed as physical distance. The matrix elements within the distance constraint are 0, and the matrix elements outside the distance constraint are 0, which is expressed by formula (2). ij Represents the physical distance between memories, d max(phy) Indicates the upper limit of physical distance.

[0041]

[0042] When the .def file does not exist, the distance between memories is expressed as hierarchical distance, and the matrix elements are represented in the same way as above.

[0043] S4. Input the conflict graph G(V,E), let U be the set of uncolored vertices, C k is the set of vertices assigned to color k. During initialization, set U=V, and the color number k is initially 0. The program selects an uncolored vertex from U each time and assigns it color k. When assigning colors, give priority to vertices with the least current conflicts to ensure that the coloring process reduces conflicts as much as possible. Once the color k of the vertex is determined, the vertex is removed from the uncolored set U and added to the corresponding color set. Subsequently, the program will continue to select the remaining uncolored vertices and repeat this process. After each color assignment, k increases by 1, indicating the start of the next round of coloring. This process continues until all vertices are colored. Finally, all vertex sets V are divided into several subsets C0, C1,…, C q-1 , where q is the minimum number of colors required. Each subset C k Contains all vertices assigned to color k, and there is no color conflict between vertices. Through this process, all conflicting relationships in the graph are effectively resolved.

[0044] S5. Use the FFD (First Fit Decreasing) method to solve the one-dimensional packing problem for each item in the collection, and use the PSO (Particle Swarm Optimization) method to optimize. Use the quick sort algorithm to sort the memory power consumption in descending order, and create a new memory group to store the packed results. For each memory, put it into the first controller group that can accommodate it. If the memory can be placed in an existing group, put it in the earliest group that can accommodate it. Otherwise, create a new group and put the memory in it, and repeat the above steps until all items are packed. Use the quick sort algorithm to sort the group's remaining power consumption and the memories that do not conflict with other memories in descending order and pack them according to the above steps.

[0045] S6. Abstract the memory allocation scheme into particles, and the particle position vector contains the memory allocation information. Establish the fitness function: f(p) = α·number of controller groups + β·power consumption error + γ·conflict penalty, where α, β and γ are weight coefficients. The particle adjusts its search direction according to the current speed and position, searching towards a better solution. The update formula is:

[0046] v i (t+1)=ωi·v i (t)+c1·r1·(p best -x i )+c2·r2·(g best -x i )(3)

[0047] x i (t+1)=x i (t)+v i (t+1)(4)

[0048] Among them, v i (t) is the velocity of the particle, x i (t) is the position of the particle, that is, the allocation scheme of the memory. ω is the inertia weight, that is, the degree of velocity retention. c1 and c2 are acceleration factors, which control the weight of the particle when approaching the individual optimal solution and the global optimal solution respectively. r1 and r2 are two random numbers. p best and q best They are the individual optimal solution and the global optimal solution of the particle respectively. The particle swarm will iterate multiple times according to the fitness function and position update rule until the fitness convergence threshold is reached. The optimal memory grouping scheme is output.

[0049] It should be noted that the above content only illustrates the technical idea of ​​the present invention and cannot be used to limit the protection scope of the present invention. For ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principle of the present invention. These improvements and modifications all fall within the protection scope of the claims of the present invention.

Claims

1. A chip built-in self-test memory grouping method based on BPPC algorithm, characterized in that: The method comprises the following steps: Step 1, extracting built-in self-test memory parameter information and preprocessing the data; Step 2: Preliminary grouping of memories using an unsupervised learning algorithm based on memory attributes; Step 3, for each compatible memory group obtained in step 2, a constraint relationship between memories is constructed according to the distance and the relationship is represented by constructing a conflict graph; Step 4, subdividing the compatible memory group into a plurality of compatible memory groups without internal conflict relationships according to the constraint relationship; Step 5: Use the FFD method to pack the memory for testing and assign the memory to the corresponding controller; Step six, use the particle swarm optimization algorithm to globally optimize the storage grouping and output the grouping results.

2. A chip built-in self-test memory grouping method based on BPPC algorithm according to claim 1, characterized in that: Design a memory array to accommodate the memory attribute file in the chip design case, read from the memory design file and store it into the array, delete or supplement missing data, normalize or standardize numerical features, and encode categorical variables.

3. A chip built-in self-test memory grouping method based on BPPC algorithm according to claim 2, characterized in that: The memory attribute file includes the memory number, instance name, model, physical coordinates of the instance, clock domain, type, test algorithm, logical port, operation set, address bit width and power consumption.

4. The chip built-in self-test memory grouping method based on BPPC algorithm according to claim 1, characterized in that: The method of grouping and clustering the memories in step 2 to obtain a compatible memory group is as follows: according to the memory information array extracted in step 1, the attributes other than power consumption and distance are clustered using the K-means++ algorithm in unsupervised learning, the memories are divided into multiple clusters, and a preliminary clustering result is obtained.

5. The chip built-in self-test memory grouping method based on BPPC algorithm according to claim 1, characterized in that: The method of step 3 constructing the constraint relationship between memories according to the distance and expressing the relationship by constructing a conflict graph is as follows: establishing an undirected conflict graph G(V,E), where the vertex set V represents the memories in the compatible group without internal constraints, and the edge set E represents the conflict relationship between memories, using (v i ,v j )∈E describes the vertex v i and v j The existing conflict relations, the free vertices in the conflict graph, i.e., the free memories, will be processed in the subsequent program steps. The adjacency matrix is ​​used to represent the conflict graph, and the physical distance and hierarchical distance between memories are calculated according to the memory information file.

6. The chip built-in self-test memory grouping method based on BPPC algorithm according to claim 1, characterized in that: The method of step 4 for subdividing the compatible memory group into several compatible memory groups without internal conflict relationships according to the constraint relationship is: based on the vertex coloring problem model, according to the conflict graph and adjacency matrix between memories induced by the memory distance restriction in step 3, the compatible memory without internal constraints is subdivided into compatible memory groups without distance restriction constraints using a greedy algorithm.

7. The chip built-in self-test memory grouping method based on BPPC algorithm according to claim 1, characterized in that: The method for packing the test memory in step 5 is as follows: using the First Fit Decreasing method, the compatible memories without distance restrictions and the control area power consumption subdivided in step 4 are arranged in descending order, the memory groups are packed using a greedy algorithm, and after the free memories are sorted in descending order, the packing is completed first in the controller with remaining capacity, and the rest are packed independently.

8. The chip built-in self-test memory grouping method based on BPPC algorithm according to claim 1, characterized in that: The particle swarm optimization algorithm is used to evaluate particles and establish the fitness function of particles according to the power consumption constraint and the number of controller groups. The local optimal solution of the memory allocation scheme is searched through multiple iterations, and finally the global optimal solution is approached, and the memory grouping result is output.

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