Simulation circuit intelligent design method based on process and post-simulation optimization feedback

Abstract

The invention provides an intelligent design method of an analog circuit based on process and post-simulation optimization feedback, and belongs to the field of multi-objective optimization of circuit design. The method comprises three processes: a circuit diagram optimization process, a layout optimization process and a device process optimization process. In the circuit diagram optimization process, parameters of circuit components are optimized by using a GLAL-MOPSO algorithm; in the layout optimization process, on the basis of a GLAL-MOPSO algorithm, a decision variable grouping strategy is designed to cope with the optimization problem of large-scale variables in layout optimization; in order to increase the optimization range of the circuit design, a device process optimization process is added in the circuit optimization process. In the process optimization process, parameters of a device process are optimized by using a GLAL-MOPSO algorithm, and a circuit diagram and a layout can be optimized again on the basis of a result obtained in the device process optimization process. According to the method, automatic optimization iteration is carried out on analog circuit design and device process optimization, so that the time cost and the manual design cost are saved, and the circuit design efficiency is effectively improved.

Description

Technical Field

[0001] The present invention belongs to the fields of electronic design automation, analog circuit design, semiconductor device manufacturing process, simulation technology, and multi-objective optimization technology, and mainly relates to an analog circuit intelligent design method based on process and post-simulation optimization feedback. Background Art

[0002] Electronic Design Automation (EDA) refers to a set of computer-aided tools used to design, verify and implement integrated circuits (ICs) and electronic systems. EDA tools scientifically and effectively integrate databases, computational mathematics, graph theory, graphics, topological logic, optimization theory, etc., which can greatly improve the efficiency, accuracy and complexity processing capabilities of electronic design.

[0003] Analog circuit design is a complex technical field that mainly involves the design of circuits that use continuous voltage or current signals to process information. Analog circuit design usually requires the experience of designers and is optimized through repeated simulation and testing. The difficulty of analog circuit design lies in the need to compromise between multiple factors such as speed, power consumption, gain, accuracy, power supply voltage, noise, area, etc., and analog circuits are more sensitive to noise and interference than digital circuits. Therefore, modern complex analog circuit design is a time-consuming and labor-intensive process that requires the frequent participation of highly skilled designers.

[0004] Semiconductor device manufacturing technology is the process technology for processing semiconductor materials into devices with specific electronic functions (such as transistors, diodes, and integrated circuits). This field involves a variety of technologies, including materials science, microelectronics, chemical engineering, etc. Optimizing the manufacturing process is a crucial step in the semiconductor industry. The optimization targets such as junction depth, material thickness, concentration, sheet resistance, etc. are aimed at improving device performance while increasing manufacturing efficiency and reducing costs. Key parameters in the process such as doping concentration, temperature, time, etc. will directly affect the performance of semiconductor devices. Technicians use TCAD (Technology Computer-Aided Design) simulation to gradually adjust these parameters, observe the impact on device characteristics, and find the best parameter combination. Summary of the invention

[0005] The object of the present invention is to provide an analog circuit intelligent design method based on process and post-simulation optimization feedback. A global-local adaptive learning multi-objective particle swarm algorithm (GLAL-MOPSO) is used to automatically call the EDA simulation tool, and the circuit diagram and layout of the analog circuit are optimized according to the results of the pre- and post-simulations to meet the design requirements, and a strategy for grouping decision variables is designed for the large-scale decision variable problem in layout optimization, which effectively improves the efficiency of circuit optimization. If the circuit diagram and layout are difficult to meet the design requirements or do not meet the constraints under the current device process, the device process is optimized according to the simulation results, and similar to the circuit optimization process, the GLAL-MOPSO algorithm is used to automatically call the TCAD simulation tool to optimize the device performance, and finally automatically design an analog circuit that meets the target. The present invention integrates the design optimization and device process optimization of analog circuits into a system, which is used to assist or even replace manual design work, and effectively improves the design efficiency of analog circuits. In order to solve the technical problems that analog circuit equipment in the prior art is time-consuming and labor-intensive, and requires frequent participation of high-tech talents.

[0006] In order to realize the above technology, the present invention comprises the following steps:

[0007] S1: Input the circuit diagram to be optimized. The circuit diagram adopts the initial device process and specifies the number, type, and connection method of the circuit components. Enter the circuit diagram optimization process.

[0008] S2: Inputting algorithm parameters and index requirements of the circuit diagram optimization process, and initializing the circuit diagram optimization algorithm according to the algorithm parameters, index requirements and circuit diagram, specifically including the following steps:

[0009] S21: Initialize the parameters of the circuit diagram optimization algorithm, the parameters including the initialization population size , the dimension of the solution , Iterations , number of targets .

[0010] S22: Randomly generate an initial solution set, initialize the objectives and constraints of the circuit diagram optimization algorithm. The optimization requirements in the circuit diagram optimization process generally include: total current, signal-to-noise ratio, harmonic loss, gain, bandwidth, power consumption, common mode rejection ratio, noise factor, etc. Select one or more simulation indicators to be optimized from the optimization index requirements as the optimization target, and select other simulation indicators of interest as constraints. For example, noise factor, power consumption and harmonic loss can be used as optimization targets, bandwidth and signal-to-noise ratio can be used to determine a range as inequality constraints, and total current can be used to determine a value as an equality constraint.

[0011] Taking the minimization multi-objective optimization problem as an example, a The multi-objective optimization problem with a dimensional objective function can be defined as follows:

[0012] min f(x)=[ f 1 x ,…, f i x …, f M (x)]

[0013] And satisfy the inequality constraints g(x)= [ g 1 x ,…, g i x …, g p (x)] and equality constraints , where for each and satisfy:

[0014]

[0015]

[0016] in, yes dimensional decision vector, representing a set of circuit device parameters, is the target number, and is the number of constraints; represents the optimization objective; Indicates An optimization goal, and Respectively represent The inequality constraints and In the process of multi-objective circuit diagram parameter optimization, two solutions may not be directly comparable. The optimal solution to the problem is composed of a set of Pareto optimal solutions, which are defined by the Pareto dominance relationship. and , if it satisfies:

[0017]

[0018] but Pareto dominance , recorded as If a solution is not dominated by any feasible solution, it is called a non-dominated solution. All non-dominated feasible solutions become a non-dominated solution set. In the initialization phase of the algorithm, a non-dominated solution set is calculated based on the initial solution set and continuously updated in iterations. The ideal result of the circuit diagram optimization process is a Pareto non-dominated solution set. .

[0019] S23: Parameters of the front simulator are configured to ensure good communication between the circuit diagram optimization algorithm and the front simulator.

[0020] Specifically, the parameter configuration includes the selection of simulation type, setting of ports and test points, time step, simulation time, temperature setting, etc.

[0021] S3: The circuit diagram optimization process uses the global-local adaptive learning multi-objective particle swarm optimization (GLAL-MOPSO) algorithm to efficiently solve and update the population. The specific steps of the GLAL-MOPSO algorithm are as follows:

[0022] S31: Select a part of the solutions in each sub-region of the target space as the local best solution (local best, lBest), and let some particles learn from the local best solution, which will explore each local region more efficiently. For this purpose, a local optimal solution archive is maintained. A local optimal solution represents the optimal solution in a local region. A series of uniformly distributed reference vectors are predefined in the target space, and then the distance between each solution and all reference vectors in the non-dominated solution set is calculated:

[0023]

[0024] in, Indicates non-dominated solution to The distance between the reference vectors, represents the first A solution, is the first in the set of non-dominated solutions The target value of a solution. Indicates A reference vector, represents the non-dominated solution set, is the number of reference vectors, Denotes the norm. Symbol Represents the vector cross product. It’s the ideal point.

[0025] Ideal point Calculated as follows:

[0026] z * =[ z 1 * ,… z t * ,… z M * ]

[0027]

[0028] in, Indicates the ideal point No. Dimensions, ideal point The dimension is equal to the number of targets , represents the non-dominated solution set, Non-dominated solution set The solution in Representation solution No. Optimize the target value.

[0029] Each reference vector selects a distance The smallest non-dominated solution is taken as the local optimal solution of the local area. Reference vector The selected local optimal solution is calculated as follows:

[0030]

[0031] represents the local optimal solution, It is the distance The corresponding non-dominated solutions; Represents the size of the non-dominated solution set. A non-dominated solution can be selected by multiple reference vectors at the same time, but it is only counted once, that is, the number of solutions in the local optimal solution set is less than or equal to the number of reference vectors. Calculate the Euclidean distance between each solution in the population and each local optimal solution in the target space, and select the nearest local optimal solution to match it.

[0032] S32: Select the convergence global optimal solution (convergence gBest, c_gBest) and the diversity global optimal solution (diversity gBest, d_gBest). During the evolution process, particles select different types of global optimal solutions or the local optimal solutions mentioned above for learning according to the evolutionary state.

[0033] The convergence global optimal solution is to guide the population to converge quickly, so it is defined as the distance from the ideal point The nearest nondominated solution:

[0034]

[0035] in, represents the convergence global optimal solution, is a non-dominated solution set, Indicates non-dominated solutions, Indicates Non-dominated solutions The target value and ideal point The Euclidean distance of .

[0036] The purpose of the diversity global optimal solution is to guide the population to a sparse space, count the number of particles matched by each local optimal solution, and use this to indicate the degree of crowding in the area. The sparsest local optimal solution with the least number of matching particles is selected as the diversity global optimal solution:

[0037]

[0038] in represents the global optimal solution of diversity, Indicates A local optimal solution, represents the number of local optimal solutions, Indicates Local optimal solution The number of matching particles. The fewer the number of matching particles, the lower the exploration degree of the area. Particles can be guided to learn from unexplored areas to improve the diversity of the population.

[0039] S33: A particle evolution state evaluation mechanism is used to allow particles to adaptively select learning targets based on their evolution state. Particles are evaluated from two aspects: the exploration value of the current flight direction (VFD) and the crowding in the local area (CLA). The exploration value of the current flight direction VFD(x) is calculated by the current target value of the particle and the target value of the previous generation:

[0040]

[0041] in, Represents particles Currently in The difference between the optimization objective function value and the previous generation is recorded as -1 if it decreases or remains unchanged, otherwise it is recorded as 1. Indicates Generation of particles, Indicates Generation of particles, Table The first generation of particles The optimized objective function value, Indicates The first generation of particles Optimize the objective function value. Then Sum and get the exploration value index of the current flight direction :

[0042]

[0043] Crowding index of local area Measured with particles The number of particles in the same local area, that is, the number of particles The number of particles matching the same local optimal solution:

[0044]

[0045] In the formula is the size of the population, Represents a counter, which counts once when the condition in the brackets is met. is a particle in the population, Is the population except Other particles besides The larger the value, the more crowded the particles in the area are.

[0046] S34: Local optimal solution according to definition , convergence global optimal solution and diversity global optimal solution , and the exploration value of the current flight direction and the local area congestion index , select learning objectives and parameter adjustments for particle adaptation.

[0047] First, define a general form of the GLAL-MOPSO algorithm velocity update formula:

[0048]

[0049] in, Indicates The velocity of the particle in the iteration, Indicates The velocity of the particle in the iteration, Indicates The position of the particle at the iteration, - is a random number on [0,1], and - are the inertia weight coefficient and the acceleration coefficient, represents the best historical position of the particle, represents the local optimal solution corresponding to the particle, represents the global optimal solution of diversity, Represents the convergence global optimal solution, which is updated as the algorithm iterates. The position of the particle at iteration The update formula is:

[0050]

[0051] Particles adaptively adjust learning objectives and parameters according to the evolutionary state to achieve a global-local adaptive learning strategy.

[0052] First case: and .when , indicating that the current speed direction of the particle can reduce most target values, and it is worthwhile to continue flying in the current direction. In this case, the inertia weight parameter can be appropriately increased. If at the same time , indicating that the local area where the particles are located is relatively sparse, which increases the local learning ability of the particles and reduces the global learning ability. Therefore, we set , , , , .in Indicates that in the range [ ]Uniformly distributed random numbers, The expected value of is 0.45, and random numbers within a certain range are used to enhance the diversity of the population. At this time, the speed update formula becomes:

[0053]

[0054] The second case: If and , indicating that the particle's current velocity direction is worth exploring but the local area is relatively crowded. The probability of is updated according to the following formula, otherwise it is updated according to the first case.

[0055]

[0056] Right now , , the inertia weight coefficient and the two acceleration coefficients are set as follows, similar to the first case, that is , , .

[0057] The third case: and .when , indicating that the current speed direction of the particle makes most of the target values ​​rise. If the particle continues to fly in the current direction, the target value may become worse. In this case, the inertia weight parameter should be reduced. If at the same time , indicating that the local area where the particles are located is relatively sparse, which can increase the ability of local learning of particles and at the same time learn to converge to the global optimum to accelerate the decrease of particle target value. At this time, the speed update formula is:

[0058]

[0059] Right now , and All set to , which is different from the previous two cases is , the expected value is 0.15.

[0060] The fourth case: If and , indicating that the current velocity direction of the particle lacks exploration value and the local area is relatively crowded, and it may fall into the local optimum. The ability of global learning should be increased. The probability of is updated according to the following formula, otherwise it is updated according to the third case.

[0061]

[0062] Right now , the inertia weight coefficient and the three acceleration coefficients are set as follows, similar to the third case, namely , and All set to .

[0063] S35: Send the solution set to the front simulator, which obtains the simulation index of each solution through simulation calculation and sends it back to the circuit diagram optimization algorithm, and calculates the optimization target value of each solution based on the obtained simulation indexes. and constraint value , , update the non-dominated solution set and local optimal solution , convergence global optimal solution , Diversity Global Optimal Solution and the best historical position of the particle .

[0064] S36: Repeat S31 to S35 until the optimization exit condition is met. If the solution set after the optimization does not meet the optimization constraint conditions, the device process optimization process S4-S6 is performed, otherwise the solution set of the circuit diagram optimization process is output and S7 is executed.

[0065] S4: According to the degree of constraint violation of the solution set after circuit diagram optimization, modify or set the index requirements of device process optimization. Enter the device process optimization process.

[0066] In order to increase the optimization scope of circuit design and prevent the circuit diagram and layout from being optimized multiple times and still failing to meet the desired goal or constraint, the present invention adds a device process optimization process to the circuit optimization process. When the circuit diagram fails to meet the constraint after multiple optimizations, the device process parameter optimization is performed.

[0067] S5: Input algorithm parameters and index requirements of the device process optimization process, and initialize the process optimization algorithm according to the algorithm parameters and index requirements, which specifically includes the following steps:

[0068] S51: Initialize the parameters of the process optimization algorithm, including the initialization population size , the dimension of the solution , Iterations and target number wait.

[0069] S52: Initialize the goals and constraints of the process optimization algorithm. The optimization requirements in the process simulation are usually the extracted process results, which generally include: junction depth, material thickness, doping concentration, etching depth, sheet resistance, breakdown field strength, contact resistance, etc. Select one or more simulation indicators to be optimized from the optimization indicator requirements as the optimization target, and other simulation indicators of interest can be selected as constraints. For example, sheet resistance, breakdown field strength, and contact resistance can be used as optimization targets, junction depth and material thickness can be used to determine a range as inequality constraints, and doping concentration and etching depth can be used to determine a value as equality constraints.

[0070] S53: Parameters of the process simulator are configured to ensure good communication between the process optimization algorithm and the process simulator.

[0071] Specifically, the parameter configuration includes simulation type, process flow setting, grid setting, etc.

[0072] S6: The process optimization process uses the GLAL-MOPSO algorithm to efficiently iterate and optimize the process parameters. The specific steps are as follows:

[0073] S61: The method for updating the population calculation is consistent with the steps described in S31-S34.

[0074] S62: Send the solution set to the process simulator, which obtains the simulation index of each solution through simulation calculation and sends it back to the process optimization algorithm, and calculates the target value of each solution based on the obtained simulation indexes. and constraint value , , update the non-dominated solution set and local optimal solution , convergence global optimal solution , Diversity Global Optimal Solution and the best historical position of the particle .

[0075] S63: Repeat S61-S62 until the optimization exit condition is met, output the optimized process, update it to the circuit diagram optimization process and re-execute S2-S3.

[0076] S7: A solution that satisfies the constraints and has an excellent optimization target value is selected from the non-dominated solution set output by the circuit diagram optimization process as an elite solution. This elite solution is used as the initial circuit diagram of the layout optimization process. It can be used to generate an initial layout and enter the layout optimization process.

[0077] S8: Input the algorithm parameters and index requirements of the layout optimization process, and initialize the layout optimization algorithm according to the algorithm parameters, index requirements and elite solutions obtained by circuit diagram optimization, which specifically includes the following steps:

[0078] S81: Initialize parameters of the layout optimization algorithm, including initialization population size , the dimension of the solution , Iterations and target number wait.

[0079] S82: Initialize the goals and constraints of the layout optimization algorithm. The optimization requirements in the post-simulation process generally include: routing length, power consumption, matching, parasitic parameters, temperature distribution uniformity, etc. Select one or more simulation indicators to be optimized from the optimization indicator requirements as the optimization target, and select other simulation indicators of interest as constraints. For example, routing length, power consumption, and parasitic parameters can be used as optimization targets, temperature distribution uniformity can be determined as a range as an inequality constraint, and matching can be determined as a value as an equality constraint.

[0080] S83: Configure the parameters of the post-simulator, such as simulation type setting, power supply and input signal setting, grid and simulation accuracy setting, etc. Ensure good communication between the layout optimization algorithm and the post-simulator.

[0081] Specifically, the parameter configuration includes simulation type setting, power supply and input signal setting, grid and simulation accuracy setting, etc.

[0082] S9: In order to solve the problem of low solution efficiency caused by large-scale decision variables during layout optimization, a decision variable grouping strategy is used based on the GLAL-MOPSO algorithm to decompose the original optimization problem into multiple sub-problems for optimization. The specific steps are as follows:

[0083] S91: Grouping vector sets by a set of decision variables The original optimization problem Decompose into A sub-question, Indicates A sub-question, Each binary vector in Each dimension of corresponds to the decision variable of the original optimization problem. b i = [ β 1 ,…, β t ,…, β D ] , 1 or 0 respectively indicates optimizing or not optimizing the subproblem. decision variables.

[0084] S92: Decision variable grouping vector set Get offspring through crossover and mutation operations , offspring Size and parentage same, and Merge into a new decision variable grouping vector set , Each vector in the above formula transforms the original optimization problem into a sub-problem, takes the individuals of the current population as parents and evenly distributes them to each sub-problem. The GLAL-MOPSO algorithm is used to optimize and update each sub-problem, and the calculation method is the same as that described in S31-S34.

[0085] S93: The layout optimization algorithm sends the solution set to the post-simulator, which obtains the simulation index of each solution through simulation calculation and sends it back to the layout optimization algorithm. The target value of each solution is calculated based on the obtained simulation indexes. and constraint value , ; Group the new decision variable vector set Calculate the evaluation index of each vector and :

[0086]

[0087]

[0088] in is the number of individuals in the subproblem, Indicates offspring individuals, and Respectively represent The maximum and minimum values ​​of the optimization target values, It reflects the influence of this sub-problem on the convergence of the original optimization problem. The smaller the better. Represents the size of each subproblem, the smaller the better, Represents the values ​​in a binary vector, either 0 or 1.

[0089] S94: According to the target value and constraint value , Update non-dominated solution set and local optimal solution , convergence global optimal solution , Diversity Global Optimal Solution and the best historical position of the particle , according to the indicator and Select the decision variable grouping vector with excellent attributes to obtain the best front The decision variable grouping vectors enter the next iteration.

[0090] S95: Repeat S91 to S94 until the optimization exit condition is met and output the optimized layout.

[0091] S10: If the solution output by S9 meets the post-simulation constraint requirements, it will be adopted as the final optimization result; otherwise, the feedback strategy is selected according to the degree of constraint violation: if the violation is minor, S7 is re-executed to select elite solutions from the circuit diagram optimization solution set, and the layout optimization process S8-S9 is re-executed; if the violation is serious or the solution output by repeated layout optimization processes still cannot meet the post-simulation constraint conditions, the pre-simulation target or constraint in step S2 is readjusted, and then the optimization continues from S3.

[0092] Compared with the prior art, the present invention has the following beneficial technical effects:

[0093] 1) The present invention can reduce the design cost of analog circuits and improve design efficiency: through simulation technology and intelligent optimization algorithms, it can not only efficiently complete the optimization of parameters and structures in conventional circuit design, but also increase the optimization space by optimizing device processes, ultimately reducing manual design costs and unnecessary simulation calculations.

[0094] 2) The present invention designs a global-local adaptive learning multi-objective particle swarm algorithm, which can efficiently optimize multiple objectives at the same time and can optimize multiple conflicting performance indicators; and proposes a decision variable grouping strategy for large-scale variable optimization problems that may arise in layout optimization, so that a more balanced and high-quality design solution can be obtained for complex circuit design problems.

[0095] 3) The present invention has a wide range of applications and strong adaptability: it is suitable for various types of circuit designs, and can be optimized for different design processes: device process, circuit schematics, and layouts. It has broad application prospects and a large optimization range. BRIEF DESCRIPTION OF THE DRAWINGS

[0096] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0097] Figure 1 An overall flow chart of an analog circuit intelligent design method based on process and post-simulation optimization feedback provided in an embodiment of the present invention.

[0098] Figure 2 A flow chart of a global-local adaptive learning multi-objective particle swarm algorithm (GLAL-MOPSO) designed for the present invention and a decision variable grouping strategy designed for large-scale decision variable problems. DETAILED DESCRIPTION

[0099] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0100] This embodiment illustrates the optimization process of an analog circuit. The optimization requirements in the circuit diagram optimization process are: harmonic loss ( ) is less than 0.5 and the smaller the better, gain ( ) is greater than or equal to 10 and the higher the better, the total current ( ) is less than 0.8 and the smaller the better, and the signal-to-noise ratio ( ) is greater than or equal to 80 dB and the higher the better, while the bandwidth ( ) is greater than or equal to 5.

[0101] The index requirements in the process of process optimization are: gate oxide thickness ( ) is controlled between 1.2nm and 1.5nm, and the junction depth ( ) is less than 30nm and the smaller the better, doping concentration ( )exist to Between, drive current ( ) greater than 400 The higher the better to increase the switching speed; sheet resistance ( ) is less than 10 Ω to ensure low resistance on the conductive path.

[0102] The index requirements during layout optimization are: power consumption ( ) is less than or equal to 1.5 and the smaller the better, parasitic resistance ( ) is less than or equal to 10 mΩ and the smaller the better. The temperature of each point in the circuit ( ) is less than or equal to 85 and the smaller the better, the trace length ( ) is as small as possible, and the device and wire meet the overlap limit ( ), parasitic capacitance ( ) is less than or equal to 0.1 pF and the smaller the better, the differential trace symmetry error ( ) is less than or equal to 2% and the smaller the better, power supply ripple ( ) is less than or equal to 10 mV and the smaller the better. At the same time, the current density of the key node ( ) is less than or equal to To avoid electromigration failure, the noise coupling coefficient between signal lines ( ) is less than or equal to -60dB and the lower the better. Based on the above optimization requirements, this embodiment provides a circuit optimization method based on pre- and post-simulation strategy and multi-objective optimization, and its process is as follows: Figure 1 As shown, the specific steps include:

[0103] S1: Input the circuit diagram to be optimized. The circuit diagram sets and defines the number (100), type (resistor, capacitor, inductor, current source, MOS tube, ground, diode and voltage source), connection method and device properties of the circuit components.

[0104] S2: Inputting algorithm parameters and index requirements of the circuit diagram optimization process, and initializing the circuit diagram optimization algorithm according to the algorithm parameters, index requirements and circuit diagram, specifically including the following steps:

[0105] S21: Initialize the parameters of the circuit diagram optimization algorithm, including initializing the population size , the dimension of the solution , Iterations , number of targets , the number of constraints .

[0106] S22: Randomly generate an initial solution set, initialize the objectives and constraints of the circuit diagram optimization algorithm, and select , , , As the optimization target; select as optimization constraints.

[0107] At this time, the optimization problem is expressed as:

[0108] min f(x)=[ f Gain (x), f IDC (x), f SNR (x), f BW (x)]

[0109] And meet:

[0110]

[0111] in, yes dimensional decision vector; in the process of circuit diagram optimization, It represents a set of circuit parameters and can also be regarded as a circuit diagram; Indicates circuit usage This set of parameters is about The objective function is Indicates about The objective function is Indicates about The objective function is Indicates about The objective function of Indicates an inequality constraint on BW. When the constraint is satisfied, it is less than or equal to The value of and , then the Pareto dominate relationship is defined as follows:

[0112] if:

[0113]

[0114] but Pareto dominance , recorded as .

[0115] The ideal result of the circuit diagram optimization process is a Pareto non-dominated solution set , that is, any two solutions in the solution set and There is no domination between them.

[0116] S23: Parameters of the front simulator are configured to ensure good communication between the circuit diagram optimization algorithm and the front simulator.

[0117] S3: The circuit diagram optimization process uses the GLAL-MOPSO algorithm to efficiently iterate and optimize the circuit diagram parameters. The specific steps are as follows:

[0118] S31: Update the solution set using the GLAL-MOPSO algorithm.

[0119] S32: Send the solution set to the front simulator, which obtains the simulation index of each solution through simulation calculation and sends it back to the circuit diagram optimization algorithm, and calculates the target value of each solution based on the obtained simulation indexes. and constraint value , update the non-dominated solution set and local optimal solution , convergence global optimal solution , Diversity Global Optimal Solution and the best historical position of the particle .

[0120] S33: Repeat S31 to S32 until the optimization exit condition is met. If the solution set after the optimization does not meet the optimization constraints, the device process optimization process S4-S6 is performed, otherwise the solution set of the circuit diagram optimization process is output and S7 is executed; in this example, it is assumed that the first circuit diagram optimization result does not meet the constraints and enters the device process optimization process.

[0121] S4: According to the degree of constraint violation of the solution set after circuit diagram optimization, set the index requirements for device process optimization. Enter the device process optimization process.

[0122] S5: Input algorithm parameters and index requirements of the device process optimization process, and initialize the process optimization algorithm according to the algorithm parameters and index requirements, which specifically includes the following steps:

[0123] S51: Initialize the parameters of the process optimization algorithm, including initializing the population size , the dimension of the solution , Iterations , number of targets , the number of constraints .

[0124] S52: Initialize the goals and constraints of the process optimization algorithm, select the junction depth ( )、Drive Current( )、Square resistance( ) is the optimization goal , and , select the gate oxide thickness ( ) and doping concentration ( ) is an inequality constraint and .

[0125] At this time, the optimization problem is expressed as:

[0126] min f(x)=[ f Xj x , f Idsat (x), f Rsheet (x)]

[0127] And meet:

[0128]

[0129]

[0130] in, yes dimensional decision vector; in the process of device process optimization, Represents information about process parameters; Respectively indicate the process used This set of parameters is about value, Value and The objective function of the value; and Indicates about Value and Inequality constraints on values, which are less than or equal to The value of .

[0131] S53: Initialize the process simulator, configure parameters of the process simulator, and ensure good communication between the process optimization algorithm and the process simulator.

[0132] S6: The process optimization process uses the GLAL-MOPSO algorithm to efficiently iterate and optimize the circuit diagram parameters. The specific steps are as follows:

[0133] S61: Update the solution set using the GLAL-MOPSO algorithm.

[0134] S62: Send the solution set to the process simulator, which obtains the simulation index of each solution through simulation calculation and sends it back to the process optimization algorithm, and calculates the target value of each solution based on the obtained simulation indexes. and constraint value , , update the non-dominated solution set and local optimal solution , convergence global optimal solution , Diversity Global Optimal Solution and the best historical position of the particle .

[0135] S63: Repeat S61 to S62 until the optimization exit condition is met, output the optimized process, update it to the circuit diagram optimization process and re-execute S2-S3.

[0136] S7: A solution that satisfies the constraints and has an excellent optimization target value is selected from the non-dominated solution set output by the circuit diagram optimization process as an elite solution. This elite solution is used as the initial circuit diagram of the layout optimization process. It can be used to generate an initial layout and enter the layout optimization process.

[0137] S8: Input the algorithm parameters and index requirements of the layout optimization process, and initialize the layout optimization algorithm according to the algorithm parameters, index requirements and elite solutions obtained by circuit diagram optimization, which specifically includes the following steps:

[0138] S81: Initialize the parameters of the layout optimization algorithm, including initializing the population size , the dimension of the solution , Iterations , number of targets , the number of constraints .

[0139] S82: Initialize the goals and constraints of the layout optimization algorithm and select the routing length ( )、parasitic resistance( )、parasitic capacitance( ), differential trace symmetry error ( )、Power supply ripple( )、Noise coupling coefficient( ) as the optimization target , , , , , , select power consumption ( ) and temperature ( ) as an inequality constraint , , select the overlap limit ( ) as an equality constraint .

[0140] At this time, the optimization problem is expressed as:

[0141] min f(x)=[ f L x , f R (x), f Cpar (x), f SErr (x), f VRipple (x), f NC (x)]

[0142] And meet:

[0143]

[0144]

[0145]

[0146] in, yes dimensional decision vector; in the process of layout and routing optimization, Represents the encoding information of layout and routing, 200 is the encoding length; Respectively indicate the process used This set of parameters is about value, value, value, value, Value and The objective function of the value; and Indicates about Value and Inequality constraints on values, which are less than or equal to The value of Indicates about An equality constraint on the values ​​of a value. The equality holds if the constraint is satisfied.

[0147] S83: Start the post-simulator, configure the parameters of the post-simulator, and ensure good communication between the layout optimization algorithm and the post-simulator.

[0148] S9: In order to solve the problem of low solution efficiency caused by large-scale decision variables during layout optimization, a decision variable grouping strategy is used based on the GLAL-MOPSO algorithm to decompose the original optimization problem into multiple sub-problems for optimization. Figure 2 As shown, the specific steps are as follows:

[0149] S91: Grouping vector sets by a set of decision variables The original optimization problem Decompose into A sub-question, Indicates A sub-question, Each binary vector in Each dimension of corresponds to the decision variable of the original optimization problem. b i = [ β 1 ,…, β t ,…, β D ] , 1 or 0 respectively indicates optimizing or not optimizing the subproblem. decision variables.

[0150] S92: Decision variable grouping vector set Get offspring through crossover and mutation operations , size and parent same, and Merge into a new decision variable grouping vector set , Each vector in the equation transforms the original optimization problem into a sub-problem, takes the individuals of the current population as parents and evenly distributes them to each sub-problem, and uses the GLAL-MOPSO algorithm to optimize and update each sub-problem.

[0151] S93: The layout optimization algorithm sends the solution set to the post-simulator, which obtains the simulation index of each solution through simulation calculation and sends it back to the layout optimization algorithm. The target value of each solution is calculated based on the obtained simulation indexes. and constraint value , ; Group the new decision variable vector set Calculate the evaluation index of each vector and :

[0152]

[0153]

[0154] in is the number of individuals in the subproblem, Indicates offspring individuals, and Respectively represent The maximum and minimum values ​​of the optimization target values, Represents the values ​​in a binary vector, either 0 or 1. It reflects the influence of this sub-problem on the convergence of the original optimization problem. The smaller the better. Represents the size of each subproblem, the smaller the better.

[0155] S94: According to the target value and constraint value , , , update the non-dominated solution set and local optimal solution , convergence global optimal solution , Diversity Global Optimal Solution and the best historical position of the particle , according to the indicator and Select the decision variable grouping vector with excellent attributes to obtain the best front The decision variable grouping vectors enter the next iteration.

[0156] S95: Repeat S91 to S94 until the optimization exit condition is met and output the optimized layout.

[0157] S10: If the solution set output by S9 exists If all constraints are satisfied, then the be adopted; otherwise, select a feedback strategy according to the degree of constraint violation: if the violation is minor, re-execute S7 to select the elite solution of the circuit diagram optimization result, and re-execute the layout optimization process; if the violation is serious or the solution output by repeated layout optimization processes still cannot meet the post-simulation constraints, readjust the pre-simulation target or constraint of step S2, and then continue the optimization from the circuit diagram optimization process.

[0158] Through simulation technology and intelligent optimization algorithm, the present invention can not only efficiently optimize circuit parameters and structures, but also optimize device processes to increase optimization space, reduce manual design costs and unnecessary simulation calculation costs, and improve design efficiency. The present invention can optimize multiple circuit indicators at the same time, weigh and optimize conflicting performance indicators, and propose a strategy for decision variable analysis for the optimization problem of large-scale variables, so that a more balanced and high-quality design solution can be obtained for complex circuit design problems. The present invention has a wide range of applications and strong adaptability: it is suitable for various types of circuit designs, and can be optimized for different design processes: device processes, circuit diagrams, and layouts. The application prospects of circuit optimization are broad and the optimization range is large.

[0159] It is to be understood that the present invention is described by some embodiments, and it is known to those skilled in the art that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. In addition, under the teachings of the present invention, these features and embodiments may be modified to adapt to specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the scope of protection of the present invention.

Claims

1. An intelligent design method for analog circuits based on process and post-simulation optimization feedback, characterized in that: The following steps are involved: S1: Input the circuit diagram to be optimized. The circuit diagram adopts the initial device process and specifies the number, type and connection method of circuit components; enter the circuit diagram optimization process; S2: inputting algorithm parameters and index requirements of the circuit diagram optimization process, and initializing the circuit diagram optimization algorithm according to the algorithm parameters, index requirements and the circuit diagram; S3: The circuit diagram optimization process adopts the global-local adaptive learning multi-objective particle swarm algorithm, namely the GLAL-MOPSO algorithm, to solve; if the solution set after the optimization does not meet the optimization constraints, the device process optimization process S4-S6 is carried out, otherwise the solution set of the circuit diagram optimization process is output and S7 is executed; S4: according to the degree of constraint violation of the solution set after circuit diagram optimization, the index requirements of device process optimization are set, and the device process optimization process is entered; S5: inputting algorithm parameters and index requirements of the device process optimization process, and initializing the process optimization algorithm according to the algorithm parameters and index requirements; S6: The process optimization process uses the GLAL-MOPSO algorithm to iteratively optimize the process parameters; output the optimized process, update it to the circuit diagram optimization process and re-execute S2-S3; S7: Select a solution that satisfies the constraints and has an excellent optimization target value from the non-dominated solution set output by the circuit diagram optimization process as an elite solution, use this elite solution as the initial circuit diagram of the layout optimization process, and use it to generate an initial layout to enter the layout optimization process; S8: inputting algorithm parameters and index requirements of the layout optimization process, and initializing the layout optimization algorithm according to the algorithm parameters, index requirements and elite solutions obtained by optimizing the circuit diagram; S9: In order to solve the dilemma of low solution efficiency caused by large-scale decision variables during layout optimization, a decision variable grouping strategy is adopted based on the GLAL-MOPSO algorithm to decompose the original optimization problem into multiple sub-problems and optimize them separately; S10: If the solution output by S9 meets the post-simulation constraint requirements, it will be adopted as the final optimization result; otherwise, the feedback strategy is selected according to the degree of constraint violation: if the violation is minor, S7 is re-executed to select the elite solution of the circuit diagram optimization result, and the layout optimization process S8-S9 is re-executed; if the violation is serious or the solution output by the layout optimization process is repeated for multiple times and still cannot meet the post-simulation constraint conditions, the pre-simulation target or constraint in step S2 is readjusted, and then the optimization continues from S3.

2. The analog circuit intelligent design method based on process and post-simulation optimization feedback according to claim 1, characterized in that: The initialization of the circuit diagram optimization algorithm in step S2 includes the following steps: S21: Initialize the parameters of the circuit diagram optimization algorithm, including initializing the population size , the dimension of the solution , Iterations and target number ; S22: Initializing the objectives and constraints of the circuit diagram optimization algorithm; selecting one or more simulation indicators to be optimized from the optimization indicator requirements as optimization objectives, and selecting other simulation indicators of interest as constraints; One with The multi-objective optimization problem with a dimensional objective function can be defined as follows: Inequality constraints and equality constraints , where for each and satisfy: in, yes dimensional decision vector, representing a set of circuit device parameters, and is the number of constraints; represents the optimization objective; Indicates The optimization goal is and Respectively represent The inequality constraints and equality constraints; In the process of multi-objective circuit diagram parameter optimization, two solutions may not be directly comparable. The optimal solution to the problem is composed of a set of Pareto optimal solutions, which are defined by the Pareto dominance relationship. and , if it satisfies: but Pareto dominance , recorded as ; If a solution is not dominated by any feasible solution, it is called a non-dominated solution. All non-dominated feasible solutions become a non-dominated solution set. In the initialization phase of the algorithm, a non-dominated solution set is calculated based on the initial solution set and is continuously updated in iterations. S23: Parameters of the front simulator are configured to ensure good communication between the circuit diagram optimization algorithm and the front simulator.

3. The analog circuit intelligent design method based on process and post-simulation optimization feedback according to claim 2, characterized in that: The circuit diagram optimization process of step S3 includes the following steps: S31: Select a part of the solutions in each sub-region in the target space as the local optimal solution, and let some particles learn from the local optimal solution; S32: Select the convergence global optimal solution and the diversity global optimal solution. During the evolution process, particles select different types of global optimal solutions or the local optimal solutions mentioned above for learning according to the evolutionary state; S33: A particle evolution state evaluation mechanism is adopted to allow particles to adaptively select learning targets based on their evolution state; particles are evaluated from two aspects: the exploration value of the current flight direction and the congestion of the local area; S34: Adaptively select learning objectives and parameter adjustments for particles based on the local optimal solution, convergence global optimal solution, and diversity global optimal solution, as well as the exploration value of the current flight direction and the crowding index of the local area; S35: sending the solution set to the front simulator, which obtains simulation indicators of each solution through simulation calculation and sends them back to the circuit diagram optimization algorithm, calculates the optimization target value and constraint value of each solution according to the obtained simulation indicators, and updates the non-dominated solution set, local optimal solution, convergence global optimal solution, diversity global optimal solution and the historical best position of the particle; S36: Repeat S31 to S35 until the optimization exit condition is met. If the solution set after the optimization does not meet the optimization constraint conditions, the device process optimization process S4-S6 is performed, otherwise the solution set of the circuit diagram optimization process is output and S7 is executed.

4. The analog circuit intelligent design method based on process and post-simulation optimization feedback according to claim 3 is characterized in that: Step S5: initializing the process optimization algorithm specifically includes the following steps: S5: Input algorithm parameters and index requirements of the device process optimization process, and initialize the process optimization algorithm based on them, which specifically includes the following steps: S51: Initialize the parameters of the process optimization algorithm, including the initialization population size , the dimension of the solution , Iterations and target number ; S52: Initializing the objectives and constraints of the process optimization algorithm, selecting one or more simulation indicators to be optimized from the optimization indicator requirements as optimization objectives, and selecting other simulation indicators of interest as constraints; S53: Parameters of the process simulator are configured to ensure good communication between the process optimization algorithm and the process simulator.

5. The analog circuit intelligent design method based on process and post-simulation optimization feedback according to claim 4, characterized in that: The process optimization process in step S6 specifically includes the following steps: S61: The method for updating the population calculation is the same as steps S31-S34; S62: Send the solution set to the process simulator, which obtains simulation indicators of each solution through simulation calculation and sends them back to the process optimization algorithm, calculates the target value and constraint value of each solution according to the obtained simulation indicators, and updates the non-dominated solution set, local optimal solution, convergence global optimal solution, diversity global optimal solution and the historical best position of the particle; S63: Repeat S61-S62 until the optimization exit condition is met, output the optimized process, update it to the circuit diagram optimization process and re-execute S2-S3.

6. The analog circuit intelligent design method based on process and post-simulation optimization feedback according to claim 5, characterized in that: Step S8: initializing the layout optimization algorithm specifically includes the following steps: S81: Initialize parameters of the layout optimization algorithm, including initialization population size , the dimension of the solution , Iterations and target number ; S82: Initialize the objectives and constraints of the layout optimization algorithm, select one or more simulation indicators to be optimized from the optimization indicator requirements as optimization objectives, and select other simulation indicators of interest as constraints; S83: Initialize the post-simulator, configure parameters of the post-simulator, and ensure good communication between the layout optimization algorithm and the post-simulator.

7. The analog circuit intelligent design method based on process and post-simulation optimization feedback according to claim 6, characterized in that: The intelligent optimization algorithm in step S9 specifically includes the following steps: S91: Grouping vector sets by a set of decision variables The original optimization problem Decompose into A sub-question, Indicates Sub-questions; S92: Decision variable grouping vector set Get offspring through crossover and mutation operations , offspring Size and parentage same, and Merge into a new decision variable grouping vector set , Each vector in the above formula transforms the original optimization problem into a sub-problem, takes the individuals of the current population as parents and evenly distributes them to each sub-problem. The GLAL-MOPSO algorithm is used to optimize and update each sub-problem. The calculation method is the same as that described in S31-S34. S93: The layout optimization algorithm sends the solution set to the post-simulator, which obtains the simulation index of each solution through simulation calculation and sends it back to the layout optimization algorithm, and calculates the target value and constraint value of each solution based on the obtained simulation indexes; the new decision variable grouping vector set Calculate the evaluation index of each vector and : S94: Update the non-dominated solution set, local optimal solution, convergence global optimal solution, diversity global optimal solution and the historical best position of the particle according to the target value and constraint value. and Select the decision variable grouping vector with excellent attributes to obtain the best front The decision variable grouping vectors enter the next iteration; S95: Repeat S91 to S94 until the optimization exit condition is met and output the optimized layout.

Images