Time delay circuit layout and semiconductor device
By adopting a mirror symmetric configuration in the delay circuit layout of the delay phase-locked loop DLL, the paths of multiple adjustable delay chains and selectors are matched with each other, and the problem of inconsistency between the delay phase-locked loop DLL is solved, and the alignment of clock signals and accurate operation of dynamic random access memory is achieved.
Patent Information
- Application Number
- CN202411571204.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-06
- Publication Date
- 2025-03-14
AI Technical Summary
In the structure of the delay phase-locked loop DLL, the delay paths between the multiple adjustable delay chains are inconsistent, resulting in the problem that the output clock signal is not aligned, which leads to the problem of the operation of the integrated circuit module being out of synchronization during operation.
By designing a delay circuit layout, the layout includes a duty cycle adjustment circuit, multiple adjustable delay chains, input signal selectors, output signal selectors and internal control selectors, and adopts a mirror symmetric configuration to match the paths of the adjustable delay chains and selectors to each other, thereby achieving alignment of the clock signal.
The mutual matching of each delayed circuit in the multiple delayed phase-locked loop circuit is achieved, allowing the dynamic random access memory to operate accurately, extending the service life of the delayed phase-locked loop circuit, and improving the reliability of the use.
Smart Images
Figure CN119623395A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a delay circuit layout and a semiconductor device, and in particular to a delay circuit layout for matching each delay line in a multi-way delay phase-locked loop circuit with each other, and a semiconductor device having the delay phase-locked loop circuit. Background Art
[0002] A delay-locked loop (DLL) is a delay circuit. It is a clock circuit whose output signal is generally the same as the input signal and has a specified delay relative to the input signal without the need for frequency multiplication. In other words, the main function of a delay-locked loop is to generate a clock signal with the same frequency as the reference clock. Of course, through a voltage-controlled delay chain, a delay-locked loop can also generate multiple phase-split clock signals.
[0003] Figure 5 1 is a circuit diagram showing the overall structure of a delay-locked loop circuit in the prior art. Figure 5 As shown, the delay-locked loop circuit 100' comprises: a duty cycle correction circuit (DCC: Duty-Cycle Corrector) 1' to which a clock input signal Clk_in is input; an adjustable delay chain (DL: DelayLine) 3' connected to the duty cycle correction circuit 1' and outputting a clock output signal Clk_out; a control circuit (Control) 5' for controlling the duty cycle correction circuit 1' and the adjustable delay chain 3'; a phase detector (PD: Phase Detect) 7' to which the clock input signal Clk_in is input and the output end of which is connected to the control circuit 5'; and a fixed delay circuit (DR: Delay Replica) 8' to which the clock output signal Clk_out is input and the output end of which is connected to the phase detector 7'. The adjustable delay chain 3' has a coarse adjustment delay unit 9a' and a fine adjustment delay unit 10a'.
[0004] In with Figure 5 In the delay circuit layout corresponding to the circuit diagram of the delay phase-locked loop circuit 100' shown, for this type of delay phase-locked loop circuit 100', it is usually necessary to consider the following issues in the layout of the layout: that is, whether the coarse adjustment delay unit 9a' and the fine adjustment delay unit 10a' as the basic delay unit devices in the adjustable delay chain 3' match the relevant metal connections, whether the internal clock tree of the adjustable delay chain 3' matches, how to prevent the noise of the metal connections on the output clock signal Clk_out, and whether the delay path in the fixed delay circuit 8' is consistent with the delay path in the adjustable delay chain 3'.
[0005] On the other hand, in order to adapt to integrated circuit modules with increasing integration, the structure of the delay locked loop DLL is required to be more compact, which results in the need to simultaneously set multiple adjustable delay chains 3' in the structure of a delay locked loop DLL.
[0006] However, in a delay-locked loop (DLL) structure, if multiple adjustable delay chains 3' are set at the same time, since the delay paths between the multiple adjustable delay chains 3' are not consistent, it may lead to the problem that the output clock signals Clk_out outputted by each adjustable delay chain 3' cannot be aligned, which eventually leads to the problem of asynchronous operation of the entire integrated circuit module during operation.
[0007] Specifically, for example, when four adjustable delay chains 3' are simultaneously provided in the structure of a delay locked loop DLL, it is difficult to ensure the consistency between the devices and metal wirings of each basic delay unit inside each adjustable delay chain 3' in the existing layout, and it is also difficult to match the parasitic resistance and parasitic capacitance inside each adjustable delay chain 3'.
[0008] Moreover, since the input clock signal will be input and output in any adjustable delay chain path, the layout needs to keep the relative position of the input selector consistent with the input device in each adjustable delay chain, and the relative position of the output selector consistent with the output device in each adjustable delay chain. At the same time, the internal basic delay unit in each adjustable delay chain and the internal selector in the control circuit also need to be consistent.
[0009] In addition, while keeping the relative positions of the various devices consistent, it is also necessary to consider the matching of the parasitic resistance and parasitic capacitance of the metal wiring. Since there are N adjustable delay chains, the overall metal wiring of the entire delay-locked loop circuit module is at least N times that of the traditional delay-locked loop DLL. For the process of dynamic random access memory (DRAM) with delay-locked loop DLL, the layout usually uses 3-4 layers of metal as devices, so the layout wiring will be limited.
[0010] On the other hand, assuming that Figure 5 The delay phase-locked loop circuit 100' shown in the figure is provided with four adjustable delay chains 3'. In this case, Figure 6As shown, when the clock input signal Clk_in is input to the delay locked loop 100' as the clock reference signal ref_clk, the clock input signal Clk_in passes through four adjustable delay chains 3' to obtain four clock output signals Clk_out, namely Clk in dlyline_1, Clk in dlyline_2, Clk in dlyline_3 and Clk in dlyline_4.
[0011] Figure 6 FIG. 1 is a schematic diagram showing waveforms of an input clock signal Clk_in and a clock output signal Clk_out in a delay locked loop circuit in the prior art. Figure 6 As shown, in the layout of the delay-locked loop DLL with multiple adjustable delay chains, due to the placement of various devices in the layout or the mismatch in the input and output paths and metal connections, output errors may occur when switching different adjustable delay chains 3', resulting in Figure 6 There is a mismatch between the clock output signal Clk_out shown in the figure, namely, the four clock signals Clk in dlyline_1, Clk in dlyline_2, Clk in dlyline_3 and Clk in dlyline_4, which leads to errors in the operation of the dynamic random access memory.
[0012] That is to say, in the layout of a delay locked loop DLL with multiple adjustable delay chains, it is difficult to ensure that various devices and metal connections are matched because the layout of the delay locked loop DLL is limited by metal wiring. Summary of the invention Technical problem to be solved by the invention
[0013] The present invention is completed to solve the above-mentioned problems. Its purpose is to provide a delay circuit layout and a semiconductor device for matching each delay line in a multi-way delay locked loop circuit. Even if a plurality of adjustable delay chains need to be configured simultaneously in the delay circuit layout, the clock output signals obtained after the clock input signal passes through each adjustable delay chain can be aligned with each other, so that a dynamic random access memory including a delay locked circuit with a plurality of adjustable delay chains can operate accurately.
[0014] Furthermore, according to the delay circuit layout of the delay phase-locked loop circuit with multiple adjustable delay chains involved in the present invention, although multiple adjustable delay chains are set at the same time, the clock signal Clk only passes through one of the adjustable delay chains at the same time. Therefore, the usage time of one adjustable delay chain among the multiple (for example, n) adjustable delay chains is only 1 / n of the usage time of the adjustable delay chain in the delay phase-locked loop circuit in the prior art. Therefore, the service life of the delay phase-locked loop circuit can be extended and the reliability of use can be improved.
[0015] Furthermore, according to the delay circuit layout of the delay phase-locked loop circuit with multiple adjustable delay chains involved in the present invention, since the signal lines connecting the multiple adjustable delay chains and each device can realize shared metal lines, the limited metal connection resources in the layout can be fully utilized. Technical means for solving technical problems
[0016] The present invention provides a delay circuit layout, characterized in that it includes: A duty cycle adjustment circuit layout unit, wherein the duty cycle adjustment circuit layout unit constitutes a duty cycle adjustment circuit, and 2N input signals including 1 main clock signal and 2N-1 command signals are input to the duty cycle adjustment circuit, wherein N is a natural number; 2N adjustable delay chain layout units, the 2N adjustable delay chain layout units constitute 2N adjustable delay chains, the 2N adjustable delay chains are input with the 2N input signals and perform adjustable delay processing on the 2N input signals respectively; An input signal selector layout unit, the input signal selector layout unit constituting an input signal selector, the input signal selector being connected between the duty cycle adjustment circuit and the 2N adjustable delay chains; an output signal selector layout unit, the output signal selector layout unit constituting an output signal selector, the output signal selector being connected to the 2N adjustable delay chains and outputting 2N output signals; and an internal control selector layout unit, the internal control selector layout unit constituting an internal control selector, the internal control selector selecting any one of the 2N adjustable delay chains to turn it on, In the delay circuit layout, the 2N adjustable delay chain layout units are divided into a first adjustable delay chain layout unit and a second group of adjustable delay chain layout units, and the first adjustable delay chain layout unit and the second group of adjustable delay chain layout units are arranged on both sides of the long side direction of the internal control selector layout unit in a centrally symmetrical mirror manner.
[0017] Furthermore, in the delay circuit layout involved in the present invention, the input signal selector layout unit and the output signal selector layout unit are arranged on both sides of the short side direction of the internal control selector layout unit in a centrally symmetrical mirror manner.
[0018] Furthermore, in the delay circuit layout involved in the present invention, in the delay circuit layout, the duty cycle adjustment circuit layout unit is configured on a side close to the input signal selector layout unit.
[0019] Furthermore, the delay circuit layout involved in the present invention also includes a control circuit layout unit constituting a control circuit, and the control circuit layout unit is configured on a side of the first adjustable delay chain layout unit or the second group of adjustable delay chain layout units away from the internal control selector layout unit.
[0020] Furthermore, in the delay circuit layout involved in the present invention, the internal control selector layout unit and the control circuit layout unit are configured separately.
[0021] Furthermore, in the delay circuit layout involved in the present invention, the delay circuit layout also includes a phase detector layout unit constituting a phase detector, and the phase detector is input with the 2N input signals and connected to the control circuit.
[0022] Furthermore, in the delay circuit layout involved in the present invention, the delay circuit layout also includes a fixed delay circuit layout unit constituting a fixed delay circuit, and the fixed delay circuit is connected to the 2N output signals input and connected to the phase detector.
[0023] Furthermore, in the delay circuit layout involved in the present invention, in the 2N adjustable delay chain layout units, the 2N adjustable delay chains are respectively constructed to include a coarse adjustment delay unit and a fine adjustment delay unit.
[0024] Furthermore, in the delay circuit layout involved in the present invention, in the delay circuit layout, the duty cycle adjustment circuit layout unit, the 2N adjustable delay chain layout units, the input signal selector layout unit, the output signal selector layout unit, the internal control selector layout unit and the control circuit layout unit are electrically connected through metal wires.
[0025] Furthermore, in the delay circuit layout involved in the present invention, in the delay circuit layout, the metal connections share metal lines.
[0026] The present invention also provides a memory, which includes a delay circuit corresponding to the delay circuit layout as described above.
[0027] Furthermore, in the memory involved in the present invention, the memory is a dynamic random access memory. Effects of the Invention
[0028] First, according to the delay circuit layout and semiconductor device of the delay locked loop circuit with multiple adjustable delay chains involved in the present invention, even if multiple adjustable delay chains need to be configured simultaneously in the delay circuit layout, the clock output signals obtained after the clock input signal passes through each adjustable delay chain can be aligned with each other, so that the dynamic random access memory including the delay locked loop circuit with multiple adjustable delay chains can work accurately.
[0029] Furthermore, according to the delay circuit layout and semiconductor device of the delay locked loop circuit with multiple adjustable delay chains involved in the present invention, although multiple adjustable delay chains are set at the same time, the clock signal Clk only passes through one of the adjustable delay chains at the same time. Therefore, the usage time of one adjustable delay chain among the multiple (for example, n) adjustable delay chains is only 1 / n of the usage time of the adjustable delay chain in the delay locked loop circuit in the prior art. Therefore, the service life of the delay locked loop circuit can be extended and the reliability of use can be improved.
[0030] Furthermore, according to the delay circuit layout and semiconductor device of the delay phase-locked loop circuit with multiple adjustable delay chains involved in the present invention, since the signal lines connecting the multiple adjustable delay chains and each device can realize shared metal lines, the limited metal connection resources in the layout can be fully utilized. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] Figure 1 : is a circuit diagram showing the overall structure of a delay locked loop circuit according to an embodiment of the present invention. Figure 2 Detailed description is given in FIG. 5 which is a schematic diagram showing a layout of a delay circuit of a delay locked loop circuit according to an embodiment of the present invention. Figure 3 1 is a schematic diagram showing waveforms of an input clock signal Clk_in and a clock output signal Clk_out in a delay locked loop circuit according to an embodiment of the present invention. Figure 4 1 is a schematic diagram showing a wiring diagram of a delay circuit layout of a delay locked loop circuit according to an embodiment of the present invention. Figure 5 is a circuit diagram showing the overall structure of a delay locked loop circuit in the prior art. Figure 6The figure is a schematic diagram showing waveforms of an input clock signal Clk_in and a clock output signal Clk_out in a delay locked loop circuit in the prior art. DETAILED DESCRIPTION
[0032] Regarding the overall circuit structure and layout of the delay locked loop circuit 100 involved in the present invention, in order to more clearly illustrate the technical solution involved in the present application, the following is a specific implementation method combined with the attached Figure 1-6 Further specific description is given. Moreover, the following description of the embodiments of the present invention with reference to the accompanying drawings is intended to explain the overall inventive concept of the present invention, and should not be understood as a limitation of the present invention. Obviously, the drawings described below are only some examples of the present application. For ordinary technicians in this field, the present application can also be applied to other similar scenarios based on these drawings without creative work. Unless it is obvious from the language environment or otherwise explained, the same reference numerals in the figures represent the same structure or operation.
[0033] In the description of the present application, it should be understood that the directions or positional relationships indicated by directional words such as "front, back, up, down, left, right", "lateral, vertical, perpendicular, horizontal" and "top, bottom" are usually based on the directions or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description. Unless otherwise specified, these directional words do not indicate or imply that the device or element referred to must have a specific direction or be constructed and operated in a specific direction, and therefore cannot be understood as limiting the scope of protection of the present application; the directional words "inside and outside" refer to the inside and outside relative to the contours of each component itself.
[0034] In addition, for ease of description, spatially relative terms such as "above", "above", "on the upper surface of", "above", etc. may be used herein to describe the spatial positional relationship between a device or feature and other devices or features as shown in the figure. It should be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation described in the figure. For example, if the device in the accompanying drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Thus, the exemplary term "above" may include both "above" and "below". The device may also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatially relative descriptions used herein are interpreted accordingly.
[0035] In addition, it should be noted that, as shown in the present application and the claims, unless the context clearly indicates an exception, the words "a", "an", "a kind" and / or "the" do not specifically refer to the singular, but may also include the plural. Generally speaking, the terms "including" and "comprising" only indicate the inclusion of clearly identified steps and elements, and these steps and elements do not constitute an exclusive list, and the method or device may also include other steps or elements. In addition, although the terms used in this application are selected from well-known and commonly used terms, some of the terms mentioned in the specification of this application may be selected by the applicant at his or her discretion, and their detailed meanings are explained in the relevant parts of the description of this article. In addition, it is required to understand this application not only by the actual terms used, but also by the meaning implied by each term. <Overall Circuit Structure of DLLL Circuit 100>
[0036] Below, refer to Figure 1 , the overall circuit structure of the delay locked loop circuit 100 involved in the embodiment of the present invention is described in detail.
[0037] Figure 1 1 is a circuit diagram showing the overall structure of the delay locked loop circuit 100 involved in the embodiment of the present invention. In addition, the delay locked loop circuit 100 involved in the embodiment of the present invention includes 2N adjustable delay chains 3, where N is a natural number. In the following, for the convenience of explanation, the delay locked loop circuit 100 in which N is 2, i.e., having 4 adjustable delay chains 3, is described as an example, but N can be any natural number as long as it is within the range allowed by the size of the integrated circuit.
[0038] Specifically, regarding the overall circuit structure of the delay locked loop circuit 100 involved in the embodiment of the present invention, as shown in FIG. Figure 1As shown, the delay-locked loop circuit 100 includes: a duty cycle adjustment circuit (DCC: Duty-Cycle Corrector) 1, which is input with four input signals, namely, a clock input signal Clk_in, a first instruction input signal Cmd_in1, a second instruction input signal Cmd_in3 and a third instruction input signal Cmd_in3; four adjustable delay chains (DL: DelayLine) 3a, 3b, 3c, 3d, which are respectively input with the above four input signals and respectively perform adjustable delay processing on the four input signals; an input signal selector (Input Mux) 2, which is connected between the duty cycle adjustment circuit 1 and the adjustable delay chains 3a, 3b, 3c, 3d; an output signal selector (Output Mux) 2, which is connected between the duty cycle adjustment circuit 1 and the adjustable delay chains 3a, 3b, 3c, 3d; Mux) 4, the output signal selector 4 is connected to the adjustable delay chains 3a, 3b, 3c, 3d respectively, and outputs four output signals, namely, the clock output signal Clk_out, the first instruction output signal Cmd_out1, the second instruction output signal Cmd_out3 and the third instruction output signal Cmd_out3; a control circuit (Control) 5, the control circuit 5 controls the duty cycle adjustment circuit 1, and has an internal control selector (Internal Mux) 6 for controlling the adjustable delay chains 3a, 3b, 3c, 3d; a phase detector (PD: PhaseDetect) 7, the phase detector 7 is input with the above four input signals, and its output end is connected to the control circuit 5; and a fixed delay circuit (DR: Delay Replica) 8, the fixed delay circuit 8 is input with the clock output signal Clk_out, and its output end is connected to the phase detector 7.
[0039] Furthermore, if Figure 1As shown, the adjustable delay chains 3a, 3b, 3c, 3d respectively have coarse delay units (Coarse delay) 9a, 9b, 9c, 9d, and fine delay units (Fine delay) 10a, 10b, 10c, 10d. Among them, when the four input signals are respectively input into the adjustable delay chains 3a, 3b, 3c, and 3d, first, the four input signals are input into the coarse adjustment delay units 9a, 9b, 9c, and 9d, and the coarse adjustment delay units 9a, 9b, 9c, and 9d respectively perform a relatively rough first delay processing on the four input signals, and then, the four input signals processed by the coarse adjustment delay units 9a, 9b, 9c, and 9d are input into the fine adjustment delay units 10a, 10b, 10c, and 10d, and the fine adjustment delay units 10a, 10b, 10c, and 10d perform a relatively fine second delay processing on the four input signals, thereby obtaining four internal signals, namely the clock internal signal Clk_internal, the first instruction internal signal Cmd_internal 1, the second instruction internal signal Cmd_internal 3, and the third instruction internal signal Cmd_internal 3, and respectively input them into the output signal selector 4.
[0040] On the other hand, the operation mode of the delay locked loop circuit 100 according to the embodiment of the present invention is to make the clock output signal Clk_out the same as the clock input signal Clk_in and to make the clock output signal Clk_out have a predetermined delay relative to the clock input signal Clk_in. Figure 1 , the operation mode of the delay locked loop circuit 100 involved in the embodiment of the present invention is described.
[0041] First, if Figure 1 As shown, for example, the four input signals input to the duty cycle adjustment circuit 1 include one clock input signal Clk_in, the four output signals output from the output signal selector 4 include one clock output signal Clk_out, and the internal control selector 6 is set to select the adjustable delay chain 3a and cause the clock signal input signal Clk_in to be delayed via the adjustable delay chain 3a.
[0042] Secondly, if Figure 1 As shown, the control circuit 5 controls the coarse adjustment delay unit 9a and the fine adjustment delay unit 10a in the adjustable delay chain 3a so that the clock output signal Clk_out has a specified delay relative to the clock input signal Clk_in.
[0043] Then, the output signal selector 4 inputs the clock output signal Clk_out to the fixed delay circuit 8, which fixes the frequency of the clock output signal Clk_out, and then inputs it to the phase detector 7. The phase detector 7 identifies the phase difference between the clock input signal Clk_in and the clock output signal Clk_out, and outputs a control voltage Vcontrol (not shown) corresponding to the phase difference, and then inputs the control voltage Vcontrol to the control circuit 5.
[0044] Finally, if Figure 1 As shown, the control circuit 5 controls the duty cycle adjustment circuit 1 according to Vcontrol from the phase detector 7, thereby making the delay between the clock output signal Clk_out and the clock input signal Clk_in have a specified delay.
[0045] In addition, if Figure 1 As shown, although the description of the present invention takes the case where the internal control selector 6 selects the adjustable delay chain 3a as an example for explanation, in fact, any one of the adjustable delay chain 3b, the adjustable delay chain 3c, and the adjustable delay chain 3d can also be selected to achieve the same effect. <Layout of Delay Circuit Layout 100L>
[0046] Below, refer to Figure 2 , the layout of the delay locked loop circuit 100 involved in the embodiment of the present invention is described in detail.
[0047] Figure 2 FIG. 1 is a schematic diagram showing the layout of a delay circuit layout 100L according to an embodiment of the present invention. Figure 2 The delay circuit layout 100L shown includes Figure 1 The circuit structure of the delay locked loop circuit 100 shown in the figure shows the corresponding layout of the duty cycle adjustment circuit 1, the input signal selector 2, the adjustable delay chains 3a, 3b, 3c, 3d, the output signal selector 4, the control circuit 5, and the internal control selector 6. The layout of other circuit structures is not shown here because it does not involve the inventive point of the present invention.
[0048] like Figure 2As shown, in the delay circuit layout 100L involved in the embodiment of the present invention, the duty cycle adjustment circuit layout unit 1L constitutes the duty cycle adjustment circuit 1, the input signal selector layout unit 2L constitutes the input signal selector 2, the adjustable delay chain layout units 3aL, 3bL, 3cL, and 3dL respectively constitute the adjustable delay chains 3a, 3b, 3c, and 3d, the output signal selector layout unit 4L constitutes the output signal selector 4, the control circuit layout unit 5L constitutes the control circuit 5, and the internal control selector layout unit 6L constitutes the internal control selector 6.
[0049] Furthermore, if Figure 2 As shown, first, the internal control selector layout unit 6L is configured at the center of the entire layout of the delay locked loop circuit 100, and then Figure 2 The upper part of the control selector layout unit 6L is provided with an adjustable delay chain layout unit 3bL and an adjustable delay chain layout unit 3aL in sequence along the direction away from the internal control selector layout unit 6L. Figure 2 On the lower side of the circuit, an adjustable delay chain layout unit 3cL and an adjustable delay chain layout unit 3dL are sequentially arranged in a direction away from the internal control selector layout unit 6L.
[0050] That is, in the delay circuit layout 100L involved in the embodiment of the present invention, Figure 2 As shown, the adjustable delay chain layout units 3aL, 3bL, 3cL, and 3dL are divided into two groups of adjustable delay chain layout units, wherein the adjustable delay chain layout unit 3aL and the adjustable delay chain layout unit 3bL constitute a first group of adjustable delay chain layout units, and the adjustable delay chain layout unit 3cL and the adjustable delay chain layout unit 3dL constitute a second group of adjustable delay chain layout units, and then the first adjustable delay chain layout unit and the second group of adjustable delay chain layout units are configured on both sides of the long side direction of the internal control selector layout unit 6L in a center-symmetrical mirror manner.
[0051] Furthermore, if Figure 2 As shown, in Figure 2 The left part of the internal control selector layout unit 6L is configured with an input signal selector layout unit 2L. Figure 2 In the right part, the output signal selector layout unit 4L is configured on the right side of the internal control selector layout unit 6L.
[0052] That is, in the delay circuit layout 100L involved in the embodiment of the present invention, Figure 2 As shown, the input signal selector layout unit 2L and the output signal selector layout unit 4L are arranged on both sides of the short side direction of the internal control selector layout unit 6L in a center-symmetrical mirror manner.
[0053] Furthermore, if Figure 2 As shown, in the delay circuit layout 100L according to the embodiment of the present invention, the duty cycle adjustment circuit layout unit 1L is arranged on a side close to the input signal selector layout unit 2L.
[0054] In addition, if Figure 2 As shown, in the delay circuit layout 100L involved in the embodiment of the present invention, the control circuit layout unit 5L and the internal control selector layout Figure 6 L is configured separately and is configured on a side of the adjustable delay chain layout unit 3aL away from the internal control selector unit 6L. Of course, the delay circuit layout 100L involved in the embodiment of the present invention is not limited to Figure 2 In the layout shown, the control circuit layout unit 5L can also be arranged on a side of the adjustable delay chain layout unit 3dL away from the internal control selector unit 6L. <Technical Effects of Delay Circuit Layout 100L>
[0055] Below, according to Figure 3 , the technical effects of the delay locked loop circuit 100 involved in the embodiment of the present invention are described in detail.
[0056] Figure 3 1 is a schematic diagram showing waveforms of a clock input signal Clk_in and a clock output signal Clk_out in a delay locked loop circuit 100 according to an embodiment of the present invention. Figure 3 As shown, when a clock input signal Clk_in is input to the delay locked loop circuit 100, the internal control selector 6 is used to select the adjustable delay chains 3a, 3b, 3c, and 3d respectively to make the clock input signal Clk_in pass through the adjustable delay chains 3a, 3b, 3c, and 3d respectively, and then four clock output signals Clk_out are output. Figure 3 In the figure, the waveform of the clock input signal Clk_in is marked as ref_clk, and the waveforms of the four clock output signals Clk_out are marked as clk_in dlyline_1, clk_in dlyline_2, clk_in dlyline_3, and clk_in dlyline_4, respectively.
[0057] like Figure 3As shown, the waveform ref_clk of the clock input signal Clk_in is compared with the waveforms clk_in dlyline_1, clk_in dlyline_2, clk_in dlyline_3, and clk_in dlyline_4 of each clock output signal Clk_out, and it can be seen that the waveform ref_clk and the waveform clk_in dlyline_1 meet the conditions that the frequency is the same and the phase difference is 2.5 times the square wave period. Similarly, the waveform ref_clk and the waveform clk_in dlyline_2, the waveform ref_clk and the waveform clk_in dlyline_3, and the waveform ref_clk and the waveform clk_in dlyline_3 also meet the above conditions. That is to say, the delay locked loop circuit 100 involved in the embodiment of the present invention enables each clock output signal Clk_out to be aligned with each other.
[0058] In summary, in the delay circuit layout 100L involved in the embodiment of the present invention, the adjustable delay chain layout unit 3bL and the adjustable delay chain layout unit 3aL, the adjustable delay chain layout unit 3cL and the adjustable delay chain layout unit 3dL, the input signal selector layout unit 2L, and the output signal selector layout unit 4L are respectively configured on the upper side, the lower side, the left side, and the right side with the internal control selector layout unit 6L as the center, so that the adjustable delay chain layout unit 3bL and the adjustable delay chain layout unit 3cL are mirror-symmetric along the long side direction of the internal control selector layout unit 6L, and the adjustable delay chain layout unit 3aL and the adjustable delay chain layout unit 3dL are mirror-symmetric along the long side direction of the internal control selector layout unit 6L, and the input signal selector layout unit 2L and the output signal selector layout unit 4L are mirror-symmetric along the short side direction of the internal control selector layout unit 6L.
[0059] That is to say, by configuring the input signal selector layout unit 2L, the output signal selector layout unit 4L, and the internal control selector layout unit 6L at the center position of the first adjustable delay chain layout unit and the second group of adjustable delay chain layout units, that is, the center position of the delay circuit layout 100L, and configuring the duty cycle adjustment circuit layout unit 1L on the side close to the input signal selector layout unit 2L, the adjustable delay chain layout unit 3aL, the adjustable delay chain layout unit 3bL, the adjustable delay chain layout unit 3cL and the adjustable delay chain layout unit 3dL can have the same path to the selectors in the input signal selector layout unit 2L, the output signal selector layout unit 4L, and the internal control selector layout unit 6L, respectively, thereby achieving the purpose of matching each signal path with each other.
[0060] Therefore, according to the delay circuit layout 100L involved in the embodiment of the present invention, although it is necessary to configure multiple adjustable delay chains 3a, 3b, 3c, and 3d at the same time, the clock output signal Clk_out obtained by the clock input signal Clk_in after passing through each adjustable delay chain can be aligned with each other through the mirror-symmetrical configuration as described above, so that the dynamic random access memory of the delay locked loop circuit 100 having multiple adjustable delay chains 3a, 3b, 3c, and 3d set at the same time can operate accurately.
[0061] Moreover, if Figure 2 As shown, according to the delay circuit layout 100L involved in the embodiment of the present invention, although four adjustable delay chains 3a, 3b, 3c, and 3d are configured at the same time, the clock signal Clk is made to pass through only one of the adjustable delay chains, for example, the adjustable delay chain 3a. Therefore, the use time of the adjustable delay chain 3a among the four adjustable delay chains 3a, 3b, 3c, and 3d is only 1 / 4 of the use time of the adjustable delay chain in the delay phase-locked loop circuit 100' in the prior art. Therefore, the service life of the delay phase-locked loop circuit 100 can be extended and the reliability of use can be improved. <Schematic diagram of wiring of delay circuit layout 100L>
[0062] Below, refer to Figure 4 , a wiring schematic diagram of the delay circuit layout 100L involved in an embodiment of the present invention is described in detail.
[0063] Figure 4 FIG. 1 is a schematic diagram showing a layout of a delay circuit of a delay-locked loop circuit according to an embodiment of the present invention. Figure 4 As shown, in the delay circuit layout 100L involved in the embodiment of the present invention, the duty cycle adjustment circuit layout unit 1L, the adjustable delay chain layout unit 3aL, the adjustable delay chain layout unit 3bL, the adjustable delay chain layout unit 3cL, the adjustable delay chain layout unit 3 Figure 3 dL, the input signal selector layout unit 2L, the output signal selector layout unit 4L, the internal control selector layout unit 6L, and the control circuit layout unit 5L are electrically connected through metal wiring shown by thick arrow lines.
[0064] Specifically, regarding the adjustable delay chain layout unit 3aL, the adjustable delay chain layout unit 3bL, the adjustable delay chain layout unit 3cL, the adjustable delay chain layout unit Figure 3 The metal connection lines set between dL and the input signal selector layout unit 2L, the output signal selector layout unit 4L, and the internal control selector layout unit 6L, such as Figure 4As shown, since the adjustable delay chain layout unit 3bL and the adjustable delay chain layout unit 3cL are mirror-symmetric along the long side direction of the internal control selector layout unit 6L, and the adjustable delay chain layout unit 3aL and the adjustable delay chain layout unit 3dL are mirror-symmetric along the long side direction of the internal control selector layout unit 6L, the adjustable delay chain layout unit 3aL, the adjustable delay chain layout unit 3bL, the adjustable delay chain layout unit 3cL, and the adjustable delay chain layout unit 3dL can be made mirror-symmetric. Figure 3 The various input devices and output devices in dL are connected to the center of the delay circuit layout 100L, that is, the internal control selector layout. Figure 6 The relative positions of L are the same.
[0065] Therefore, from the adjustable delay chain layout unit 3aL, the adjustable delay chain layout unit 3bL, the adjustable delay chain layout unit 3cL, the adjustable delay chain layout unit Figure 3 dL to internal control selector board Figure 6 The metal wiring of L can share metal lines, thereby making full use of limited metal wiring resources.
[0066] Furthermore, if Figure 4 As shown in FIG. 1 , since the input signal selector layout unit 2L and the output signal selector layout unit 4L are mirror-symmetric along the short side direction of the internal control selector layout unit 6L, the various input devices, output devices, and selectors in the input signal selector layout unit 2L and the output signal selector layout unit 4L can be aligned to the center of the delay circuit layout 100L, i.e., the internal control selector layout unit 6L. Figure 6 The relative positions of L are the same.
[0067] Therefore, from the input signal selector layout unit 2L, the output signal selector layout unit 4L to the internal control selector layout unit Figure 6 The metal wiring of L can share metal lines, thereby making full use of limited metal wiring resources.
[0068] In addition, if Figure 4 As shown, in the delay circuit layout 100L involved in the embodiment of the present invention, since all signal paths are from one side of the adjustable delay chain layout unit 3aL and the adjustable delay chain layout unit 3bL, and the adjustable delay chain layout unit 3cL and the adjustable delay chain layout unit 3cL Figure 3 One side of dL is respectively connected to the internal control selector layout unit 6L, and is sent to the control circuit layout unit 5L after completing the four-selection. Therefore, most of the signal lines from the internal control selector layout unit 6L to the control circuit layout unit 5L can share metal wires, thereby making full use of limited metal connection resources.
[0069] In summary, according to the delay circuit layout 100L having multiple adjustable delay chains 3aL, 3bL, 3cL, and 3dL, since the signal lines connecting the multiple adjustable delay chains 3aL, 3bL, 3cL, and 3dL and various devices can realize shared metal lines, the limited metal connection resources in the layout can be fully utilized. <Memory with Delay Circuit Layout 100L>
[0070] The embodiment of the present invention also relates to a semiconductor device having the delay locked loop circuit 100 as described above. Specifically, in the field of integrated circuit technology, Figure 1 The DLL circuit 100 shown is usually built into a semiconductor device. For example, the DLL circuit 100 is built into a dynamic random access memory (DRAM), thereby performing synchronization control on various operations in the dynamic random access memory.
[0071] Although the present application describes various exemplary embodiments and examples, various features, methods, and functions described in one or more embodiments are not limited to application in specific embodiments and may be applied to the embodiments alone or in various combinations.
[0072] Therefore, it is considered that numerous modifications not shown in the examples are also included in the technical scope disclosed in the present specification, for example, including the case where at least one component is modified, added or omitted, and the case where at least one component is extracted and combined with components of other embodiments. Industrial Applicability
[0073] The delay circuit layout and semiconductor device involved in the present invention can be applied to the delay circuit layout that requires each delay line in a multi-way delay locked loop circuit to match each other, and the semiconductor device having the delay locked loop circuit. Description of symbols
[0074] 1,1'Duty cycle adjustment circuit, 1L duty cycle adjustment circuit layout unit, 2 input signal selectors, 2L input signal selector layout unit, 3a,3b,3c,3d,3' adjustable delay chain, 3aL, 3bL, 3cL, 3dL adjustable delay chain layout unit, 4 output signal selectors, 4L output signal selector layout unit, 5,5' control circuit, 5L control circuit layout unit, 6 internal control selectors, 6L internal control selector layout unit, 7,7' phase detector, 8,8' fixed delay circuit, 9a,9b,9c,9d,9a' coarse adjustment delay unit, 10a, 10b, 10c, 10d, 10a' fine-tuning delay unit, 100,100' Delay locked loop circuit.
Claims
1. A delay circuit layout, characterized in that: include: A duty cycle adjustment circuit layout unit, wherein the duty cycle adjustment circuit layout unit constitutes a duty cycle adjustment circuit, and 2N input signals including 1 main clock signal and 2N-1 command signals are input to the duty cycle adjustment circuit, wherein N is a natural number; 2N adjustable delay chain layout units, the 2N adjustable delay chain layout units constitute 2N adjustable delay chains, the 2N adjustable delay chains are input with the 2N input signals and perform adjustable delay processing on the 2N input signals respectively; An input signal selector layout unit, the input signal selector layout unit constituting an input signal selector, the input signal selector being connected between the duty cycle adjustment circuit and the 2N adjustable delay chains; an output signal selector layout unit, the output signal selector layout unit constituting an output signal selector, the output signal selector being connected to the 2N adjustable delay chains and outputting 2N output signals; and an internal control selector layout unit, the internal control selector layout unit constituting an internal control selector, the internal control selector selecting any one of the 2N adjustable delay chains to turn it on, In the delay circuit layout, the 2N adjustable delay chain layout units are divided into a first adjustable delay chain layout unit and a second group of adjustable delay chain layout units, and the first adjustable delay chain layout unit and the second group of adjustable delay chain layout units are arranged on both sides of the long side direction of the internal control selector layout unit in a centrally symmetrical mirror manner.
2. The delay circuit layout according to claim 1, characterized in that: In the delay circuit layout, the input signal selector layout unit and the output signal selector layout unit are arranged on both sides of the short side direction of the internal control selector layout unit in a centrally symmetrical mirror manner.
3. The delay circuit layout according to claim 1, characterized in that: In the delay circuit layout, the duty cycle adjustment circuit layout unit is arranged on a side close to the input signal selector layout unit.
4. The delay circuit layout according to any one of claims 1 to 3, characterized in that: The delay circuit layout also includes a control circuit layout unit constituting a control circuit, and the control circuit layout unit is configured on a side of the first adjustable delay chain layout unit or the second group of adjustable delay chain layout units away from the internal control selector layout unit.
5. The delay circuit layout according to claim 4, characterized in that: The internal control selector layout unit is configured separately from the control circuit layout unit.
6. The delay circuit layout according to claim 4, characterized in that: The delay circuit layout also includes a phase detector layout unit constituting a phase detector. The phase detector is input with the 2N input signals and is connected to the control circuit.
7. The delay circuit layout according to claim 6, characterized in that: The delay circuit layout also includes a fixed delay circuit layout unit constituting a fixed delay circuit, and the fixed delay circuit is connected to the 2N output signals input thereto and is connected to the phase detector.
8. The delay circuit layout according to any one of claims 1 to 3, characterized in that: In the 2N adjustable delay chain layout units, the 2N adjustable delay chains are respectively constructed to include a coarse adjustment delay unit and a fine adjustment delay unit.
9. The delay circuit layout according to any one of claims 1 to 3, characterized in that: In the delay circuit layout, the duty cycle adjustment circuit layout unit, the 2N adjustable delay chain layout units, the input signal selector layout unit, the output signal selector layout unit, the internal control selector layout unit and the control circuit layout unit are electrically connected through metal wires.
10. The delay circuit layout according to claim 9, characterized in that: In the delay circuit layout, the metal connections share metal lines.
11. A memory, characterized in that: include: A delay circuit corresponding to the delay circuit layout according to any one of claims 1 to 10.
12. The memory according to claim 11, wherein: The memory is a dynamic random access memory.