Package reliability optimization method and system based on position optimization, and related equipment

Abstract

The invention relates to a position optimization-based packaging reliability optimization method and system and related equipment, and the method comprises the steps: carrying out the design of a packaging scheme in a manner of randomly arranging the position of a chip packaged on a substrate, and carrying out the optimization of the packaging scheme through the modeling of the chip, the substrate and a welding ball, and calculating the variance of the stress of the welding ball. Through the mode, the stress of the solder balls during chip packaging can be averaged as much as possible, so that the reliability of chip packaging is improved; moreover, the method is easy to realize automatic processing, and is beneficial to improving the working efficiency of the chip packaging design and manufacturing process.

Description

Technical Field

[0001] The present invention is applicable to the field of semiconductor packaging technology, and in particular relates to a packaging reliability optimization method, system and related equipment based on position optimization. Background Art

[0002] In the chip packaging process, FPG (Fine Pitch BGA) packaging and BGA (Ball Grid Array) packaging have become important chip packaging forms due to their excellent efficiency and performance. FPG packaging is mainly used in high-frequency communication equipment, computer motherboards, high-performance graphics cards, mobile devices and consumer electronics, and is suitable for scenarios that require high signal integrity and miniaturized design; BGA is widely used in processors, microcontrollers, FPGAs, network equipment and consumer electronics, and is suitable for occasions that require high power handling, stable performance and high-density pin connections. With the advancement of manufacturing technology, the solder ball pitch of FPG and BGA packaging has been continuously reduced, which has promoted the development of chip miniaturization and high performance. With the rapid development of the Internet of Things (IoT), artificial intelligence (AI) and 5G technology, the demand for high-performance and high-density chip packaging continues to increase. The respective advantages of FPG packaging and BGA packaging make them suitable for different application scenarios. When choosing a packaging form, design engineers need to comprehensively consider factors such as performance, cost, heat dissipation and production process to achieve the best design effect.

[0003] In the chip packaging process, solder ball stress is a key consideration. Issues related to solder ball stress include the following: Thermal expansion mismatch: The thermal expansion coefficients of the chip and substrate (such as PCB) are usually different when the temperature changes. This difference can cause stress in the solder balls during heating and cooling, which may affect the reliability of the solder joints. Solder joint fatigue. Solder balls will experience periodic thermal cycles during long-term use, which will lead to solder joint fatigue and possible failure. Excessive stress may accelerate the formation of cracks in the solder joints. Insufficient signal integrity and excessive solder ball stress may lead to poor connection between the chip and the substrate, thus affecting the integrity of signal transmission and causing degradation of electrical performance; Reliability and life are difficult to guarantee, and the stress level of the solder balls directly affects the overall reliability of the package. Excessive stress may cause solder joint failure, thus shortening the product's life. Problems in the manufacturing process: During the packaging process, the stress of the solder balls may cause defects such as bubbles and cracks, which may cause problems in subsequent testing and use.

[0004] In summary, during the chip packaging design and manufacturing process, the positions of the chips on the packaging substrate and the positions of the solder balls are different, which will lead to large differences in the stress between the solder balls, causing some solder balls to be subjected to excessive stress and fail prematurely. This situation will greatly affect the consistency of the reliability of the packaging process. Summary of the invention

[0005] The present invention provides a packaging reliability optimization method, system and related equipment based on position optimization, aiming to solve the technical problem of insufficient packaging reliability caused by large stress difference between solder balls in the existing chip packaging process.

[0006] In order to solve the above technical problems, in a first aspect, the present invention provides a packaging reliability optimization method based on position optimization, comprising the following steps: S101, obtaining a first shape of a packaging substrate and a second shape of a chip to be packaged, wherein the first shape and the second shape include a length and a width; S102, gridding the packaging substrate according to the first shape and the second shape to obtain a gridded packaging substrate, and determining the number of iterations according to the gridding degree of the packaging substrate; S103, arranging the chips on the grid packaging substrate in a random arrangement manner to obtain a packaging solution; S104, determining whether the packaging solution meets the preset chip layout rule, if yes, executing step S105; if no, returning to step S103; S105, based on the packaging solution, modeling the chip and the packaging substrate, and simultaneously modeling the solder balls for soldering the chip to the packaging substrate, to obtain a packaging model; S106, obtaining an average equivalent stress of each solder ball based on the packaging model, and obtaining a stress variance value according to the average equivalent stress; S107, repeating steps S103-S106 until the number of repetitions is equal to the number of iterations, to obtain a plurality of the packaging solutions and the corresponding stress variance values; S108, selecting a corresponding packaging solution as an optimized packaging solution according to the stress variance value with the smallest numerical value, and outputting a packaging position of the chip packaged on the packaging substrate corresponding to the optimized packaging solution.

[0007] Furthermore, in step S102, the grid size for gridding the packaging substrate is determined according to the second shapes of the plurality of chips, and the length and width of the plurality of chips are defined as ( a 1, b 1) ( a 2, b2) … a n , b n ), the common divisor of the length and width of the plurality of said chips is k , the grid size and the common divisor k The length and width of the packaging substrate are equal to ( A , B ), the number of chips is n , the number of iterations is N , satisfying the following relationship: .

[0008] Furthermore, in step S106, the number of solder balls in the packaging model is defined as n , the average equivalent stress of each solder ball is F 1. F 2. … F n , the stress variance value is St 2 , satisfying the following relationship: ; .

[0009] Furthermore, the preset chip arrangement rule is: different chips do not overlap each other when arranged on the grid packaging substrate; A plane coordinate system is constructed with the top corner of the grid packaging substrate as the origin to define any first chip arranged on the grid packaging substrate. R1 , Second chip R2 The series of coordinates of the lower left corner and the upper right corner in the plane coordinate system are R1=[x11,y11,x12,y12] , R2=[x21,y21,x22,y22] When any one of the following relations is satisfied, the packaging solution satisfies the preset chip layout rule: R1[2] ≤ R2[0] ; R1[0] ≥ R2[2] ; R1[3] ≤ R2[1] ; R1[1] ≥ R2[3] .

[0010] Furthermore, the preset chip arrangement rule is: When different chips are arranged on the grid packaging substrate, the spacing between them is not less than the preset packaging spacing; A plane coordinate system is constructed with the top corner of the grid packaging substrate as the origin to define any first chip arranged on the grid packaging substrate. R1, Second chip R2 The series of coordinates of the lower left corner and the upper right corner in the plane coordinate system are R1=[x11,y11,x12,y12] , R2=[x21,y21,x22,y22] , the preset package spacing is GP When any one of the following relations is satisfied, the packaging solution satisfies the preset chip layout rule: R1[2] ≤ R2[0], GP ≤ R2[0] - R1[2] ; R2[2] ≤ R1[0], GP ≤ R1[0] - R2[2] ; R1[3] ≤ R2[1], GP ≤ R2[1] - R1[3] ; R2[3] ≤ R1[1], GP ≤ R1[1] - R2[3] .

[0011] In a second aspect, the present invention further provides a packaging reliability optimization system based on position optimization, comprising: An initialization module, used to obtain a first shape of a packaging substrate and a second shape of a chip to be packaged, wherein the first shape and the second shape include a length and a width; A gridding module, used for gridding the packaging substrate according to the first shape and the second shape to obtain a gridded packaging substrate, and determining the number of iterations according to the gridding degree of the packaging substrate; A random arrangement module, used to arrange the chips on the grid packaging substrate in a random arrangement manner to obtain a packaging solution; A judgment module, used to judge whether the packaging scheme meets the preset chip arrangement rule, and if so, execute the modeling module; if not, return to the random arrangement module; A modeling module, used to model the chip and the packaging substrate based on the packaging solution, and simultaneously model the solder balls used to solder the chip to the packaging substrate, to obtain a packaging model; A stress simulation module, used for obtaining an average equivalent stress of each solder ball based on the packaging model, and obtaining a stress variance value according to the average equivalent stress; An iterative control module, used for repeatedly executing the random arrangement module, the judgment module, the modeling module and the stress simulation module in sequence until the number of repetitions is equal to the number of iterations, so as to obtain a plurality of the packaging schemes and the corresponding stress variance values; The output module is used to select a corresponding packaging scheme as an optimized packaging scheme according to the stress variance value with the smallest numerical value, and output the packaging position of the chip packaged on the packaging substrate corresponding to the optimized packaging scheme.

[0012] Furthermore, the random arrangement module is further used to determine the grid size for gridding the packaging substrate according to the second shapes of the plurality of chips, and define the length and width of the plurality of chips as (a 1, b 1) ( a 2, b 2) … a n , b n ), the common divisor of the length and width of the plurality of said chips is k , the grid size and the common divisor k The length and width of the packaging substrate are equal to ( A , B ), the number of chips is n , the number of iterations is N , satisfying the following relationship: .

[0013] Furthermore, the stress simulation module is also used to define the number of solder balls in the packaging model as n , the average equivalent stress of each solder ball is F 1. F 2. … F n , the stress variance value is St 2 , satisfying the following relationship: ; .

[0014] In the third aspect, the present invention also provides a computer device, comprising: a memory, a processor, and a packaging reliability optimization program based on position optimization stored in the memory and executable on the processor, wherein when the processor executes the packaging reliability optimization program based on position optimization, the steps in the packaging reliability optimization method based on position optimization as described in any one of the above embodiments are implemented.

[0015] In a fourth aspect, the present invention also provides a computer-readable storage medium, on which a packaging reliability optimization program based on position optimization is stored. When the packaging reliability optimization program based on position optimization is executed by a processor, the steps in the packaging reliability optimization method based on position optimization as described in any one of the above embodiments are implemented.

[0016] The beneficial effect achieved by the present invention is that a packaging reliability optimization method based on position optimization is proposed. The method designs a packaging scheme by randomly arranging the chip packages on the substrate, and optimizes the packaging scheme by calculating the variance of the solder ball stress through modeling of the chip, substrate and solder balls. In this way, the solder ball stress during chip packaging can be made as even as possible, thereby improving the reliability of the chip packaging; and the method is easy to realize automated processing, which is conducive to improving the work efficiency of the chip packaging design and manufacturing process. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a flowchart of the steps of a packaging reliability optimization method based on position optimization provided by an embodiment of the present invention; Figure 2 It is a schematic diagram of chip arrangement positions in a packaging reliability optimization method based on position optimization provided by an embodiment of the present invention; Figure 3 It is a schematic diagram of the packaging model structure in the packaging reliability optimization method based on position optimization provided by an embodiment of the present invention; Figure 4 is a structural schematic diagram of a packaging reliability optimization system based on position optimization provided by an embodiment of the present invention; Figure 5 It is a schematic diagram of the structure of a computer device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0019] Please refer to Figure 1 , Figure 1 1 is a flowchart of the steps of a packaging reliability optimization method based on position optimization provided by an embodiment of the present invention, wherein the packaging reliability optimization method based on position optimization comprises the following steps: S101 . Acquire a first shape of a packaging substrate and a second shape of a chip to be packaged, wherein the first shape and the second shape include a length and a width.

[0020] S102 , meshing the packaging substrate according to the first shape and the second shape to obtain a meshed packaging substrate, and determining the number of iterations according to the meshing degree of the packaging substrate.

[0021] In step S102, the grid size for gridding the packaging substrate is determined according to the second shapes of the plurality of chips, and the length and width of the plurality of chips are defined as (a 1, b 1) ( a 2, b 2) … a n , b n ), the common divisor of the length and width of the plurality of said chips is k , the grid size and the common divisor k The length and width of the packaging substrate are equal to ( A , B ), the number of chips is n , the number of iterations is N , satisfying the following relationship: .

[0022] In the embodiment of the present invention, the common divisor k It can be determined according to the size of the package substrate. According to the above relationship, the grid size determines the scale of iteration. The higher the degree of gridding, the more positions the chip can be arranged, and the more iterations will be; conversely, the smaller the degree of gridding, the fewer positions the chip can be arranged, and the fewer iterations will be. In the implementation process, since the scale of the chip is generally between 10μm-100μm, in order to achieve chip miniaturization, the common divisor k The lowest common denominator can be used to ensure that the chip layout locations are rich enough.

[0023] S103, arranging the chips on the grid packaging substrate in a random arrangement to obtain a packaging solution.

[0024] Specifically, when the chip is arranged on the grid packaging substrate, the top angle of the chip is aligned with the top angle of the grid in the grid packaging substrate.

[0025] S104, determining whether the packaging solution satisfies a preset chip arrangement rule, if so, executing step S105; if not, returning to step S103.

[0026] For details, please refer to Figure 2 , Figure 2 It is a schematic diagram of chip arrangement positions in a packaging reliability optimization method based on position optimization provided by an embodiment of the present invention, wherein the preset chip arrangement rule is: different chips do not overlap each other when arranged on the grid packaging substrate; A plane coordinate system is constructed with the top corner of the grid packaging substrate as the origin to define any first chip arranged on the grid packaging substrate. R1 , Second chip R2The series of coordinates of the lower left corner and the upper right corner in the plane coordinate system are R1=[x11,y11,x12,y12] , R2=[x21,y21,x22,y22] When any one of the following relations is satisfied, the packaging solution satisfies the preset chip layout rule: R1[2] ≤ R2[0] ; R1[0] ≥ R2[2] ; R1[3] ≤ R2[1] ; R1[1] ≥ R2[3] .

[0027] The above relationship determines the position relationship between any chips by comparing the index values ​​of the series, corresponding to Figure 2 The positional relationship shown in the figure actually corresponds to: First Chip R1 On the right side is the second chip R2 Left side; First Chip R1 On the left side is the second chip R2 Right side; First Chip R1 The upper side is on the second chip R2 lower side; First Chip R1 The lower side is on the second chip R2 upper side.

[0028] Alternatively, in the case of specific requirements, the spacing between chips must not be less than a certain value due to packaging or performance requirements, and the preset chip layout rule may also be: When different chips are arranged on the grid packaging substrate, the spacing between them is not less than the preset packaging spacing; The preset package spacing is GP When any one of the following relations is satisfied, the packaging solution satisfies the preset chip layout rule: R1[2] ≤ R2[0], GP ≤ R2[0] - R1[2] ; R2[2] ≤ R1[0], GP ≤ R1[0] - R2[2] ; R1[3] ≤ R2[1], GP ≤ R2[1] - R1[3] ; R2[3] ≤ R1[1], GP ≤ R1[1] - R2[3] .

[0029] It can be understood that the spacing between different chips is a situation based on the fact that the chips do not overlap each other, so the positional relationship reflected by the above relationship is similar to that in the previous text, namely: First Chip R1 On the right side is the second chip R2 On the left side, and the spacing is greater than the preset packaging spacing; First Chip R1On the left side is the second chip R2 On the right side, and the spacing is greater than the preset packaging spacing; First Chip R1 The upper side is on the second chip R2 The lower side, and the spacing is greater than the preset packaging spacing; First Chip R1 The lower side is on the second chip R2 The upper side of the packaging is provided with a spacing greater than the preset packaging spacing.

[0030] Figure 2 The chip R3 is also included in the grid packaging substrate. It can be understood that when multiple chips are arranged on the grid packaging substrate, any two chips must satisfy the preset chip arrangement rule. During implementation, the specific type of the preset chip arrangement rule can be determined according to actual needs, and since the position data (coordinate series) of the chip is known and does not involve complex mathematical calculations, the judgment process of step S104 can be easily implemented through an automated process.

[0031] S105 . Based on the packaging solution, model the chip and the packaging substrate, and simultaneously model the solder balls used to solder the chip to the packaging substrate, to obtain a packaging model.

[0032] For details, please refer to Figure 3 , Figure 3 It is a schematic diagram of the packaging model structure in the packaging reliability optimization method based on position optimization provided by an embodiment of the present invention. Generally, the position where the chip is welded on the packaging substrate is designed with a corresponding solder pad. In fact, the solder ball is in contact with the solder pad, and its final shape is not a complete sphere.

[0033] S106 , obtaining an average equivalent stress of each of the solder balls based on the packaging model, and obtaining a stress variance value according to the average equivalent stress.

[0034] Specifically, in the embodiment of the present invention, in order to facilitate finite element analysis, the modeling of the solder ball in the packaging model is evenly divided into four equal parts in height, wherein the upper contact area and the lower contact area are the most sensitive areas when stress changes occur in the packaging substrate, so when calculating stress, only the volume average equivalent (mises) stress of the upper contact area and the lower contact area needs to be paid attention to. During implementation, the average equivalent stress can be obtained by force analysis of the packaging model.

[0035] In step S106, the number of solder balls in the package model is defined as n , the average equivalent stress of each solder ball is F 1. F 2. … Fn , the stress variance value is St 2 , satisfying the following relationship: ; .

[0036] S107 , repeating steps S103 - S106 until the number of repetitions is equal to the number of iterations, to obtain a plurality of the packaging solutions and the corresponding stress variance values.

[0037] S108, selecting a corresponding packaging solution as an optimized packaging solution according to the stress variance value with the smallest numerical value, and outputting a packaging position of the chip packaged on the packaging substrate corresponding to the optimized packaging solution.

[0038] The stress variance value measures the degree of stress dispersion of all the solder balls in the packaging model. The packaging solution with the smallest variance value not only meets the requirements of chip layout, but also makes the chip product have a more average solder ball stress during actual assembly, thereby optimizing the chip packaging reliability.

[0039] The beneficial effect achieved by the present invention is that a packaging reliability optimization method based on position optimization is proposed. The method designs a packaging scheme by randomly arranging the chip packages on the substrate, and optimizes the packaging scheme by calculating the variance of the solder ball stress through modeling of the chip, substrate and solder balls. In this way, the solder ball stress during chip packaging can be made as even as possible, thereby improving the reliability of the chip packaging; and the method is easy to realize automated processing, which is conducive to improving the work efficiency of the chip packaging design and manufacturing process.

[0040] The embodiment of the present invention also provides a packaging reliability optimization system 200 based on position optimization, please refer to Figure 4 , Figure 4 is a schematic diagram of the structure of a packaging reliability optimization system based on position optimization provided by an embodiment of the present invention. The packaging reliability optimization system 200 based on position optimization includes: Initialization module 201, used to obtain a first shape of a packaging substrate and a second shape of a chip to be packaged, wherein the first shape and the second shape include a length and a width; A gridding module 202 is used to grid the packaging substrate according to the first shape and the second shape to obtain a gridded packaging substrate, and determine the number of iterations according to the gridding degree of the packaging substrate; A random arrangement module 203 is used to arrange the chips on the grid packaging substrate in a random arrangement manner to obtain a packaging solution; A judgment module 204 is used to judge whether the packaging solution meets the preset chip arrangement rule. If yes, the modeling module 205 is executed; if no, the random arrangement module 203 is returned. A modeling module 205 is used to model the chip and the packaging substrate based on the packaging solution, and simultaneously model the solder balls used to solder the chip to the packaging substrate, to obtain a packaging model; A stress simulation module 206, configured to obtain an average equivalent stress of each solder ball based on the packaging model, and obtain a stress variance value according to the average equivalent stress; An iterative control module 207, configured to repeatedly execute the random arrangement module 203, the judgment module 204, the modeling module 205 and the stress simulation module 206 in sequence until the number of repetitions is equal to the number of iterations, thereby obtaining a plurality of the packaging solutions and the corresponding stress variance values; The output module 208 is used to select a corresponding packaging solution as an optimized packaging solution according to the stress variance value with the smallest numerical value, and output a packaging position of the chip packaged on the packaging substrate corresponding to the optimized packaging solution.

[0041] The random arrangement module 203 is further used to determine the grid size for gridding the packaging substrate according to the second shapes of the plurality of chips, and define the length and width of the plurality of chips as ( a 1, b 1) ( a 2, b 2) … a n , b n ), the common divisor of the length and width of the plurality of said chips is k , the grid size and the common divisor k The length and width of the packaging substrate are equal to ( A , B ), the number of chips is n , the number of iterations is N , satisfying the following relationship: .

[0042] The stress simulation module 206 is also used to define the number of solder balls in the packaging model as: n , the average equivalent stress of each solder ball is F 1. F 2. … F n , the stress variance value is St 2 , satisfying the following relationship: ; .

[0043] The packaging reliability optimization system 200 based on position optimization can implement the steps in the packaging reliability optimization method based on position optimization in the above embodiment, and can achieve the same technical effects. Please refer to the description in the above embodiment and will not be repeated here.

[0044] The embodiment of the present invention also provides a computer device, please refer to Figure 5 , Figure 5 It is a structural diagram of a computer device provided in an embodiment of the present invention. The computer device 300 includes: a memory 302, a processor 301, and a packaging reliability optimization program based on position optimization stored in the memory 302 and executable on the processor 301.

[0045] The processor 301 calls the packaging reliability optimization program based on position optimization stored in the memory 302 to execute the steps of the packaging reliability optimization method based on position optimization provided by the embodiment of the present invention. Figure 1 , specifically including the following steps: S101 . Acquire a first shape of a packaging substrate and a second shape of a chip to be packaged, wherein the first shape and the second shape include a length and a width.

[0046] S102 , meshing the packaging substrate according to the first shape and the second shape to obtain a meshed packaging substrate, and determining the number of iterations according to the meshing degree of the packaging substrate.

[0047] In step S102, the grid size for gridding the packaging substrate is determined according to the second shapes of the plurality of chips, and the length and width of the plurality of chips are defined as ( a 1, b 1) ( a 2, b 2) … a n , b n ), the common divisor of the length and width of the plurality of said chips is k , the grid size and the common divisor k The length and width of the packaging substrate are equal to ( A , B ), the number of chips is n , the number of iterations is N , satisfying the following relationship: .

[0048] S103, arranging the chips on the grid packaging substrate in a random arrangement to obtain a packaging solution.

[0049] S104, determining whether the packaging solution satisfies a preset chip arrangement rule, if so, executing step S105; if not, returning to step S103.

[0050] The preset chip arrangement rule is: different chips do not overlap each other when arranged on the grid packaging substrate; A plane coordinate system is constructed with the top corner of the grid packaging substrate as the origin to define any first chip arranged on the grid packaging substrate. R1 , Second chip R2 The series of coordinates of the lower left corner and the upper right corner in the plane coordinate system are R1=[x11,y11,x12,y12] , R2=[x21,y21,x22,y22] When any one of the following relations is satisfied, the packaging solution satisfies the preset chip layout rule: R1[2] ≤ R2[0] ; R1[0] ≥ R2[2] ; R1[3] ≤ R2[1] ; R1[1] ≥ R2[3] .

[0051] Alternatively, the preset chip layout rule is: When different chips are arranged on the grid packaging substrate, the spacing between them is not less than the preset packaging spacing; The preset package spacing is GP When any one of the following relations is satisfied, the packaging solution satisfies the preset chip layout rule: R1[2] ≤ R2[0], GP ≤ R2[0] - R1[2] ; R2[2] ≤ R1[0], GP ≤ R1[0] - R2[2] ; R1[3] ≤ R2[1], GP ≤ R2[1] - R1[3] ; R2[3] ≤ R1[1], GP ≤ R1[1] - R2[3] .

[0052] S105 . Based on the packaging solution, model the chip and the packaging substrate, and simultaneously model the solder balls used to solder the chip to the packaging substrate, to obtain a packaging model.

[0053] S106 , obtaining an average equivalent stress of each of the solder balls based on the packaging model, and obtaining a stress variance value according to the average equivalent stress.

[0054] In step S106, the number of solder balls in the package model is defined as n , the average equivalent stress of each solder ball isF 1. F 2. … F n , the stress variance value is St 2 , satisfying the following relationship: ; .

[0055] S107 , repeating steps S103 - S106 until the number of repetitions is equal to the number of iterations, to obtain a plurality of the packaging solutions and the corresponding stress variance values.

[0056] S108, selecting a corresponding packaging solution as an optimized packaging solution according to the stress variance value with the smallest numerical value, and outputting a packaging position of the chip packaged on the packaging substrate corresponding to the optimized packaging solution.

[0057] The computer device 300 provided in the embodiment of the present invention can implement the steps in the method in the above embodiment and can achieve the same technical effects. Please refer to the description in the above embodiment and will not be repeated here.

[0058] An embodiment of the present invention also provides a computer-readable storage medium, on which a packaging reliability optimization program based on position optimization is stored. When the packaging reliability optimization program based on position optimization is executed by a processor, the various processes and steps in the method provided by the embodiment of the present invention are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0059] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be realized by instructing the relevant hardware (which can be a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) through a packaging reliability optimization program based on position optimization. The program can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes of the embodiments of the above-mentioned methods. The storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0060] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0061] The embodiments of the present invention are described above in conjunction with the accompanying drawings. What is disclosed is only the preferred embodiment of the present invention. However, the present invention is not limited to the above-mentioned specific implementation manner. The above-mentioned specific implementation manner is only illustrative rather than restrictive. Under the enlightenment of the present invention, ordinary technicians in this field can also make many forms and equivalent changes without departing from the scope of protection of the purpose of the present invention and the claims, all of which are within the protection of the present invention.

Claims

1. A packaging reliability optimization method based on position optimization, characterized in that: The following steps are involved: S101, obtaining a first shape of a packaging substrate and a second shape of a chip to be packaged, wherein the first shape and the second shape include a length and a width; S102, gridding the packaging substrate according to the first shape and the second shape to obtain a gridded packaging substrate, and determining the number of iterations according to the gridding degree of the packaging substrate; S103, arranging the chips on the grid packaging substrate in a random arrangement manner to obtain a packaging solution; S104, determining whether the packaging solution meets the preset chip layout rule, if so, executing step S105; If not, return to step S103; S105, based on the packaging solution, modeling the chip and the packaging substrate, and simultaneously modeling the solder balls for soldering the chip to the packaging substrate, to obtain a packaging model; S106, obtaining an average equivalent stress of each solder ball based on the packaging model, and obtaining a stress variance value according to the average equivalent stress; S107, repeating steps S103-S106 until the number of repetitions is equal to the number of iterations, to obtain a plurality of the packaging solutions and the corresponding stress variance values; S108, selecting a corresponding packaging solution as an optimized packaging solution according to the stress variance value with the smallest numerical value, and outputting a packaging position of the chip packaged on the packaging substrate corresponding to the optimized packaging solution.

2. The packaging reliability optimization method based on position optimization according to claim 1, characterized in that: In step S102, the grid size for gridding the packaging substrate is determined according to the second shapes of the plurality of chips, and the length and width of the plurality of chips are defined as ( a 1, b 1) ( a 2, b 2) … a n , b n ), the common divisor of the length and width of the plurality of said chips is k , the grid size and the common divisor k The length and width of the packaging substrate are equal to ( A , B ), the number of chips is n , the number of iterations is N , satisfying the following relationship: 。 3. The packaging reliability optimization method based on position optimization according to claim 1, characterized in that: In step S106, the number of solder balls in the package model is defined as n , the average equivalent stress of each solder ball is F 1. F 2. … F n , the stress variance value is St 2 , satisfying the following relationship: ； 。 4. The packaging reliability optimization method based on position optimization according to claim 1, characterized in that: The preset chip arrangement rule is: different chips are arranged on the grid packaging substrate without overlapping each other; A plane coordinate system is constructed with the top corner of the grid packaging substrate as the origin to define any first chip arranged on the grid packaging substrate. R1 , Second chip R2 The series of coordinates of the lower left corner and the upper right corner in the plane coordinate system are R1=[x11,y11,x12,y12] , R2=[x21,y21,x22,y22] When any one of the following relations is satisfied, the packaging solution satisfies the preset chip layout rule: R1[2] ≤ R2[0] ； R1[0] ≥ R2[2] ； R1[3] ≤ R2[1] ； R1[1] ≥ R2[3] 。 5. The packaging reliability optimization method based on position optimization according to claim 1, characterized in that: The preset chip layout rule is: When different chips are arranged on the grid packaging substrate, the spacing between them is not less than the preset packaging spacing; A plane coordinate system is constructed with the top corner of the grid packaging substrate as the origin to define any first chip arranged on the grid packaging substrate. R1 , Second chip R2 The series of coordinates of the lower left corner and the upper right corner in the plane coordinate system are R1=[x11,y11,x12,y12] , R2=[x21,y21,x22,y22] , the preset package spacing is GP When any one of the following relations is satisfied, the packaging solution satisfies the preset chip layout rule: R1[2] ≤ R2[0], GP ≤ R2[0] - R1[2] ； R2[2] ≤ R1[0], GP ≤ R1[0] - R2[2] ； R1[3] ≤ R2[1], GP ≤ R2[1] - R1[3] ； R2[3] ≤ R1[1], GP ≤ R1[1] - R2[3] 。 6. A packaging reliability optimization system based on position optimization, characterized in that: include: An initialization module, used to obtain a first shape of a packaging substrate and a second shape of a chip to be packaged, wherein the first shape and the second shape include a length and a width; A gridding module, used for gridding the packaging substrate according to the first shape and the second shape to obtain a gridded packaging substrate, and determining the number of iterations according to the gridding degree of the packaging substrate; A random arrangement module, used to arrange the chips on the grid packaging substrate in a random arrangement manner to obtain a packaging solution; A judging module, used to judge whether the packaging solution meets the preset chip arrangement rule, and if so, execute the modeling module; If not, return to the random arrangement module; A modeling module, used to model the chip and the packaging substrate based on the packaging solution, and simultaneously model the solder balls used to solder the chip to the packaging substrate, to obtain a packaging model; A stress simulation module, used for obtaining an average equivalent stress of each solder ball based on the packaging model, and obtaining a stress variance value according to the average equivalent stress; An iterative control module, used for repeatedly executing the random arrangement module, the judgment module, the modeling module and the stress simulation module in sequence until the number of repetitions is equal to the number of iterations, so as to obtain a plurality of the packaging schemes and the corresponding stress variance values; The output module is used to select a corresponding packaging scheme as an optimized packaging scheme according to the stress variance value with the smallest numerical value, and output the packaging position of the chip packaged on the packaging substrate corresponding to the optimized packaging scheme.

7. The packaging reliability optimization system based on position optimization according to claim 6, characterized in that: The random arrangement module is also used to determine the grid size for gridding the packaging substrate according to the second shapes of the plurality of chips, and define the length and width of the plurality of chips as ( a 1, b 1) ( a 2, b 2) … a n , b n ), the common divisor of the length and width of the plurality of said chips is k , the grid size and the common divisor k The length and width of the packaging substrate are equal to ( A , B ), the number of chips is n , the number of iterations is N , satisfying the following relationship: 。 8. The packaging reliability optimization system based on position optimization according to claim 6, characterized in that: The stress simulation module is also used to define the number of solder balls in the packaging model as n , the average equivalent stress of each solder ball is F 1. F 2. … F n , the stress variance value is St 2 , satisfying the following relationship: ； 。 9. A computer device, characterized in that: include: A memory, a processor, and a packaging reliability optimization program based on position optimization stored in the memory and executable on the processor, wherein the processor implements the steps of the packaging reliability optimization method based on position optimization as described in any one of claims 1 to 5 when executing the packaging reliability optimization program based on position optimization.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a packaging reliability optimization program based on position optimization, and when the packaging reliability optimization program based on position optimization is executed by a processor, the steps in the packaging reliability optimization method based on position optimization as described in any one of claims 1-5 are implemented.

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