Fuse type programmable circuit

Abstract

The invention discloses a fuse type programmable circuit, and relates to the technical field of analog integrated circuits. Comprising a fuse reading and programming circuit and a trial writing and fuse data latching circuit. When the power supply end is powered on, high-level pulse signals appear at the input port ENREAD and the input port # imgabs0 #, and the fuse reads and programming circuit outputs a value corresponding to the fuse F1; output data enter the trial writing and fuse data latch circuit, and after pulse signals of an input port ENREAD and an input port # imgabs1 # are finished, the output data are latched in a latch composed of a fourth P-type MOS tube MP4, a fifth P-type MOS tube MP5, a ninth N-type MOS tube MN9 and a tenth N-type MOS tube MN10 through an eighth N-type MOS tube MN8 and an eleventh N-type MOS tube MN11. According to the invention, the quiescent current in the reading and latching process is very small, so that the problem that the static power consumption of the existing one-time programmable circuit is relatively high is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of analog integrated circuits, and in particular to a fuse type programmable circuit. Background Art

[0002] Integrated circuits are often subject to manufacturing process fluctuations and packaging stress and therefore need to be calibrated after production and packaging using data stored in a one-time programmable circuit.

[0003] In the prior art, a one-time programmable circuit based on polysilicon fuses is a low-power adjustment technology that is easy to implement with CMOS technology and can be programmed after packaging, and is widely used in high-precision analog integrated circuits. The working principle of a one-time programmable circuit based on polysilicon fuses includes: an external control signal is input, and the input signal is processed by a trigger module inside the circuit to generate a trigger pulse for blowing the polysilicon fuse; after the latch receives the trigger pulse, it outputs a high-level blow signal; the timing control module receives the blow signal, combines the internal clock signal, controls the output time of the blow signal, and blows the fuse.

[0004] The defects of the above-mentioned prior art are: when outputting a high-level fuse signal, the fuse state needs to be converted to a high-level output, which increases the processing time of the circuit and increases the static power consumption. Summary of the invention

[0005] Based on this, it is necessary to provide a fuse-type programmable circuit to address the above technical issues.

[0006] The embodiment of the present invention provides a fuse type programmable circuit, comprising: a fuse reading and burning circuit and a test writing and fuse data latching circuit;

[0007] The fuse reading and writing circuit includes: a fuse F1, a fourth N-type MOS transistor MN4, a fifth N-type MOS transistor MN5, a sixth N-type MOS transistor MN6, a first P-type MOS transistor MP1, a second P-type MOS transistor MP2 and a third P-type MOS transistor MP3;

[0008] The gate of the fifth N-type MOS transistor MN5 and the gate of the sixth N-type MOS transistor MN6 are connected to the input port EN_READ; the gate of the third P-type MOS transistor MP3 is connected to the input port The source of the third P-type MOS transistor MP3 is connected to one end of the fuse F1; the gate of the fourth N-type MOS transistor MN4, the drain of the fifth N-type MOS transistor MN5, the drain of the first P-type MOS transistor MP1 and the gate of the second P-type MOS transistor MP2 are connected to the output port DF; the drain of the sixth N-type MOS transistor MN6 and the drain of the second P-type MOS transistor MP2 are connected to the output port

[0009] The test writing and fuse data latch circuit includes: an eighth N-type MOS transistor MN8, a ninth N-type MOS transistor MN9, a tenth N-type MOS transistor MN10, an eleventh N-type MOS transistor MN11, a twelfth N-type MOS transistor MN12, a thirteenth N-type MOS transistor MN13, a fourteenth N-type MOS transistor MN14, a fourth P-type MOS transistor MP4 and a fifth P-type MOS transistor MP5;

[0010] The gate of the eighth N-type MOS transistor MN8 is connected to the output port DF, and the gate of the eleventh N-type MOS transistor MN11 is connected to the output port DF; the gate of the thirteenth N-type MOS transistor MN13 and the gate of the fourteenth N-type MOS transistor MN14 are connected to the input port EN_READ; the gate of the ninth N-type MOS transistor MN9, the drain of the tenth N-type MOS transistor MN10, the drain of the fourteenth N-type MOS transistor MN14, the gate of the fourth P-type MOS transistor MP4, the drain of the fifth P-type MOS transistor MP5, and the drain of the twelfth N-type MOS transistor MN12 are connected to the output port DOUT;

[0011] When the power supply is powered on, the input port EN_READ and the input port A narrow high-level pulse signal appears, the fourth N-type MOS transistor MN4, the fifth N-type MOS transistor MN5, the sixth N-type MOS transistor MN6, the first P-type MOS transistor MP1, the second P-type MOS transistor MP2 and the third P-type MOS transistor MP3 are enabled, and the fuse reading and burning circuit outputs the value corresponding to the fuse F1; the output data is transmitted through the output port DF and the output port Enter the test write and fuse data latch circuit, input port EN_READ and input port After the pulse signal ends, the output data is latched in the latch composed of the fourth P-type MOS transistor MP4, the fifth P-type MOS transistor MP5, the ninth N-type MOS transistor MN9 and the tenth N-type MOS transistor MN10 through the eighth N-type MOS transistor MN8 and the eleventh N-type MOS transistor MN11.

[0012] Optionally, the drain of the fourth N-type MOS transistor MN4 is connected to the source of the sixth N-type MOS transistor MN6 , and the source of the fourth N-type MOS transistor MN4 is grounded.

[0013] Optionally, the fuse reading and writing circuit further includes a first AND gate AND1, a first N-type MOS transistor MN1, a second N-type MOS transistor MN2, and a third N-type MOS transistor MN3;

[0014] One end of the fuse F1 connected to the source of the third P-type MOS transistor MP3 is also connected to the drain of the first N-type MOS transistor MN1, and the other end of the fuse F1, the source of the first P-type MOS transistor MP1 and the source of the second P-type MOS transistor MP2 are connected to the power supply end;

[0015] An input end of the first AND gate AND1 is connected to the input port EN_PRO and the input port DIN, and an output end of the first AND gate AND1 is connected to the gate of the first N-type MOS transistor MN1;

[0016] The gate of the second N-type MOS transistor MN2 is connected to the input bias voltage VB, the drain of the second N-type MOS transistor MN2 is connected to the gate of the first P-type MOS transistor MP1, the drain of the third P-type MOS transistor MP3 and the gate of the third N-type MOS transistor MN3; the drain of the third N-type MOS transistor MN3 is connected to the source of the fifth N-type MOS transistor MN5.

[0017] Optionally, a source of the first N-type MOS transistor MN1 is grounded, a source of the second N-type MOS transistor MN2 is grounded, and a source of the third N-type MOS transistor MN3 is grounded.

[0018] Optionally, the output end of the third AND gate AND3 is connected to the gate of the twelfth N-type MOS transistor MN12, the drain of the eighth N-type MOS transistor MN8 is connected to the source of the thirteenth N-type MOS transistor MN13, and the drain of the eleventh N-type MOS transistor MN11 is connected to the source of the fourteenth N-type MOS transistor MN14.

[0019] Optionally, the source of the eighth N-type MOS transistor MN8, the source of the ninth N-type MOS transistor MN9, the source of the tenth N-type MOS transistor MN10, the source of the eleventh N-type MOS transistor MN11 and the source of the twelfth N-type MOS transistor MN12 are grounded, and the source of the fourth P-type MOS transistor MP4 and the source of the fifth P-type MOS transistor MP5 are connected to the power supply end.

[0020] Optionally, the test write and fuse data latch circuit further includes a second AND gate AND2, a third AND gate AND3 and a seventh N-type MOS transistor MN7;

[0021] An input end of the second AND gate AND2 is connected to the input port DIN and the input port EN_WRIT, and an output end of the second AND gate AND2 is connected to the gate of the seventh N-type MOS transistor MN7;

[0022] The input terminal of the third AND gate AND3 is connected to the input port The output end of the third AND gate AND3 is connected to the gate of the twelfth N-type MOS transistor MN12;

[0023] The drain of the thirteenth N-type MOS transistor MN13, the drain of the ninth N-type MOS transistor MN9, the gate of the tenth N-type MOS transistor MN10, the drain of the fourth P-type MOS transistor MP4 and the gate of the fifth P-type MOS transistor MP5 are connected to the drain of the seventh N-type MOS transistor MN7; the source of the seventh N-type MOS transistor MN7 is grounded.

[0024] Compared with the prior art, the fuse-type programmable circuit provided in the embodiment of the present invention has the following beneficial effects:

[0025] After the power supply end is powered on, the input port EN_READ and the input port A narrow high-level pulse signal appears, and the fuse state can be read in only a short period of time, which reduces the processing time of the circuit; after the reading is completed, the data is latched in the eighth N-type MOS tube MN8 and the eleventh N-type MOS tube MN11, and is latched in the latch composed of the fourth P-type MOS tube MP4, the fifth P-type MOS tube MP5, the ninth N-type MOS tube MN9 and the tenth N-type MOS tube MN10, and the static current in the reading and latching process is very small, which solves the problem of high static power consumption of the existing single-time programmable circuit.

[0026] In addition, when the enable of the input port EN_WRIT is high, the output data in the test write and fuse data latch circuit is changed through the seventh N-type MOS tube MN7 and the twelfth N-type MOS tube MN12, and output through the output port DOUT, avoiding additional digital circuits and reducing static power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A circuit diagram of a fuse-type programmable circuit provided in one embodiment;

[0028] Figure 2 A schematic diagram of a fuse reading and writing circuit of a fuse type programmable circuit provided in one embodiment;

[0029] Figure 3 A schematic diagram of a test writing and fuse data latching circuit of a fuse type programmable circuit provided in one embodiment. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solution and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0031] In one embodiment, a fuse-type programmable circuit is provided, such as Figure 1 As shown, the circuit includes: a fuse reading and burning circuit and a test writing and fuse data latching circuit.

[0032] The input end of the fuse reading and writing circuit is connected to the input port EN_READ, the input port EN_PRO and the input port DIN, and the output end of the fuse reading and writing circuit is connected to the output port DF. The fuse reading and writing circuit is connected to the input end of the test writing and fuse data latch circuit through the input port EN_READ, the input port DIN and the output port DF, and the input end of the test writing and fuse data latch circuit is also connected to the input port EN_WRIT, and the output end of the test writing and fuse data latch circuit is connected to the output port DOUT.

[0033] 1. If Figure 2 As shown, the fuse reading and burning circuit mainly includes: a fuse F1, a first AND gate AND1, a first N-type MOS transistor MN1, a second N-type MOS transistor MN2, a third N-type MOS transistor MN3, a fourth N-type MOS transistor MN4, a fifth N-type MOS transistor MN5, a sixth N-type MOS transistor MN6, a first P-type MOS transistor MP1, a second P-type MOS transistor MP2 and a third P-type MOS transistor MP3.

[0034] The gate of the fifth N-type MOS transistor MN5 and the gate of the sixth N-type MOS transistor MN6 are connected to the input port EN_READ; the gate of the third P-type MOS transistor MP3 is connected to the input port The source of the third P-type MOS transistor MP3 is connected to one end of the fuse F1; the gate of the fourth N-type MOS transistor MN4, the drain of the fifth N-type MOS transistor MN5, the drain of the first P-type MOS transistor MP1 and the gate of the second P-type MOS transistor MP2 are connected to the output port DF; the drain of the sixth N-type MOS transistor MN6 and the drain of the second P-type MOS transistor MP2 are connected to the output port

[0035] The end of the fuse F1 connected to the source of the third P-type MOS transistor MP3 is also connected to the drain of the first N-type MOS transistor MN1. The input end of the first AND gate AND1 is connected to the input port EN_PRO and the input port DIN. The output end of the first AND gate AND1 is connected to the gate of the first N-type MOS transistor MN1.

[0036] The other end of the fuse F1 , the source of the first P-type MOS transistor MP1 , and the source of the second P-type MOS transistor MP2 are connected to the power supply end.

[0037] The gate of the second N-type MOS transistor MN2 is connected to the input bias voltage VB, the drain of the second N-type MOS transistor MN2 is connected to the gate of the first P-type MOS transistor MP1, the drain of the third P-type MOS transistor MP3 and the gate of the third N-type MOS transistor MN3; the drain of the third N-type MOS transistor MN3 is connected to the source of the fifth N-type MOS transistor MN5.

[0038] The source of the first N-type MOS transistor MN1 is grounded, the source of the second N-type MOS transistor MN2 is grounded, and the source of the third N-type MOS transistor MN3 is grounded.

[0039] The drain of the fourth N-type MOS transistor MN4 is connected to the source of the sixth N-type MOS transistor MN6 , and the source of the fourth N-type MOS transistor MN4 is grounded.

[0040] 2. If Figure 3 As shown, the test writing and fuse data latch circuit mainly includes: a second AND gate AND2, a third AND gate AND3, a seventh N-type MOS transistor MN7, an eighth N-type MOS transistor MN8, a ninth N-type MOS transistor MN9, a tenth N-type MOS transistor MN10, an eleventh N-type MOS transistor MN11, a twelfth N-type MOS transistor MN12, a thirteenth N-type MOS transistor MN13, a fourteenth N-type MOS transistor MN14, a fourth P-type MOS transistor MP4 and a fifth P-type MOS transistor MP5.

[0041] The input end of the second AND gate AND2 is connected to the input port DIN and the input port EN_WRIT, and the output end of the second AND gate AND2 is connected to the gate of the seventh N-type MOS transistor MN7. The input end of the third AND gate AND3 is connected to the input port The output end of the third AND gate AND3 is connected to the source of the twelfth N-type MOS transistor MN12.

[0042] The gate of the eighth N-type MOS transistor MN8 is connected to the output port DF, and the gate of the eleventh N-type MOS transistor MN11 is connected to the output port The gate of the thirteenth N-type MOS transistor MN13 and the gate of the fourteenth N-type MOS transistor MN14 are connected to the input port EN_READ; the gate of the ninth N-type MOS transistor MN9, the drain of the tenth N-type MOS transistor MN10, the drain of the fourteenth N-type MOS transistor MN14, the gate of the fourth P-type MOS transistor MP4, the drain of the fifth P-type MOS transistor MP5 and the drain of the twelfth N-type MOS transistor MN12 are connected to the output port DOUT.

[0043] The drain of the eighth N-type MOS transistor MN8 is connected to the source of the thirteenth N-type MOS transistor MN13, and the drain of the eleventh N-type MOS transistor MN11 is connected to the source of the fourteenth N-type MOS transistor MN14. The source of the eighth N-type MOS transistor MN8, the source of the ninth N-type MOS transistor MN9, the source of the tenth N-type MOS transistor MN10, and the source of the eleventh N-type MOS transistor MN11 are grounded, and the source of the fourth P-type MOS transistor MP4 and the source of the fifth P-type MOS transistor MP5 are connected to the power supply terminal.

[0044] The drain of the thirteenth N-type MOS transistor MN13, the drain of the ninth N-type MOS transistor MN9, the gate of the tenth N-type MOS transistor MN10, the drain of the fourth P-type MOS transistor MP4 and the gate of the fifth P-type MOS transistor MP5 are connected.

[0045] The working principle of the above circuit includes:

[0046] The fuse reading is realized as follows: when the power supply is powered on, the input port EN_READ and the input port A narrow high-level pulse signal appears, and the fourth N-type MOS transistor MN4, the fifth N-type MOS transistor MN5, the sixth N-type MOS transistor MN6, the first P-type MOS transistor MP1, the second P-type MOS transistor MP2 and the third P-type MOS transistor MP3 are enabled. The fuse reading and burning circuit outputs the value corresponding to the fuse F1, and it only takes a short time to read the fuse state. If the fuse is not burned, the value corresponding to the fuse is '0'; if the fuse is burned, the value corresponding to the fuse is '1'. The output data is transmitted through the output port DF and the output port Enter the test write and fuse data latch circuit, input port EN_READ and input port After the pulse signal ends, the output data is latched in the latch composed of the fourth P-type MOS transistor MP4, the fifth P-type MOS transistor MP5, the ninth N-type MOS transistor MN9 and the tenth N-type MOS transistor MN10 through the eighth N-type MOS transistor MN8 and the eleventh N-type MOS transistor MN11. After the reading is completed, it is completely turned off, and there is almost no static current.

[0047] In this process, the third P-type MOS transistor MP3, the thirteenth N-type MOS transistor MN13, and the fourteenth N-type MOS transistor MN14 are used as switches, the second N-type MOS transistor MN2 is used as a current source, the first P-type MOS transistor MP1 and the third N-type MOS transistor MN3 form an inverter, and the fourth N-type MOS transistor MN4 and the second P-type MOS transistor MP2 form another inverter.

[0048] The implementation method of the test write is as follows: when the enable of the input port EN_WRIT is high, the output data in the test write and fuse data latch circuit is changed through the seventh N-type MOS transistor MN7 and the twelfth N-type MOS transistor MN12, and output through the output port DOUT.

[0049] The implementation method of fuse burning is as follows: when the enable of the input terminal EN_PRO is '1' and the input terminal DIN is '1', the first N-type MOS transistor MN1 is turned on so that a large current flows through the fuse F1 and the fuse is burned, and the value stored in the fuse thus becomes '1'.

[0050] From the above implementation, it can be seen that the circuit consumes a certain current only when reading the fuse status within a short period of time after power-on, and consumes almost no power after reading, and there is no static current. At the same time, it can latch the read fuse status and perform trial writing, thus avoiding additional digital circuits.

[0051] The above-mentioned embodiments only express several implementation methods of the present invention, and the description is relatively specific and detailed, but it cannot be understood as limiting the scope of the invention patent. It should be pointed out that for ordinary technicians in this field, several modifications and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention.

Claims

1. A fuse-type programmable circuit, characterized in that: include: Fuse reading and writing circuit and test writing and fuse data latching circuit; The fuse reading and writing circuit includes: a fuse F1, a fourth N-type MOS transistor MN4, a fifth N-type MOS transistor MN5, a sixth N-type MOS transistor MN6, a first P-type MOS transistor MP1, a second P-type MOS transistor MP2 and a third P-type MOS transistor MP3; The gate of the fifth N-type MOS transistor MN5 and the gate of the sixth N-type MOS transistor MN6 are connected to the input port EN_READ; the gate of the third P-type MOS transistor MP3 is connected to the input port The source of the third P-type MOS transistor MP3 is connected to one end of the fuse F1; the gate of the fourth N-type MOS transistor MN4, the drain of the fifth N-type MOS transistor MN5, the drain of the first P-type MOS transistor MP1 and the gate of the second P-type MOS transistor MP2 are connected to the output port DF; the drain of the sixth N-type MOS transistor MN6 and the drain of the second P-type MOS transistor MP2 are connected to the output port The test writing and fuse data latching circuit comprises: an eighth N-type MOS transistor MN8, a ninth N-type MOS transistor MN9, a tenth N-type MOS transistor MN10, an eleventh N-type MOS transistor MN11, a twelfth N-type MOS transistor MN12, a thirteenth N-type MOS transistor MN13, a fourteenth N-type MOS transistor MN14, a fourth P-type MOS transistor MP4 and a fifth P-type MOS transistor MP5; The gate of the eighth N-type MOS transistor MN8 is connected to the output port DF, and the gate of the eleventh N-type MOS transistor MN11 is connected to the output port The gate of the thirteenth N-type MOS transistor MN13 and the gate of the fourteenth N-type MOS transistor MN14 are connected to the input port EN_READ; the gate of the ninth N-type MOS transistor MN9, the drain of the tenth N-type MOS transistor MN10, the drain of the fourteenth N-type MOS transistor MN14, the gate of the fourth P-type MOS transistor MP4, the drain of the fifth P-type MOS transistor MP5 and the drain of the twelfth N-type MOS transistor MN12 are connected to the output port DOUT; When the power supply is powered on, the input port EN_READ and the input port When a high-level pulse signal appears, the fourth N-type MOS transistor MN4, the fifth N-type MOS transistor MN5, the sixth N-type MOS transistor MN6, the first P-type MOS transistor MP1, the second P-type MOS transistor MP2 and the third P-type MOS transistor MP3 are enabled, and the fuse reading and burning circuit outputs the value corresponding to the fuse F1; the output data is transmitted through the output port DF and the output port Enter the test write and fuse data latch circuit; input port EN_READ and input port After the pulse signal ends, the output data is latched in the latch composed of the fourth P-type MOS transistor MP4, the fifth P-type MOS transistor MP5, the ninth N-type MOS transistor MN9 and the tenth N-type MOS transistor MN10 through the eighth N-type MOS transistor MN8 and the eleventh N-type MOS transistor MN11.

2. A fuse-type programmable circuit as claimed in claim 1, characterized in that: The drain of the fourth N-type MOS transistor MN4 is connected to the source of the sixth N-type MOS transistor MN6 , and the source of the fourth N-type MOS transistor MN4 is grounded.

3. A fuse-type programmable circuit as claimed in claim 1, characterized in that: The fuse reading and writing circuit also includes a first AND gate AND1, a first N-type MOS transistor MN1, a second N-type MOS transistor MN2, and a third N-type MOS transistor MN3; One end of the fuse F1 connected to the source of the third P-type MOS transistor MP3 is also connected to the drain of the first N-type MOS transistor MN1, and the other end of the fuse F1, the source of the first P-type MOS transistor MP1 and the source of the second P-type MOS transistor MP2 are connected to the power supply end; The input end of the first AND gate AND1 is connected to the input port EN_PRO and the input port DIN, and the output end of the first AND gate AND1 is connected to the gate of the first N-type MOS transistor MN1; The gate of the second N-type MOS transistor MN2 is connected to the input bias voltage VB, the drain of the second N-type MOS transistor MN2 is connected to the gate of the first P-type MOS transistor MP1, the drain of the third P-type MOS transistor MP3 and the gate of the third N-type MOS transistor MN3; the drain of the third N-type MOS transistor MN3 is connected to the source of the fifth N-type MOS transistor MN5.

4. A fuse-type programmable circuit as claimed in claim 3, characterized in that: The source of the first N-type MOS transistor MN1 is grounded, the source of the second N-type MOS transistor MN2 is grounded, and the source of the third N-type MOS transistor MN3 is grounded.

5. A fuse-type programmable circuit as claimed in claim 1, characterized in that: The drain of the eighth N-type MOS transistor MN8 is connected to the source of the thirteenth N-type MOS transistor MN13 , and the drain of the eleventh N-type MOS transistor MN11 is connected to the source of the fourteenth N-type MOS transistor MN14 .

6. A fuse-type programmable circuit as claimed in claim 1, characterized in that: The source of the eighth N-type MOS transistor MN8, the source of the ninth N-type MOS transistor MN9, the source of the tenth N-type MOS transistor MN10, the source of the eleventh N-type MOS transistor MN11 and the source of the twelfth N-type MOS transistor MN12 are grounded, and the source of the fourth P-type MOS transistor MP4 and the source of the fifth P-type MOS transistor MP5 are connected to the power supply end.

7. A fuse-type programmable circuit as claimed in claim 1, characterized in that: The test writing and fuse data latching circuit also includes a second AND gate AND2, a third AND gate AND3 and a seventh N-type MOS transistor MN7; The input end of the second AND gate AND2 is connected to the input port DIN and the input port EN_WRIT, and the output end of the second AND gate AND2 is connected to the gate of the seventh N-type MOS transistor MN7; The input end of the third AND gate AND3 is connected to the input port and the input port EN_WRIT, the output end of the third AND gate AND3 is connected to the gate of the twelfth N-type MOS transistor MN12; The drain of the thirteenth N-type MOS transistor MN13, the drain of the ninth N-type MOS transistor MN9, the gate of the tenth N-type MOS transistor MN10, the drain of the fourth P-type MOS transistor MP4 and the gate of the fifth P-type MOS transistor MP5 are connected to the drain of the seventh N-type MOS transistor MN7; the source of the seventh N-type MOS transistor MN7 is grounded.

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